SCHOOL OF ELECTRONICS

ENGINEERING

COURSE CODE: ECE 1003

COURSE NAME: DIGITAL LOGIC DESIGN

Name: Hitesh Kumar

Reg No.: 23BCE8214

Slot No.: L33+L34

 INDEX

S.No TITLE Signatur Mark

e s
.
1. Verification of Basic gates
in behavioural, structural
and gate-level modelling.
2. Verification of Half Adder
and Half Subtractor, Full
Adder & Full Subtractor.
3. Design and verification of
4-bit Binary Adder and
Subtractor.
4. Design and verification of
3×8 Decoder and 8×3
Encoder.
5. Design and verification of
4×1 MUX and 1×4 DeMUX.
 Lab Experiment-1
Title of the Experiment: Verification of basic gates using behavioural, dataflow and gate-
level modelling.

Objective/Motivation: In this lab, all the basic logic gates are designed based on their truth
tables. The objective will be to test these gate designs on Xilinx simulation tool. The tests
will be performed for all the possible combinations of inputs to verify their functionality.
Moreover, the knowledge gained will be used to design much larger and complex logic
designs.

Apparatus: EDA (Digital Playground)

Logic diagram(s):
AND gate:
Logic
Diagram:

Truth Table:

OR gate:
Logic Diagram:
Truth Table:

NOT gate:
Logic Diagram:

Truth Table:

NAND gate:
Logic Diagram:

Truth Table:
NOR gate:
Logic Diagram:

Truth Table:

XOR gate:
Logic Diagram:

Truth Table:

XNOR gate:
Logic Diagram:
Truth Table:

Verilog Code:
Test Bench: (For all gates)
a=0 ; b=0;
#100
a=0 ; b=1;
#100
a=1 ; b=0;
#100
a=1 ; b=1;
#100

1.Behavioural Model
(a) AND LOGIC –
Code:
Output:

(b) OR LOGIC –
Code:
Output:

(c) NOT LOGIC –

Code:

Output:
2.Data Flow Model
(a) AND LOGIC –
Code:

Output:
(b) OR LOGIC –
Code:

Output:

(c) NOT LOGIC –

Code:
Output:

3.Structural Model
(a) AND LOGIC –
Code:
Output:

(b) OR LOGIC –
Code:
Output:

(c) NOT LOGIC –

Code:
Output:

Observation/Result:
The simulation waveforms are obtained and verified with the expected waveforms.
 Lab Experiment-2
Title of the Experiment: To design adder and subtractor using Verilog code and compare
with their respective truth tables.
Objective/Motivation: In this lab, a half adder, full adder, half subtractor and full subtractor
are designed. The objective will be to test these designs on Xilinx simulation tool. The tests
will be performed for all the possible combinations of inputs to verify their functionality.
Moreover, the knowledge gained will be used to design much larger and complex logic
designs.

Apparatus: EDA (Digital Playground)

Logic diagram(s):
Half Adder:
Logic Diagram and Truth Table:
Half Subtractor:
Logic Diagram and Truth Table

Full Adder:
Logic Diagram And Truth Table
Full Subtractor:
Logic Diagram and Truth Table

Source codes:
Half Adder:
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
xor x1(sum,a,b);
and a1(carry,a,b);
endmodule

Half Subtractor:
module halfsub(diff, borrow, a, b);
output diff;
output borrow;
input a;
input b;
wire abar;
xor x1(diff,a,b);
not n1(abar,a);
and a1(borrow,abar,b);
endmodule

Full Adder:
module full_adder(sum, carry, a, b, c);
output sum;
output carry;
input a;
input b;
input c;
wire s1,t1,t2;
xor x1(s1,a,b);
xor x2(sum,s1,c);
and a1(t1,a,b);
and a2(t2,s1,c);
or o1(carry,t1,t2);
endmodule

Full Subtractor:
module fullsub(diff, borrow, a, b, c);
output diff;
output borrow;
input a;
input b;
input c;
wire abar,q,r,s;
xor x1(diff,a,b,c);
not n1(abar,a);
and a1(q,abar,b);
and a2(r,abar,c);
and a3(s,b,c);
or o1(borrow,q,r,s);
endmodule

Test Bench:
For Half Adder and Half Subtractor:
a=0 ; b=0;
#100
a=0 ; b=1;
#100
a=1 ; b=0;
#100
a=1 ; b=1;
#100

For Full Adder and Full Subtractor:

a=0 ; b=0; c=0;
#100
a=0 ; b=0; c=1;
#100
a=0 ; b=1; c=0;
#100
a=0 ; b=1; c=1;
#100
a=1 ; b=0; c=0;
#100
a=1 ; b=0; c=1;
#100
a=01; b=1; c=0;
#100
a=1; b=1; c=1;
#100

1)Half-Adder

CODE-

OUTPUT-

2)Half-Subtractor
CODE-
Output-

3)Full-Adder
CODE-
OUTPUT-

4)Full-Subtractor
CODE-

OUTPUT-

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
 Lab Experiment-3

Title of the Experiment: To design adder and subtractor using Verilog code and compare
with their respective truth tables.
Objective/Motivation: In this lab, a half adder, full adder, half subtractor and full subtractor
are designed. The objective will be to test these designs on Xilinx simulation tool. The tests
will be performed for all the possible combinations of inputs to verify their functionality.
Moreover, the knowledge gained will be used to design much larger and complex logic
designs.

Apparatus: EDA (Digital Playground)

Logic diagram(s):
4-bit Binary Adder:

4-bit Binary Subtractor:

Source Code:
4-bit binary Adder:
module singleStage (input a, input b, input cin, output s, output cout );
assign s = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
Test bench:
a=4’b1001;
b=4’b1100;
cin = 1’b0;
#100
a=4’b0011;
b=4’b1100;
cin = 1’b1;
#100
a=4’b1110;
b=4’b0011;
cin = 1’b0;
#100
a=4’b1011;
b=4’b1001;
cin = 1’b1;
#100

4-bit binary Subtractor:

module singleStage (input a, input b, input cin, output s, output cout );
assign s = a ^ (~b) ^ cin;
assign cout = (a & (~b)) | (a & cin) | ((~b) & cin);
endmodule
Test bench:
a=4’b1001;
b=4’b1100;
cin = 1’b0;
#100
a=4’b0011;
b=4’b1100;
cin = 1’b1;
#100
a=4’b1110;
b=4’b0011;
cin = 1’b0;
#100
a=4’b1011;
b=4’b1001;
cin = 1’b1;
#100

CODE-

OUTPUT-

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
 Lab Experiment-4
Title of the Experiment: To design Encoder and Decoder using Verilog code and compare
with their respective truth tables.
Objective/Motivation: In this lab, a 8x3 encoder and 3x8 decoder are designed. The
objective will be to test these designs on Xilinx simulation tool. The tests will be performed
for all the possible combinations of inputs to verify their functionality. Moreover, the
knowledge gained will be used to design complex designs.

Apparatus: EDA (Digital Playground)

Logic diagram(s):
Encoder:
Logic Diagram

Truth Table
Decoder:
Logic Diagram

Truth Table

Source code(s):
Encoder:
module Encoder(d0,d1,d2,d3,d4,d5,d6,d7,a,b,c);
input d0,d1,d2,d3,d4,d5,d6,d7;
output a,b,c;
or(a,d4,d5,d6,d7);
or(b,d2,d3,d6,d7);
or(c,d1,d3,d5,d7);
endmodule

Decoder:
module Decoder(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
 assign d0=(~a&~b&~c),
d1=(~a&~b&c),
d2=(~a&b&~c),
d3=(~a&b&c),
d4=(a&~b&~c),
d5=(a&~b&c),
d6=(a&b&~c),
d7=(a&b&c);
endmodule

Test Bench:
Encoder:
module TestModule;
// Inputs
reg d0;
reg d1;
reg d2;
reg d3;
reg d4;
reg d5;
reg d6;
reg d7;
// Outputs
wire a;
wire b;
wire c;
// Instantiate the Unit Under Test (UUT)
Encoder uut (
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
 .d6(d6),
.d7(d7),
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
d0 = 0;
d1 = 0;
d2 = 0;
d3 = 0;
d4 = 0;
d5 = 0;
d6 = 0;
d7 = 0;
// Wait 100 ns for global reset to finish
#100;
d0 = 0;
d1 = 0;
d2 = 0;
d3 = 1;
d4 = 0;
d5 = 0;
d6 = 0;
d7 = 0;
// Wait 100 ns for global reset to finish
#100
end
endmodule
Decoder:
module TestModule;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;
// Instantiate the Unit Under Test (UUT)
Decoder uut (
.a(a),
.b(b),
.c(c),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
 // Wait 100 ns for global reset to finish #100;
a = 1;
b = 0;
c = 1;
// Wait 100 ns for global reset to finish
#100;

end
endmodule

Encoder CODE-

OUTPUT-
Decoder CODE-

OUTPUT-

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
 Lab Experiment-5
Title of the Experiment: To design 4:1 mux and 1:4 demux using Verilog code and compare
with their respective truth tables.
Objective/Motivation: In this lab, a 4:1 mux and 1:4 demux are designed. The objective will
be to test these designs on Xilinx simulation tool. The tests will be performed for all the
possible combinations of inputs to verify their functionality. Moreover, the knowledge gained
will be used to design complex designs.

Apparatus: EDA (Digital Playground)

Logic diagram(s):
4:1 Multiplexer:
Truth Table and Logic Diagram
1:4 De-Multiplexer:

Source Code:
4:1 Multiplexer:
module 4*1mux(i,s,y);
inputs [3:0] i;
inputs [1:0] s;
output y;
reg y;
always@(i or s)
begin
y=0;
case(s)
2’b00 : y=i[0];
2’b01 : y=i[1];
2’b10 : y=i[2];
2’b11 : y=i[3];
default: y=0;
endcase
end
endmodule

1:4 De-Multiplexer:
module 1*4demux(d,s,e);
input e;
inputs [1:0] s;
output [3:0] d;
reg [3:0] d;
always@(e or s)
begin
case(s)
2’b00 : d[0]=e;
2’b01 : d[1]=e;
2’b10 : d[2]=e;
2’b11 : d[3]=e;
Default: d[0]=0;
endcase
endmodule

Test Bench:
4:1 Mux:
i[0] = 1 ; i[1] = 0; i[2] = 0; i[3] = 0; s[0]=0; s[1]=0
#100
i[0] = 0 ; i[1] = 1; i[2] = 0; i[3] = 0 ;s[0]=1; s[1]=0
#100
i[0] = 0 ; i[1] = 0; i[2] = 1; i[3] = 0 ;s[0]=0; s[1]=1
#100
i[0] = 0 ; i[1] = 0; i[2] = 0; i[3] = 1 ;s[0]=1; s[1]=1
#100
1:4 Demux:
s[0]=0; s[1]=0; e=1
#100
s[0]=1; s[1]=0; e=1
#100
s[0]=0; s[1]=1; e=1
#100
s[0]=1; s[1]=1; e=1
#100

Multiplexer Code-

Output-
De-Multiplexer Code-

Output-

Result:
The simulation waveforms are obtained and verified with the expected waveforms.