A

Laboratory File
For
EC319 Design, Testing And Verification
Prepared by

Pruthviraj Mohite (21EC023)

Semester – 6, Branch – B.Tech.
(EC) Academic Year 2023-24
Under the supervision of

Dr. Arpita Patel

Submitted to

Charotar University of Science & Technology

for Partial Fulfillment of the Requirements of the

Degree of Bachelor of Technology in Electronics & Communication

Submitted at

DEPARTMENT OF ELECTRONICS & COMMUNICATION

Faculty of Technology & Engineering, CHARUSAT

Chandubhai S. Patel Institute of Technology

 CERTIFICATE

This is to certify that Mr./Ms. Pruthviraj Mohite

of EC-1 Class, Student ID 21EC023
has satisfactory completed his/her term work in EC319 Design,
Testing and Verification for the Academic Year 2024-25.

Date:
Subject Faculty

Seal of Institute

Chandubhai S Patel Institute of Technology

At: Changa, Ta. Petlad, Dist. Anand, PIN: 388 421. Gujarat
 List of Experiments

Subject: Design,Testing and Verification

No. Name Date Sign

1 Design 4-bit synchronous BCD Counter(without FF),
Design a 4-bit counter(synchronous and a synchronous(ripple) 1/01
counter) using JK FFP.
2 Design and implement a Modulo 10 Synchronous Counter with JK
FF using Verilog. 8/01
3 Design and implement a Universal Shift register using D flip-flop
using Verilog. 22/01
4 Generate clock of 1Mhz with variable duty cycle like 25%, 50% and
75% using Verilog. 12/02
5 Design Frequency divider by 2,3 and 4 using Verilog. 19/02
6 Design and implement Finite state machine to detect a 0101
pattern with mealy state machine(OL & NOL) using Verilog.
26/02
7 Design and implement Finite state machine to detect a 0101
pattern with moore state machine (OL & NOL) using Verilog.
4/03
8 Design a FSM in Verilog HDL to detect sequence 4212, which is a
sequence of four decimal numbers(4,2,1,2) 11/03
9 Design and implement HDL code for Vending Machine which
dispatch single item for a given specification:
Product Price: 75 paisa
Input acceptable currency: 25 paisa and 50 paisa(with and without
change) 18/03
 Experiment-1
Aim: Design 4-bit synchronous BCD Counter (without FF), Design a 4-bit
counter using JK FFP.
Circuit Diagram:

JK Flipflop:
module synchronous_counter(j,k,clk,reset,q);
input j,k,clk,reset;
output reg q;
always@(posedge clk)
begin;
if(reset)
q=0;
else
begin;
case({j,k})
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=(~q);
endcase
end
end

endmodule

Jk Flipflop_tb:
module synchronous_counter_tb;

// Inputs
reg j;
reg k;
reg clk;
reg reset;

// Outputs
wire q;

// Instantiate the Unit Under Test (UUT)

synchronous_counter uut (
.j(j),
.k(k),
.clk(clk),
 .reset(reset),
.q(q)
);
initial begin
// Initialize Inputs
j = 0;
k = 0;
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#10;
reset=0;
j=0;
k=0;
#10;

j=0;
k=1;
#10;

j=1;
k=0;
#10;

j=1;
k=1;
 #10;
// Add stimulus here
end
always#7 clk=~clk;

endmodule

4_bit_Synchronous_counter:
module
four_bit_synchronous_counter(jd,kd,jc,kc,jb,kb,ja,ka,clk,reset,qd,qc,qb,qa);
input jd,kd,jc,kc,jb,kb,ja,ka,clk,reset;
output qd,qc,qb,qa;
wire jb1,ja1;

synchronous_counter j1(.j(jd),.k(kd),.clk(clk),.reset(reset),.q(qd));
synchronous_counter j2(.j(qd),.k(qd),.clk(clk),.reset(reset),.q(qc));
synchronous_counter j3(.j(jb1),.k(jb1),.clk(clk),.reset(reset),.q(qb));
synchronous_counter j4(.j(ja1),.k(ja1),.clk(clk),.reset(reset),.q(qa));

assign jb1=qc&qd;
assign ja1=qb&qc&qd;

endmodule
 4_bit_synchronous_counter_tb:
module four_bit_synchronouscounter_tb;

// Inputs
reg jd;
reg kd;
reg jc;
reg kc;
reg jb;
reg kb;
reg ja;
reg ka;
reg clk;
reg reset;

// Outputs
wire qd;
wire qc;
wire qb;
wire qa;

// Instantiate the Unit Under Test (UUT)

four_bit_synchronouscounter uut (
.jd(jd),
.kd(kd),
.jc(jc),
.kc(kc),
.jb(jb),
.kb(kb),
.ja(ja),
.ka(ka),
.clk(clk),
.reset(reset),
.qd(qd),
.qc(qc),
.qb(qb),
.qa(qa)
);

initial begin
// Initialize Inputs
jd = 0;
kd = 0;
jc = 0;
kc = 0;
jb = 0;
kb = 0;
ja = 0;
ka = 0;
clk = 0;
reset = 1;

// Wait 100 ns for global reset to finish

#10;
reset = 0;
#10;
jd=1;
kd=1;

// Add stimulus here

end

always@(posedge clk)begin
$display("Count = %0d",{qa,qb,qc,qd});
end
always #7 clk=~clk;
endmodule
Output:
Asynchronous(ripple Counter)
JK Flipflop code:
4 bit ripple counter using verilog Code:

module ripple(input jd,kd,jc,kc,jb,kb,ja,ka,clk,reset, output qd,qc,qb,qa);

jk_ff j1(.j(jd),.k(kd),.clk(clk),.reset(reset),.q(qd));
jk_ff j2(.j(jc),.k(kc),.clk(qd),.reset(reset),.q(qc));
jk_ff j3(.j(jb),.k(kb),.clk(qc),.reset(reset),.q(qb));
jk_ff j4(.j(ja),.k(ka),.clk(qb),.reset(reset),.q(qa));
endmodule

Testbench:
module ripple_tb;

// Inputs
reg jd;
reg kd;
reg jc;
reg kc;
reg jb;
reg kb;
reg ja;
reg ka;
reg clk;
reg reset;

// Outputs
wire qd;
wire qc;
wire qb;
wire qa;

// Instantiate the Unit Under Test (UUT)

ripple uut (
.jd(jd),
.kd(kd),
.jc(jc),
.kc(kc),
.jb(jb),
.kb(kb),
.ja(ja),
.ka(ka),
.clk(clk),
.reset(reset),
.qd(qd),
.qc(qc),
.qb(qb),
.qa(qa)
);

initial begin
// Initialize Inputs
jd = 0;
 kd = 0;
jc = 0;
kc = 0;
jb = 0;
kb = 0;
ja = 0;
ka = 0;
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
reset = 0;
jd=1;
kd=1
; #10;
jc=1;
kc=1
;
#10;
jb=1;
kb=1;
#10;
ja=1;
ka=1
;
#10;
end
 always @(negedge clk) begin
$display("Count = %d",{qa,qb,qc,qd});
end
always #7 clk = ~clk;
endmodule

Output:

Conclusion: We have perform 4 bit synchronous and ripple(Asynchronous)

counter with jk flipflop using Verilog code and testbench.
 Experiment-2

Aim: Design mod 10 synchronous Counter with JK Flipflop.

Circuit Diagram:

JK Flipflop:
module mod10_synchronouscounter(j,k,clk,reset,q);
input j,k,clk,reset;
output reg q;
always @(posedge clk)
begin;
if(reset)
q=0;
else
begin;
case({j,k})
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=(~q);
endcase
end
end

endmodule
 JK Flipflop_tb:
module mod10_synchronouscounter_tb;

// Inputs
reg j;
reg k;
reg clk;
reg reset;

// Outputs
wire q;

// Instantiate the Unit Under Test (UUT)

mod10_synchronouscounter uut (
.j(j),
.k(k),
.clk(clk),
.reset(reset),
.q(q)
);

initial begin
// Initialize Inputs
j = 0;
k = 0;
clk = 0;
reset = 1;

// Wait 100 ns for global reset to finish

#10;
reset = 0;
j=0;
k=0;
#10;
j=0;
k=1;
#10;
j=1;
k=0;
#10;
j=1;
k=1;
// Add stimulus here

end
always #7 clk=~clk;

endmodule

Mod 10 synchronous Counter:

module
mod10_main_synchronous_counter(jd,kd,jc,kc,jb,kb,ja,ka,clk,reset,qd,qc,qb,qa
);
input jd,kd,jc,kc,jb,kb,ja,ka,clk,reset;
output qd,qc,qb,qa;
wire jc1,jb1,ja1;

mod10_synchronouscounter j1(.j(jd),.k(kd),.clk(clk),.reset(reset),.q(qd));
mod10_synchronouscounter j2(.j(jc1),.k(jc1),.clk(clk),.reset(reset),.q(qc));
mod10_synchronouscounter j3(.j(jb1),.k(jb1),.clk(clk),.reset(reset),.q(qb));
mod10_synchronouscounter j4(.j(ja1),.k(qd),.clk(clk),.reset(reset),.q(qa));

assign jc1=(~qa)&qd;
assign jb1=qc&qd;
assign ja1=qb&qc&qd;

endmodule
 Mod 10 synchronous Counter_tb:
module mod10_main_synchronous_counter_tb;

// Inputs
reg jd;
reg kd;
reg jc;
reg kc;
reg jb;
reg kb;
reg ja;
reg ka;
reg clk;
reg reset;

// Outputs
wire qd;
wire qc;
wire qb;
wire qa;

// Instantiate the Unit Under Test (UUT)

mod10_main_synchronous_counter uut
(
.jd(jd),
.kd(kd),
.jc(jc),
.kc(kc),
.jb(jb),
.kb(kb),
.ja(ja),
.ka(ka),
.clk(clk),
.reset(reset),
.qd(qd),
.qc(qc),
.qb(qb),
.qa(qa)
);

initial begin
// Initialize Inputs
jd = 0;
kd = 0;
jc = 0;
kc = 0;
jb = 0;
kb = 0;
ja = 0;
ka = 0;
clk = 0;
reset = 1;

// Wait 100 ns for global reset to finish

#10;
reset = 0;
#10;
jd=1;
kd=1;
// Add stimulus here

end
always@(posedge clk)begin
$display("Count = %0d",{qa,qb,qc,qd});
end
always #7 clk=~clk;

endmodule
 Output:

Conclusion: We have perform Mod 10 Synchronous Counter With Jk Flipflop

using Verilog code and testbench.
 Experiment-3
Aim: Design and implement a 4 BIT Universal shift register.

State diagram:

VerilogCode:
module usr(
input wire clk, reset,
input wire [1:0] ctrl,
input wire [3:0] d,
output wire [3:0] q
);

reg[3:0] r_reg, r_next;

always @(posedge clk, posedge reset)
if (reset)
r_reg<=0;
else
r_reg<=r_next;

always @(*)
case(ctrl)
2'b00: r_next=r_reg;

2'b10: r_next={r_reg[2:0],r_reg[3]};
2'b01: r_next={r_reg[0],r_reg[3:1]};
default: r_next=d;
endcase
assign q=r_reg;
endmodule

Testbench:
module usr_tb;

// Inputs
reg clk;
reg reset;
reg [1:0] ctrl;
reg [3:0] d;

// Outputs
wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

maulik uut (
 .clk(clk),
.reset(reset),
.ctrl(ctrl),
.d(d),
.q(q)
);

initial begin
// Initialize Inputs
clk = 0;
reset = 0;

ctrl = 0;
d = 0;

// Wait 100 ns for global reset to finish

#10;

d=4'b1001;
ctrl=2'b11; //parallel loading data=1001

#10;
ctrl = 2'b01; //right shifting operation on 1001

#40;

ctrl=2'b10; //left shifting operation on 1001

 #40;
ctrl=2'b00;

// Add stimulus here

end
always #5 clk=~clk;
endmodule
Output:

Conclusion: We have perform USR(Universal shift Register) using Verilog.

 Experiment-4
Aim: Generate clock with variable duty cycle like 20% ,40%, and 60% using
Verilog.
Verilog Code:
module dutycycle(clk,out); //pwm with variable duty cycle(20,40,60)
input clk;
output [3:0]out;

reg [127:0]counter=0;

always@(posedge clk)
begin
if(counter < 128'd100)
counter<=counter+1;
else
counter<=0;
end

assign out[0] = (counter<20)?1:0; //20% duty cycle

assign out[1] = (counter<40)?1:0; //40% duty cycle
assign out[2] = (counter<60)?1:0; //60% duty cycle
assign out[3] = (counter<80)?1:0; //80% duty cycle
endmodule
 Testbench:
module dutycycle1_tb;

// Inputs
reg clk;

// Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)

dutycycle uut (
.clk(clk),
.out(out)
);

initial begin
// Initialize Inputs
clk = 0;

// Wait 100
ns for global
reset to
end finish #100;
// Add stimulus here
always #5 clk=~clk;

endmodule
Output:(20% duty Cycle)

(40% Duty Cycle)

(60% Duty Cycle)

(80% Duty Cycle)

Conclusion: We have perform to generate variable duty cycle like 20%, 40%,
and 60% using Verilog code and testbench.
 Experiment-5
Aim: Design Frequency divider by 2,3 and 4 using Verilog.
Verilog Code:
module freqdiv(clk,clk2,clk4,clk30,clk31,clk3);
input clk;
reg [127:0]count=0;
reg [127:0]count1=0;
reg [127:0]count2=0;
reg [127:0]count3=0;
output reg clk2=0,clk4=0,clk30=0,clk31=1;
output clk3;
always @(posedge clk) // div 2
begin
count=count+1
; if(count==1)
begin
clk2=~clk2;
count=0;
end
end

always @(posedge clk) // div 4

begin
count1=count1 + 1;
if(count1==2)
begin
clk4=~clk4;
count1=0;
end
end

always @(posedge clk) //div 3 pos count

begin
count2=count2 + 1;
if(count2==1)
begin
clk30=~clk30
; count2=0;
end
end

always @(negedge clk) //div 3 neg count

begin
count3=count3 + 1;
if(count3==1)
begin
clk31=~clk31
; count3=0;
end
end

assign clk3 = (clk31|clk30); // addition of clks

endmodule
 Testbench:
module freqdiv2_tb;

// Inputs
reg clk;

// Outputs
wire clk2;
wire clk4;
wire clk30;
wire clk31;
wire clk3;

// Instantiate the Unit Under Test (UUT)

freqdiv uut (
.clk(clk),

.clk2(clk2),
.clk4(clk4),
.clk0(clk0),
.clk31(clk31),
.clk3(clk3)
);

initial begin
// Initialize Inputs
clk = 0;
 // Wait 100 ns for global reset to finish
#10;

// Add stimulus here

end
always #5 clk=~clk;
endmodule

Output:

Conclusion: We have perform frequency divider by 2,3,4 using verilod and

testbench.
 Experiment-6
Aim: Design and implement Finite state machine to detect a 0101 pattern with
melay state machine (OL & NOL) using Verilog.
State diagram for Non-Overlapping:

Verilog Code:
module melay(clk,rst,x,z); // 0101 sequence Non-Overlapping
input clk,rst,x;
output reg z;

parameter [1:0]s0=2’b00;
parameter [1:0]s1=2’b01;
parameter [1:0]s2=2’b10;
parameter [1:0]s3=2’b11;

reg [1:0]c_state;
reg [1:0]n_state;

always@(posedge clk)
begin
if(rst==0)
begin
c
_
end s
t
a
t
e
=
0
;
n
_
s
t
a
t
e
=
0
;
else
begin
c_state=n_state;
case(c_state)
s0:if(x==0)
begin
n
_
s
end else begin t
a
end s1:if(x==1) t
begin e
=
s
end else begin 1
;
end s2:if(x==0) z
begin =
0
;
end else begin

end s3:if(x==1)
begin n
_
s
t
a
t
e
=
s
0
;
z
=
0
;
n =
_ s
s 3
t ;
a z
t =
e 0
= ;
s
2
;
z n
= _
0 s
; t
a
t
e
n =
_ s
s 0
t ;
a z
t =
e 0
= ;
s
1
;
z
=
0
;

n
_
s
t
a
t
e
 n
_
end else begin s
t
a
end endcase t
e
=
s
end end 0
;
z
=
1
;

n
_
s
t
a
t
e
=
s
0
;
z
=
0
;

endmodule

TestBench:
module melay_tb;

// Inputs
reg clk;
reg rst;
reg x;

// Outputs
wire z;

// Instantiate the Unit Under Test (UUT)

melay uut (
.clk(clk),
.rst(rst),
.x(x),
.z(z)
);

initial begin
// Initialize Inputs
clk = 0;
rst = 0;
x = 0;
 // Wait 100 ns for global reset to finish
#10;
rst=1;
#10;
x=0;
#10;
x=1;
#10;
x=0;
#10;
x=1;
#10;

// Add stimulus here

end
always #5 clk=~clk;

endmodule

Output:
 State Diagram for Overlapping:

Verilog Code:
module melay_ol(clk,rst,in,out); //melay 0101 Overlapping
input clk,rst,in;
output reg out;

parameter [1:0]s0=2'b00;
parameter [1:0]s1=2'b01;
parameter [1:0]s2=2'b10;
parameter [1:0]s3=2'b11;

reg[1:0]c_state;
reg[1:0]n_state;

always @(posedge clk)

begin
if(rst==0)
begin
c_state=s0;
n_state=s0
; out=0;
end

else
begin
c_state=n_state;
case(c_state)

s0:if(in)
begin
c_state=s0;
n_state=s0
; out=0;
end

else
begin
c_state=s0;
n_state=s1
; out=0;
end

s1:if(in)
begin
c_state=s1;
n_state=s2
; out=0;
end

else
begin
c_state=s1;
n_state=s1
; out=0;
end

s2:if(in)
begin
c_state=s2;
n_state=s0
; out=0;
end

else
begin
c_state=s2;
n_state=s3
; out=0;
end

s3:if(in)
begin
c_state=s3;
n_state=s2; //2-bit overlap
out=1;//output =1
end

else
begin
c_state=s3;
n_state=s0
; out=0;
end

endcase
end
end
endmodule

TestBench:
module melay_ol_tb;

// Inputs
reg clk;
reg rst;
reg in;

// Outputs
wire out;

// Instantiate the Unit Under Test (UUT)

melay_ol uut (
.clk(clk),
.rst(rst),
 .in(in),
.out(out)
);

initial begin
// Initialize Inputs
clk = 0;
rst = 0;
in = 0;

// Wait 100 ns for global reset to finish

#10;
rst = 1;
in = 0;
#10;
in = 1;
#10;
in = 0;
#10;
in = 1;
#10;
in = 0;
#10;

// Add stimulus here

end
always #5 clk=~clk;
endmodule
 Output:

Conclusion: We have perform Mealy FSM with OL and Non-OL using Verilog.
 Experiment-7
Aim: Design and implement Finite state machine to detect a 0101 pattern with
moore state machine (OL & NOL) using Verilog.

State Diagram:

Verilog Code:

module Moore0101(clk,rst,in,out);
input clk,rst,in;
output reg out;

parameter [2:0]S0=3'b000;
parameter [2:0]S1=3'b001;
parameter [2:0]S2=3'b010;
parameter [2:0]S3=3'b011;
parameter [2:0]S4=3'b100;

reg [2:0]c_state;
reg [2:0]n_state;
always@(posedge clk) begin
if(rst==1)
begin
out=3'b000;
c_state=S0;
n_state=S0;
end

else
begin
c_state=n_state;
case(c_state)

S0 : if(in)
begin
c_state=S0;
n_state=S0;
out=0;
end

else
begin
c_state=S0;
n_state=S1
; out=0;
end

S1 : if(in)
begin
c_state=S1;
n_state=S2;
out=0;

end

else
begin
c_state=S1;
n_state=S1
; out=0;
end

S2 : if(in)
begin
c_state=S2;
n_state=S0;
out=0;
end

else
begin
c_state=S2
;
n_state=s3
; out=0;
end

S3 : if(in)
begin
c_state=s3;
n_state=S4;
out=0;
end
else
c_state=S3;
n_state=S0
; out=0;
end

S4 : if(in)
begin
c_state=S4;
n_state=S0;
out=1;
end
else
begin
c_state=S4;
n_state=S0;
out=1;
end
end
endcase
end
endmodule

Testbench:
module Moore0101_tb;

// Inputs reg clk; reg rst; reg in;

// Outputs wire out;

// Instantiate the Unit Under Test (UUT) Moore0101 uut (

.clk(clk),
.rst(rst),
.in(in),
.out(out)
);

initial begin
// Initialize Inputs clk = 0;

rst = 1;
in = 0;

#10;
rst = 0;
#10;

in = 0;
#10;

in = 1;
#10;

in = 0;
#10;

in = 1;
#10;
in = 0;
#10;

in = 1;

#10;

in = 0;
#10;

in = 0;
#10;

in = 1;
#10;

in = 0;
#10;
in = 1;
#10;

in = 0;
#10;

// Add stimulus here

end
always #5 clk = ~clk;
endmodule

Output:

Conclusion: We have perform moore FSM with OL and NOL using Verilog.
 Experiment-8
Aim: Design a FSM in Verilog HDL to detect sequence 4212, which is a
sequence of four decimal numbers(4,2,1,2).
State diagram:

Verilog Code:
module seq(clk,rst,in,out);

input clk,rst;
input [2:0]in;
output reg out;

parameter [1:0]S0=2'b00;
parameter [1:0]S1=2'b01;
parameter [1:0]S2=2'b10;
parameter [1:0]S3=2'b11;
reg [1:0]c_state;
reg [1:0]n_state;

always@(posedge clk)
begin
if(rst==1)
begin
out=2'b00;
c_state=S0;
n_state=S0;
end

else
begin
c_state=n_state;

case(c_state)
S0 : if(in==3'b100)

begin
c_state=S0;
n_state=S1;
out=0;
end

else if(in==3'b010|in==3'b001)
begin
c_state=S0;
n_state=S0;
out=0;
end

else
begin
c_state=S0;
n_state=S0
; out=0;
end

S1:if(in==3'b100)

begin
c_state=S1;
n_state=S1;
out=0;
end

else if(in==3'b010)

begin
c_state=S1;
n_state=S2;
out=0;
end

else if(in==3'b001)

begin
c_state=S1;
n_state=S0;
out=0;
end

else
begin
c_state=S1;
n_state=S0
; out=0;
end

S2 : if(in==3'b100)

begin
c_state=S2;
n_state=S1;
out=0;
end
else if(in==3'b010)

begin
c_state=S2;
n_state=S0;
out=0;
end

else if(in==3'b001)

begin
c_state=S2;
n_state=S3;
out=0;
end

else
begin
c_state=S2;
n_state=S0
; out=0;
end

S3 : if(in==3'b100)

begin
c_state=S3;
n_state=S1
; out=0;
end

else if(in==3'b010)

begin
c_state=S3;
n_state=S0;
out=1;
end

else if(in==3'b001)

begin
c_state=S3;
n_state=S0;
out=0;
end

else
begin
c_state=S3;
n_state=S0
; out=0;
end

endcase

end
end
endmodule

Testbench:
module seq_tb;

// Inputs
reg clk;
reg rst;
reg [2:0] in;

// Outputs
wire out;

// Instantiate the Unit Under Test (UUT)

seq uut (
.clk(clk),
.rst(rst),
.in(in),
.out(out)
);
 initial begin
// Initialize Inputs
clk = 0;
rst = 1;

in = 3'b000;
#10;

rst = 0;
#10;
in = 3'b100;
#10;
in = 3'b010;
#10;
in = 3'b001;
#10;
in = 3'b010;
#10;

in = 3'b100;
#10;
in = 3'b001;
#10;
in = 3'b010;
#10;
in = 3'b000;
#10;

in = 3'b100;
#10;
in = 3'b010;
#10;
in = 3'b001;
#10;
in = 3'b010;
#10;

in = 3'b100;
#10;
in = 3'b001;
#10;
in = 3'b100;
#10;
in = 3'b010;
#10;
in = 3'b001;
#10;
in = 3'b010;
#10;
end
always #5 clk = ~clk;
endmodule
 Output:

Conclusion: We have detected 4212 sequence using mealy FSM using Verilog.
 Experiment-9
Aim: Design and implement HDL code for Vending Machine which
dispatch single item for a given specification:
Product Price: 75 paisa
Input acceptable currency: 25 paisa and 50 paisa(with and without change)
State diagram:

Verilog Code:
module vending_machine(clk,rst,in,out);

input clk,rst;
input [1:0]in;
output reg out;

parameter [1:0]S0=2'b00;
parameter [1:0]S1=2'b01;
parameter [1:0]S2=2'b10;
reg [1:0]c_state;
reg [1:0]n_state;

always@(posedge clk)
begin
if(rst==1)
begin
out=2'b00;
c_state=S0;
n_state=S0;
end

else
begin
c_state=n_state;

case(c_state)
S0 : if(in==2'b01)

begin
c_state=S0;
n_state=S1;
out=0;
end
else if(in==2'b00)

begin
c_state=S0;
n_state=S0;
out=0;
end

else if(in==2'b10)

begin
c_state=S0;
n_state=S2;
out=0;
end

S1 : if(in==2'b00)

begin
c_state=S1;
n_state=S0;
out=0;
end

else if(in==2'b10)
begin
c_state=S1;
n_state=S0;
out=1;
end

else if(in==2'b01)

begin
c_state=S1;
n_state=S2;
out=0;
end

S2 : if(in==2'b00)

begin
c_state=S2;
n_state=S0;
out=0;
end

else if(in==2'b10)

begin
c_state=S2;
n_state=S0
; out=1;
end

else if(in==2'b01)

begin
c_state=S2;
n_state=S0;
out=1;
end

endcase

end
end

endmodule
 Testbench:
module vending_machine_tb;

// Inputs
reg clk;
reg rst;
reg [1:0] in;

// Outputs
wire out;

// Instantiate the Unit Under Test (UUT)

vending_machine uut (
.clk(clk),

.rst(rst),
.in(in),
.out(out)
);

initial begin
// Initialize Inputs
clk = 0;
rst = 1;

in = 2'b00;
#10;
rst = 0;
#10;

in = 2'b01;
#10;

in = 2'b10;
#10;

in = 2'b10;
#10;

in = 2'b01;
#10;

in = 2'b01;
#10;

in = 2'b01;
#10;

in = 2'b01;
#10;

in = 2'b10;
#10;

end

always #5 clk = ~clk;

endmodule

Output:

Conclusion: We have perform Vending machine using mealy FSM.