Module-2:

MOSFET Scaling & Small

Geometry Effects
 MOSFET Scaling
 The design of high-density chips in MOS VLSI (Very Large-Scale
Integration) technology requires that the packing density of MOSFETs
used in the circuits is as high as possible and, consequently, that the sizes
of the transistors are as small as possible.
 The reduction of the size, i.e., the dimensions of MOSFETs, is commonly
referred to as scaling.
 It is expected that the operational characteristics of the MOS transistor
will change with the reduction of its dimensions.
 There are two basic types of size-reduction strategies:
 Full Scaling (also called constant-field scaling)
 Constant voltage scaling.
 Both types of scaling approaches will be shown to have unique effects
upon the operating characteristics of the MOS transistor.
 Scaling of MOS transistors is concerned with systematic reduction of overall
dimensions of the devices as allowed by the available technology, while
preserving the geometric ratios found in the larger devices.
 To describe device scaling, we introduce a constant scaling factor S > 1.
 All horizontal and vertical dimensions of the large-size transistor are then
divided by this scaling factor to obtain the scaled device.
 The recent history of reducing feature sizes for the typical CMOS gate-array
process.

 It is seen that a new generation of manufacturing technology replaces the

previous one about every two or three years, and the down-scaling factor S of
the minimum feature size from one generation to the next is about 1.2 to 1.5
The reduction of key dimensions on a typical MOSFET, together with the
corresponding increase of the doping densities.
 Full Scaling (Constant-field Scaling)
 This scaling option attempts to preserve the magnitude of internal
electric fields in the MOSFET, while the dimensions are scaled down by a
factor of S.
 To achieve this goal, all potentials must be scaled down proportionally,
by the same scaling factor.
 This potential scaling also affects the threshold voltage Vt0
 Finally, the Poisson Equation describing the relationship between charge
densities and electric fields dictates that the charge densities must be
increased by a factor of S in order to maintain the field conditions
The scaling factors for all significant dimensions, potentials, and doping densities
of the MOS transistor
 Gate Oxide Capacitance
 It will be assumed that the surface mobility µn is not significantly
affected by the scaled doping density.

 The gate oxide capacitance per unit area, on the other hand, is
changed as follows.
 Linear & Saturation-mode Drain Current
 The aspect ratio W/L of the MOSFET will remain unchanged under
scaling.
 The transconductance parameter kn’ will also be scaled by a factor of S.
 Terminal voltages are scaled down by the factor S
 Power Dissipation of The MOSFET

Scaling reduces both the drain current and the drain-to-source voltage by a
factor of S
Hence, the power dissipation of the transistor will be reduced by the factor by
2
 Constant-Voltage Scaling
 In constant-voltage scaling, all dimensions of the MOSFET are reduced by a
factor of S, as in full scaling. On the other hand, the power supply voltage and
the terminal voltages remain unchanged.

 The doping densities must be increased by a factor of S2 in order to preserve

the charge-field relations.
Linear & Saturation-mode Drain Current
Power
 To summarize, constant-voltage scaling may be preferred over full (constant-field) scaling in
many practical cases because of the external voltage-level constraints.
 However, that constant-voltage scaling increases the drain current density by a factor S and
the power density by a factor of S3.
 This large increase in current and power densities may eventually cause serious reliability
problems for the scaled transistor, such as electromigration, hot-carrier degradation, oxide
breakdown, and electrical over-stress.
 MOS Small-Geometry Effects.
As the device dimensions are systematically reduced through full
scaling or constant-voltage scaling, various physical limitations
become increasingly more prominent, and ultimately restrict the
amount of feasible scaling for some device dimensions.
Consequently, scaling may be carried out on a certain subset of
MOSFET dimensions in many practical cases.
The current equations must be modified accordingly. In the following,
we will briefly investigate some of these small-geometry effects
 Short-Channel Effects
 A MOS transistor is called a short-channel device if
its channel length is on the same order of
magnitude as the depletion region thicknesses of
the source and drain junctions.
 Alternatively, a MOSFET can be defined as a short-
channel device if the effective channel length Leff is
approximately equal to the source and drain
junction depth Xj
 The short-channel effects that arise in this case are
attributed to two physical phenomena:
 (i) The limitations imposed on electron drift
characteristics in the channel
 (ii) The modification of the threshold voltage
due to the shortening channel length.
The lateral electric field EY along the channel increases, as the
effective channel length Leff is decreased.
 At, lower field values, Electron drift velocity Vd α E (electric field)
 Drift velocity tends to saturate at high channel electric fields.
For channel electric fields of E = 105 V/cm and higher, the electron
drift velocity in the channel reaches a saturation value of about
Vd(sat) = 107 'cm/s.
This velocity saturation has very significant implications upon the
current-voltage characteristics of the short-channel MOSFET.
Consider the saturation-mode drain current, under the assumption that carrier velocity
in the channel has already reached its limit value.
The effective channel length Leff will be reduced due to channel-length shortening

The channel-end voltage is equal to VDSAT, the saturation current can be found as
follows:

 Carrier velocity saturation actually reduces the saturation-mode current below the
current value predicted by the conventional long-channel current equations.

 The current is no longer a quadratic function of the gate-to-source voltage VGS, and it
is virtually independent of the channel length.

 Under these conditions, the device is defined to be in saturation when the carrier
velocity in the channel approaches about 90% of its limit value.
In short-channel MOS transistors, the carrier velocity in the channel is also a
function of the normal (vertical) electric-field component Ex.
Since the vertical field influences the scattering of carriers (collisions
suffered by the carriers) in the surface region, the surface mobility is
reduced with respect to the bulk mobility.
The dependence of the surface electron mobility on the vertical electric field
can be expressed by the following empirical formula

 where µno is the low-field surface electron mobility and is an empirical

factor. For a simple estimation of field-related mobility reduction can be
approximated by
 Modification of the Threshold Voltage Due To
Short-channel Effects.
 The channel depletion region was assumed to be
created only by the applied gate voltage, and the
depletion regions associated with the drain and
source pn-junctions were neglected.
 The shape of this gate-induced bulk (channel)
depletion region was assumed to be rectangular,
extending from the source to the drain.
 In short-channel MOS transistors, however, the n+
drain and source diffusion regions in the p-type
substrate induce a significant amount of depletion
charge;
 The threshold voltage value for long channel
Threshold Voltage for long channel MOSFET’s MOSFET’s is larger than the actual threshold voltage
of the short-channel MOSFET.
 The simplified geometry of the gate-induced bulk
depletion region and the pn-junction depletion regions in
a short-channel MOS transistor.
 Bulk depletion region is assumed to have an asymmetric
trapezoidal shape, instead of a rectangular shape, to
represent accurately the gate-induced charge.
 The drain depletion region is expected to be larger than
the source depletion region because the positive drain-
to-source voltage reverse-biases the drain-substrate
junction.
 A significant portion of the total depletion region charge
under the gate is actually due to the source and drain
junction depletion, rather than the bulk depletion
induced by the gate voltage.
 Since the bulk depletion charge in the short-channel
device is smaller than expected, the threshold voltage
expression must be modified to account for this
reduction.
 where VT0 is the zero-bias threshold voltage calculated using the conventional long channel
formula
 ΔVt0 is the threshold voltage shift (reduction) due to the short-channel effect.
 The reduction term actually represents the amount of charge differential between a rectangular
depletion region and a trapezoidal depletion region.
 Let ΔLS and ΔLD represent the lateral extent of the depletion regions associated with the source
junction and the drain junction, respectively.
 Then, the bulk depletion region charge contained within the trapezoidal region is
 To calculate Δ LS and Δ LD, we will use the simplified
geometry.
 Here, Xds and XdD represent the depth of the pn-j unction
depletion regions associated with the source and the drain,
respectively.
 The edges of the source and drain diffusion regions are
represented by quarter-circular arcs, each with a radius
equal to the junction depth Xj.
 The vertical extent of the bulk depletion region into the
substrate is represented by Xdm. The junction depletion
region depths can be approximated by
Similarly, the length ΔLS can also be found as follows:

The amount of threshold voltage reduction ΔVT0 due to short-channel effects can be
found as:

The threshold voltage shift term is proportional to (Xj/L). As a result, this term becomes more
prominent for MOS transistors with shorter channel lengths, and it approaches zero for long-
channel MOSFETs where L >> Xj
Consider an n-channel MOS process with the following parameters: substrate
doping density NA = 1016 cm-3 , polysilicon gate doping density
ND (gate) = 2 x 1020 cm-3, gate oxide thickness tox = 50 nm, oxide-interface
fixed charge density Nox = 4 x 1010 cm-2 , and source and drain diffusion
doping density ND = 1017 cm-3 . In addition, the channel region is implanted
with p-type impurities (impurity concentration N = 2 x 1011 cm-2) to adjust the
threshold voltage. The junction depth of the source and drain diffusion
regions is Xj = 1.0 µm. Plot the variation of the zero-bias threshold voltage VT0
as a function of the channel length (assume that VDS = VSB = 0). Also find VT0
for L = 0.7 µm,VDS = 5 V, and VSB = 0.
(OR)
 Calculation of VT0

 The work function difference between the gate and the channel reflects the built-in
potential of the MOS system, which consists of the p-type substrate, the thin silicon
dioxide layer, and the gate electrode. Depending on the gate material, the work function
difference is

 The depletion region charge density at surface inversion

 Since the doping density of the polysilicon gate is very high; the heavily doped n-type
gate material is expected to be degenerate.
 Thus, we may assume that the Fermi potential of the polysilicon gate is approximately
equal to the conduction band potential = 0.55 V. Now, calculate the work function
difference between the gate and the channel:
 The depletion region charge density at VSB = 0 is found as follows

The oxide-interface charge is

The gate oxide capacitance per unit area is calculated using the dielectric constant of silicon dioxide and the oxide
thickness tox

Now, we can combine all components and calculate the threshold voltage
The threshold voltage without the channel implant was already calculated for the same process parameters in
Example 3.2, and was found to be V. = 0.40 V. The additional p-type channel implant will increase the threshold
voltage by an amount of qN, I Cx. Thus, we find the long-channel zero-bias threshold voltage for the process
described above as

the amount of threshold voltage reduction due to short-channel effects must be calculated using
The following plot shows the variation of the threshold voltage with the channel length.
The threshold voltage decreases by as much as 50% for channel lengths in the submicron
range, while it approaches the value of 0.8 V for larger channel lengths.
Now, consider the variation of the threshold voltage with the applied drain-to-source
voltage.
Equation shows that the depth of the drain junction depletion region increases with
the voltage VDS. For a drain-to-source voltage of VDS = 5 V, the drain depletion depth
is found as:
The threshold voltage of this short-channel MOS transistor is calculated as
 Narrow-Channel Effects
 MOS transistors that have channel widths W on the same
order of magnitude as the maximum depletion region
thickness Xdm are defined as narrow-channel devices.
 The oxide thickness in the channel region is tox, while the
regions around the channel are covered by a thick field
oxide (FOX).
 The most significant narrow-channel effect is that the actual
threshold voltage of such a device is larger than that
predicted by the conventional threshold voltage formula.

 where K is an empirical parameter depending on the shape of the fringe depletion region.
 Assuming that the depletion region edges are modeled by quarter-circular arcs, for example, the parameter K
can be found as
 MOSFET Capacitances
 The current-voltage characteristics investigated here can be applied for investigating
the DC response of MOS circuits under various operating conditions.
 In order to examine the transient (AC) response of MOSFETs and digital circuits
consisting of MOSFETs, on the other hand, we have to determine the nature and the
amount of parasitic capacitances associated with the MOS transistor.
 The on-chip capacitances found in MOS circuits are in general complicated functions
of the layout geometries and the manufacturing processes.
 Most of these capacitances are not lumped, but distributed, and their exact
calculations would usually require complex, three-dimensional nonlinear charge-
voltage models.
 In the following, we will develop simple approximations for the on-chip MOSFET
capacitances that can be used in most hand calculations.
 These capacitance models are sufficiently accurate to represent the crucial
characteristics of MOSFET charge-voltage behavior, and the equations are all based on
fundamental semiconductor device theory.
Top view of the MOSFET
 The mask length (drawn length) of the gate is
indicated by LM
 The actual channel length is indicated by L.
 The extent of both the gate-source and the
gate-drain overlap are LD;
 Thus, the channel length is given by

 The source and drain overlap region lengths

are usually equal to each other because of the
symmetry of the MOSFET structure.
 Typically, LD is on the order of 0.1 µm.
 Both the source and the drain diffusion regions
have a width of W.
 The typical diffusion region length is denoted
by Y
 Lumped Parasitic MOSFET Capacitances

Based on their physical origins, the parasitic device capacitances can be classified into
two major groups:
1. Oxide-related Capacitances.
2. Junction Capacitances.
 Oxide-related Capacitances
The two overlap capacitances that arise are
CGD (overlap) and CGS (overlap).
Assuming that both the source and the drain diffusion regions have
the same width W, the overlap capacitances can be found as

Note: Both of these overlap capacitances do not depend on the bias

conditions, i.e., they are voltage-independent.
The capacitances which result from the interaction between
the gate voltage and the channel charge.
Channel region is connected to the source, the drain, and the
substrate, we can identify three capacitances between the
gate and these regions, i.e., Cgs, Cgd and Cgb respectively.
The gate-to-channel capacitance is distributed and voltage-
dependent.
A simplified view of their bias-dependence can be obtained by
observing the conditions in the channel region during,
1. cut-off,
2. linear, and
3. saturation modes.
 Capacitance in Cut-off Mode
 The surface is not inverted.
 Consequently, there is no conducting
channel that links the surface to the
source and to the drain.
 Therefore, the gate-to-source and the
gate-to-drain capacitances are both equal
to zero: Cgs = Cgd= 0.
 The gate-to-substrate capacitance Cgb can
be approximated by
 Capacitance in linear-mode
 The inverted channel extends across the
MOSFET, between the source and the
drain.
 This conducting inversion layer on the
surface effectively shields the substrate
from the gate electric field; thus, Cgb = 0.
 In this case, the distributed gate-to-
channel capacitance may be viewed as
being shared equally between the source
and the drain, yielding
 Capacitance in Saturation-mode
 The inversion layer on the surface does not
extend to the drain, but it is pinched off.
 The gate-to-drain capacitance component is
therefore equal to zero (Cgd = 0) .
 Since the source is still linked to the
conducting channel, its shielding effect also
forces the gate-to-substrate capacitance to
be zero, Cgb = 0.
 Finally, the distributed gate-to-channel
capacitance as seen between the gate and
the source can be approximated by
Total Oxide Capacitance
Total Capacitance= (Cgb + Cgs + Cgd).
the sum of all three voltage-dependent
(distributed) gate oxide capacitances,
(Cgb + Cgs + Cgd) has a minimum value
of 0.66 Cox WL (in saturation mode)
Maximum value of Cox WL (in cut-off
and linear modes).
For simple hand calculations where all
three capacitances can be considered
to be connected in parallel, a constant
worst-case value of Cox W (L+2LD) can
be used for the sum of MOSFET gate
oxide capacitances
Variation of the distributed (gate-to-channel) oxide
capacitances as functions of gate-to-source voltage VGS
 Junction Capacitance
 The voltage-dependent source-
substrate and drain-substrate
junction capacitances, Csb and Cdb.
 Both of these capacitances are due to
the depletion charge surrounding the
respective source or drain diffusion
regions embedded in the substrate.
 Note that both of these junctions are
reverse-biased under normal
operating conditions of the MOSFET
 The amount of junction capacitance
is a function of the applied terminal
voltages.
 The n+ diffusion region forms a number of
planar pn-junctions with the surrounding p-
type substrate, Indicated here with 1 through 5.
 The dimensions of the rectangular box
representing the diffusion region are given as
W, Y, and Xj
 Three of the five planar junctions shown here
(2, 3, and 4) are actually surrounded by the p+
channel-stop implant.
 The junction labeled (1) is facing the channel,
 The bottom junction (5) is facing the p-type
substrate, which has a doping density of NA.
 Since the p+ channel-stop implant density is
usually about 10NA, the junction capacitances
associated with these sidewalls will be different
from the other junction capacitances
Types and areas of the pn-junctions
 Depletion Capacitance
 The depletion capacitance of a reverse-biased pn-junction, consider first the
depletion region thickness, Xd.
 Assuming that the n-type and p-type doping densities are given by ND and
NA, respectively
 the reverse bias voltage is given by V (negative), the depletion region
thickness can be found as follows

The built-in junction potential is

The depletion-region charge stored in this area can be written in terms
of the depletion region thickness, xd.

Here, A indicates the junction area. The junction capacitance associated

with the depletion region is defined as

1
 This expression can be rewritten in a more general form, to account for the junction grading

The parameter m in is called the grading coefficient. For an abrupt pn-junction profile, i.e., for
m = 1/2, the equations 1 and 2 become identical. The zero-bias junction capacitance per unit
area Cjo is defined as

The terminal voltages of a MOSFET will change during dynamic operation, accurate
estimation of the junction capacitances under transient conditions is quite complicated;
The problem of estimating capacitance values under changing bias conditions can be
simplified, if we calculate a large-signal average (linear) junction capacitance instead, which,
by definition, is independent of the bias potential. This equivalent large-signal capacitance
can be defined as follows:

Here, the reverse bias voltage across the pn-junction is assumed to change from VI to V2.
Hence, the equivalent capacitance Ceq is always calculated for a transition between two
known voltage levels.
Consider a simple abrupt pn-junction, which is reverse-biased with a voltage Vbias. The doping
density of the n-type region is ND 1019 cm-3, and the doping density of the p-type region is
given as NA = 1016 cm-3. The junction area is A = 20 µm x 20 µm. Calculate the Ceq for the
reverse bias voltage changes from V = 0 to V2 = - 5 V.

First, we will calculate the zero-bias junction capacitance per unit area, C , for this structure.
The built-in junction potential is found as