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Exercice 8 VHDL

The document describes the VHDL code for a divider by 5 million using 3 8-bit counters and a divider by 2 using a D flip-flop with asynchronous reset. It provides the full VHDL code for each divider circuit.

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tayari_l
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13 views3 pages

Exercice 8 VHDL

The document describes the VHDL code for a divider by 5 million using 3 8-bit counters and a divider by 2 using a D flip-flop with asynchronous reset. It provides the full VHDL code for each divider circuit.

Uploaded by

tayari_l
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1. Donner la description en langage VHDL (Entity et Architecture) d’un diviseur par 5.

106 à
partir de 3 compteurs 8 bits. Utiliser pour cela 3 variables (COUNT_0, COUNT_1,
COUNT_2) de type integer, représentant chacune la valeur d’un compteur

entity div_5000000 is

port(

clk : in std_logic;

rst : in std_logic;

div_out : out std_logic

);

end div_5000000;

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Architecture:

architecture Behavioral of div_5000000 is

signal count_0 : integer range 0 to 255 := 0;

signal count_1 : integer range 0 to 255 := 0;

signal count_2 : integer range 0 to 255 := 0;

signal div_5M : std_logic := '0';

begin

process(clk, rst)

begin

if rst = '1' then

count_0 <= 0;

count_1 <= 0;

count_2 <= 0;

div_5M <= '0';

elsif rising_edge(clk) then

if count_0 = 249 then

count_0 <= 0;

if count_1 = 249 then

count_1 <= 0;

if count_2 = 9 then
count_2 <= 0;

div_5M <= not div_5M;

else

count_2 <= count_2 + 1;

end if;

else

count_1 <= count_1 + 1;

end if;

else

count_0 <= count_0 + 1;

end if;

end if;

end process;

div_out <= div_5M;

end Behavioral;

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2. Donner la description d’un diviseur par 2 en utilisant la bascule D avec remise à zèro
asynchrone (RST).
entity div_2 is

port(

clk : in std_logic;

rst : in std_logic;

div_out : out std_logic

);

end div_2;
architecture Behavioral of div_2 is

signal div_2 : std_logic := '0';

begin

process(clk, rst)

begin

if rst = '1' then

div_2 <= '0';

elsif rising_edge(clk) then

div_2 <= not div_2;

end if;

end process;

div_out <= div_2;

end Behavioral;

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