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Optimal DCM Clock and External Feedback Inputs

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17 views1 page

Optimal DCM Clock and External Feedback Inputs

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Thiện Khiêm
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© © All Rights Reserved
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Chapter 3: Using Digital Clock Managers (DCMs)

Optimal DCM Clock and External Feedback Inputs


Each DCM has multiple optimal inputs for an incoming clock signal or external feedback
signal.

Spartan-3E FPGA DCM Clock Inputs


Table 3-14 through Table 3-16 list the direct inputs to each DCM on Spartan-3E FPGAs.
Each DCM has up to four direct input pins, used for clock or external feedback
connections. Optionally, these pins are also the direct inputs to the global buffers on the
FPGA. Each table shows all four possible direct inputs, the associated pin number by
package, the associated GCLK, RHCLK, or LHCLK clock input, and the BUFGMUX clock
buffers associated with each DCM. Lastly, each table also includes the LOC location
attribute string from the DCM, the associated BUFGMUX buffers, and the direct input
pins.
The pin number is shown for each potential direct input. Two associated pins can be
combined to form a differential clock input.
Table 3-14, page 85 shows the direct connections to the DCMs associated with the global
clock network. These DCMs are the best choice for the highest-speed clocks in the design
and for clocks with the highest fanout. The top DCMs are associated with I/O Bank 0, and
the bottom DCMs are associated with I/O Bank 2. The XC3S100E has only two “global”
DCMs, located in the upper right and lower right. The outputs from a “global” DCM drive
up to four BUFGMUX clock buffers along the same edge. The two DCMs along an edge
share these four clock buffers. Each of these buffers, in turn, connects to one of the eight
global clock lines.
Table 3-15, page 86 and Table 3-16, page 86 show the direct connections to the left- and
right-edge DCMs available on the XC3S1200E and XC3S1600E FPGAs. The output clocks
from these DCMs are available on the associated half of the FPGA. The left-edge DCMs are
associated with I/O Bank 3, and the right-edge DCMs are associated with I/O Bank 1. The
outputs from a left-edge or right-edge DCM each drive up to four BUFGMUX clock buffers
along the same edge, each of which connects to one of the eight clock lines. These
BUFGMUX buffers provide clocks to half of the chip, whereas the “global” DCMs provide
clocks to the entire FPGA.

84 www.xilinx.com Spartan-3 Generation FPGA User Guide


UG331 (v1.8) June 13, 2011

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