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Using Digital Clock Managers (DCMS)

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34 views1 page

Using Digital Clock Managers (DCMS)

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Thiện Khiêm
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© © All Rights Reserved
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Chapter 3

Using Digital Clock Managers (DCMs)


Summary
Digital Clock Managers (DCMs) provide advanced clocking capabilities to
Spartan®-3 generation FPGA applications (Spartan-3, Spartan-3E, and Extended
Spartan-3A families). Primarily, DCMs eliminate clock skew, thereby improving system
performance. Similarly, a DCM optionally phase shifts the clock output to delay the
incoming clock by a fraction of the clock period. DCMs optionally multiply or divide the
incoming clock frequency to synthesize a new clock frequency. The DCMs integrate
directly with the FPGA’s global low-skew clock distribution network.

Introduction
DCMs integrate advanced clocking capabilities directly into the FPGA’s global clock
distribution network. Consequently, DCMs solve a variety of common clocking issues,
especially in high-performance, high-frequency applications:
• Eliminate Clock Skew, either within the device or to external components, to
improve overall system performance and to eliminate clock distribution delays.
• Phase Shift a clock signal, either by a fixed fraction of a clock period or by
incremental amounts.
• Multiply or Divide an Incoming Clock Frequency or synthesize a completely new
frequency by a mixture of clock multiplication and division.
• Condition a Clock, ensuring a clean output clock with a 50% duty cycle.
• Mirror, Forward, or Rebuffer a Clock Signal, often to deskew and convert the
incoming clock signal to a different I/O standard—for example, forwarding and
converting an incoming LVTTL clock to LVDS.
• Any or all the above functions, simultaneously.
Table 3-1: Digital Clock Manager Features and Capabilities
Feature Description DCM Signals
Digital Clock Managers (DCMs) per Device Two to eight DCMs, depending on All
array size. See Figure 3-1, page 68.
Clock Input Sources • Global buffer input pad CLKIN
• Global buffer output
• General-purpose I/O (no deskew)
• Internal logic (no deskew)
Frequency Synthesizer Output Multiply CLKIN by the fraction (M/D) • CLKFX
where M = {2..32}, D = {1..32} • CLKFX180

Spartan-3 Generation FPGA User Guide www.xilinx.com 65


UG331 (v1.8) June 13, 2011

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