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Spartan-3 FPGA Clock Inputs: Table 2-3

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Spartan-3 FPGA Clock Inputs: Table 2-3

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Clock Inputs

Table 2-3: Global Clock Input Pads for Spartan-3E FPGAs (Cont’d)
Pad Bank VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484
RHCLK4 1 P65 H13 P91 P132 H15 J17 K13 L20
RHCLK5 1 P66 H12 P92 P133 H14 J16 K14 L21
RHCLK6 1 P67 G14 P93 P134 H12 J15 K20 L18
RHCLK7 1 P68 G13 P94 P135 H11 J14 J20 L19

Spartan-3 FPGA Clock Inputs


Spartan-3 devices have eight Global Clock input pads called GCLK0 through GCLK7.
GCLK0 through GCLK3 are placed at the center of the die’s bottom edge. GCLK4 through
GCLK7 are placed at the center of the die’s top edge. Any of the eight Global Clock inputs
can connect to any resource on the die. There are no restrictions by quadrant, and no
differentiation of primary and secondary clocks, simplifying I/O and logic placement. In
the Spartan-3 family, none of the clock inputs share functionality with configuration pins,
and all are on I/O pins.
The pin locations for the global clock input pads are shown in Table 2-4.

Table 2-4: Global Clock Input Pads for Spartan-3 FPGAs


Pad Bank VQ100 CP132 TQ144 PQ208 FT256 FG320 FG456 FG676 FG900 FG1156(2)
GCLK0 4 P38 M7 P55 P79 T9 P10 AB12 AF14 AK16 AP18
GCLK1 4 P39 P8 P56 P80 R9 N10 AA12 AE14 AJ16 AN18
GCLK2 5 P36 P6 P52 P76 N8 P9 Y11 AD13 AH15 AM17
GCLK3 5 P37 P7 P53 P77 P8 N9 AA11 AE13 AJ15 AN17
GCLK4 1 P87 A9 P124 P180 D9 F10 C12 C14 C16 C18
GCLK5 1 P88 A8 P125 P181 C9 E10 B12 B14 B16 B18
GCLK6 0 P89 C8 P128 P183 A8 F9 A11 A13 A15 A17
GCLK7 0 P90 A7 P127 P184 B8 E9 B11 B13 B15 B17

Notes:
1. The CP(G)132 package is discontinued. See http://www.xilinx.com/support/documentation/customer_notices/xcn08011.pdf for
details.
2. The FG(G)1156 package is discontinued. See http://www.xilinx.com/support/documentation/customer_notices/xcn07022.pdf
for details.

Clock Inputs and DCMs


Clock inputs optionally connect directly to DCMs using dedicated connections. For more
information on the clock inputs that best feed a specific DCM within a given device in each
family, see Chapter 3, “Using Digital Clock Managers (DCMs).”

Differential Clocks Using Two Inputs


A differential clock input requires two global clock inputs. The P and N inputs follow the
same configuration as for standard inputs on those pins. The clock inputs that get paired
together are consecutive pins in clock number, an even clock number and the next higher

Spartan-3 Generation FPGA User Guide www.xilinx.com 51


UG331 (v1.8) June 13, 2011

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