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Topic 6 - Clocking & Met A Stability

This document is a set of slides about clocking and metastability in digital systems from a lecture on the topic. It discusses how asynchronous inputs must be synchronized before being applied to synchronous systems using synchronizers. It describes challenges like metastability and clock skew that can occur. It presents solutions like using multiple flip-flops in synchronizers and delay locked loops to distribute clock signals with precise delays. It also discusses phase locked loops and their use in applications like clock recovery and frequency synthesis.

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anish1988
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124 views9 pages

Topic 6 - Clocking & Met A Stability

This document is a set of slides about clocking and metastability in digital systems from a lecture on the topic. It discusses how asynchronous inputs must be synchronized before being applied to synchronous systems using synchronizers. It describes challenges like metastability and clock skew that can occur. It presents solutions like using multiple flip-flops in synchronizers and delay locked loops to distribute clock signals with precise delays. It also discusses phase locked loops and their use in applications like clock recovery and frequency synthesis.

Uploaded by

anish1988
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Asynchronous inputs

Not all inputs are synchronized with the clock Examples:


Keystrokes Sensor inputs Data received from a network (transmitter has its own clock)

Topic 6 Clocking & Metastability


Peter Cheung Department of Electrical & Electronic Engineering Imperial College London

Inputs must be synchronized with the system clock before being applied to a synchronous system.

URL: www.ee.imperial.ac.uk/pcheung/ E-mail: [email protected]


PYKC 31-Jan-08 E3.05 Digital System Design Topic 6 Slide 1 PYKC 31-Jan-08 E3.05 Digital System Design Topic 6 Slide 2

A simple synchronizer

Only one synchronizer per input

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Even worse

The way to do it

Combinational delays to the two synchronizers are likely to be different.

One synchronizer per input Carefully locate the synchronization points in a system. But still a problem -- the synchronizer output may become metastable when setup and hold time are not met.

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Recommended synchronizer design

Metastability decision window

Hope that FF1 settles down before META is sampled.


In this case, SYNCIN is valid for almost a full clock period. Can calculate the probability of synchronizer failure (FF1 still metastable when META sampled)

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Metastability resolution time

Flip-flop metastable behavior


Probability of flip-flop output being in the metastable state is an exponentially decreasing function of tr (time since clock edge, i.e. resolution time). Stated another way,

MTBF ( t r ) =

exp ( t r / ) To f a

where and T0 are parameters for a particular flip-flop, f is the clock frequency, and a is the number of asynchronous transitions / sec
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MTBF versus Resolution Time (tr)

Typical flip-flop metastability parameters

MTBF ( t r ) =
Changing T0

exp ( t r / ) To f a
MTBF = 1000 yrs. F = 25 MHz a = 100 KHz tr = ?

Grad = 1/

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Is 1000 years enough?


If MTBF = 1000 years and you ship 52,000 copies of the product, then some system experiences a mysterious failure every week. Real-world MTBFs must be much higher. How to get better MTBFs?
Use faster flip-flops
But clock speeds keep getting faster, thwarting this approach.

Multiple-cycle synchronizer

Wait for multiple clock ticks to get a longer metastabilty resolution time
Waiting longer usually doesnt hurt performance unless there is a critical round-trip handshake.

Clock-skew problem

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Deskewed multiple-cycle synchronizer

Clock Skew
Clock signal may not reach all flip-flops simultaneously. Output changes of flip-flops receiving early clock may reach D inputs of flipflops with late clock too soon.

Necessary in really high-speed systems DSYNCIN is valid for almost an entire clock period.

Reasons for slowness: (a) wiring delays (b) capacitance (c) incorrect design
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Clock-skew calculation

Example of bad clock distribution

tffpd(min) + tcomb(min) thold tskew(max) > 0 First two terms are minimum time after clock edge that a D input changes Hold time is earliest time that the input may change Clock skew subtracts from the available hold-time margin Compensating for clock skew:
Longer flip-flop propagation delay Explicit combinational delays Shorter (even negative) flip-flop hold times

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Multiple Clock Domains


Many digital systems have more than one clock domains:-

Example: Classical clock recovery


Clocking information embedded in data stream Use PLL to recover the clock State of system is stored in analog loop filter

Needs to synchronise the two clock domains using two basic building blocks:
Phase-locked loop (PLL) Delay-locked loop (DLL)

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Oversampled Clock/Data Recovery


Oversample the data and perform phase alignment digitally De-couples clock generation from tracking of data Data must guarantee transitions to ensure tracking

Phase Alignment in Source Synchronous Systems Timing information carried by reference clock Use DLL to ensure proper clock phase for sampling

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What is a Delay locked loop?

What is Phase locked loop?

First order loop:


easily stabilized frequency synthesis is difficult reference clock jitter passes to output no phase error accumulation
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2nd/3rd order loop:


stability could be an issue frequency multiplication is easy reference clock jitter reduced by filtering phase error accumulation
E3.05 Digital System Design Topic 6 Slide 24

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Timing Loop Performance Parameters


Phase Jitter:

Clock Management with DLL


Can eliminate on-chip clock delay
can also eliminate on-board clock delay

4 fixed-phase outputs (0, 90 , 180 , 270 ) Selectable phase shift ( n / 256 of the period)
through configuration or through increment/decrement 1/256 of clock period or 50 picosecond granularity

Phase Offset
Error between output phase and reference phase

Bandwidth
rate at which output phase tracks reference

Frequency synthesis (division and multiplication) Outputs are always phase-coherent

Acquisition time (to lock) Frequency range (lock range)


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Solves the speed problem of large chips


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DLL in Xilinx Virtex data/clock alignment

Xilinx DLL with various phase outputs

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Using DLL to de-skew onboard clock signals

Altera Cyclone II PLL (1)


Phase-locked loop (PLL) is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback clock signal of a controlled oscillator. Main components:
Phase frequency detector (PFD) Charge pump & loop filter Voltage controlled oscillator (VCO) Counters (N pre-scale, M feedback, C post-scale)

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Altera Cyclone II PLL (2)


PLL aligns the rising edge of reference input clock to feedback clock using the PFD. PFD detects difference in phase and frequency between reference clock and feedback clock and generates an up or down control signal based on whether the feedback frequency is lagging or leading the reference frequency. If the charge pump receives an up signal, current is driven into the loop filter, otherwise, current is drawn from the loop filter. Loop filter converts these up down signals to a control voltage to control the oscillation frequency of the voltage controlled oscillator (VCO). Feedback loop counter (M) is used to increase VCO frequency above input reference frequency. Pre-scale counter (N) is used to produce the reference frequency from FIN. The post-scale counters (C) allows a number of harmonically related frequencies be generated from one common clock.

Altera Cyclone II PLL (3)


The output frequency is given by:

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References for this topic


Chapter 8, pp757-773, Digital Design Principles & Practices, John Wakerly. Metastability in Altera Devices, Altera App Note 42. Using the ClockLock &ClockBoost PLL Features in APEX Devices, Altera App Note 115. Using the Virtex Delay-Locked Loop, XAPP-132. Advantages of APEX PLLs Over Virtex DLLs, Altera TB60.

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