COMP2340

+ Lecture 5

Sequential Logic
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Sequential Circuits

• Combinational logic circuits are perfect for situations

when we require the immediate application of a
Boolean function to a set of inputs.
• There are other times, however, when we need a
circuit to change its value with consideration to its
current state as well as its inputs.
• These circuits have to “remember” their current
state.
• Sequential logic circuits provide this functionality for
us.
+
Sequential Circuits

◼ Our main objective for studying sequential logic

circuits is for understanding how registers work.

◼ Registers provide storage (memory) for values

that are being used by the processor.

◼ Wewill see how a register is constructed from

simple sequential logic circuits.
+
Topics

• As usual we will build up from basic circuits by

looking at the following:
• Bistable devices
• SR Latch
• D Latch
• Clocked D Latch
• Flip-Flop
• Register
4
+
Sequential Circuits
◼ As the name implies, a sequential logic circuit has a state at
a point in time.
◼ Sequential logic circuits require a means by which events
can be sequenced.
◼ State changes are controlled by pulses.
◼ In most sequential circuits these pulses are generated by a
clock
◼ A “clock” is a special circuit that sends electrical pulses
through a circuit.
◼ Please note however that the pulses which drive sequential
circuits can be generated by means other than a clock.

1
0
Unit of Time
+
Sequential Circuits
◼ State changes occur in sequential circuits in strict order of the
pulses that are sent to the circuit
◼ Circuits can change state:
◼ on the rising edge (moving from low to high)
◼ falling edge (moving from high to low)
◼ while the pulse is at its highest voltage
◼ while the pulse is at its lowest voltage
+
Sequential Circuits

◼ Circuits that change state on the rising edge, or falling edge of the
pulse are called edge-triggered.
◼ Level-triggered circuits change state while the pulse is at its highest
or lowest level.
+
Feedback

◼ To retain their state values, sequential

circuits rely on feedback.
◼ Feedback in digital circuits occurs
when an output is looped back to the
input.
◼ A simple example of this concept is
shown below.
◼ If the value 0 is input to the circuit the
output (Q) becomes 0. This circuit is referred
◼ Q will remain at 0 even after the input
is no longer applied, as long as power to as “bistable”
is supplied to the circuit.
◼ The same characteristic is displayed
when the input to the circuit is 1.
+
Latches
◼ The simple bistable device demonstrates the use of
feedback elegantly. However, this circuit is hard to control
and is not used in this basic form.
◼ A more useful circuit (one that is more easily controlled) is
the latch.
• A latch has two inputs (labelled S and R (for
Set and Reset)
• The circuit has two outputs labelled Q and
~Q. (We will usually only consider Q)
• This basic circuit can be constructed using
two NOR gates (as shown) but may also be
implemented using other gates
• The latch is used to store a single bit (either
1 or 0)
+
Latches

◼ Thebehavior of an SR latch is described by a

characteristic table.
◼ Q(t) means the value of the output at time t, Just before inputs are
placed on the wires S and R.
◼ Q(t+1) is the value of Q after inputs are placed on the wires S and
R.
+
Latches

◼ The SR latch actually has three

inputs: S, R, and its current output,
Q.
◼ Thus, a truth table for this circuit,
as shown at the right considers
each combination of S an R under
two assumptions each time.
◼ Q(t) = 0; output was 0 before
◼ Q(t) = 1; output was 1 before

◼ Notice the two undefined values.

When both S and R are 1, the SR
latch is unstable.
+
Latches
◼ The outputs are not really undefined when S=1 and R=1
◼ What really happens is that the outputs will both have the same
value (either both 1, or both 0)
◼ This makes the operation of the circuit subsequently unreliable.
◼ Consider what happens if the next set of inputs to the circuit is S=0;
R=0
◼ This set of inputs should leave the outputs unchanged
◼ However, what is called a race condition will ensue resulting in Q
being either 0, or 1 (can never be sure which it will be)
◼ This happens because both S and R will begin to change from 1 to 0 at
the same time but one will get there first while the other is still 0 (a race
occurs)
◼ If R gets there first the latch is reset
◼ If S gets there first the latch is set
◼ Race conditions occur all time in digital logic circuits but do not
always result in a problem such as this.
+
Latches

◼ Theclocked SR Latch is
an improvement on the
basic SR Latch.

◼A pulse is placed on the

line labeled Clock to
cause the circuit to store
its inputs
◼ This circuit “reads” its
inputs whenever the pulse Again, care has to be taken to ensure
is 1
that S and R are not both 1. Please
◼ It is level triggered
note that the use of the term clock is
conventional only as the pulse can be
generated by other means.
+
Latches

 The Clocked D-Latch

solves the problem of the
S and R inputs being both
0 at the same time
 The NOT gate ensures
that S is always the
complement of the R
input

 This circuit will store the No change in

value that is at its input state when the
when the pulse is high clock is low.
Stores input
when clock is
high.
+
Flip-Flops

 The Clocked D-Latch is level triggered

 It will start to store its input when the clock signal (pulse) is high and
will continue to do so as long as the pulse is high

 So, if the inputs change during the pulse the data that is stored in
the latch will also change.

 This is not desirable in all cases. Instead, it is often required that

data is stored at a precise time.
 So that subsequent changes in the values of the wires of the circuit
do not affect the value that is stored.

 A flip-flop is a circuit that overcomes this problem by storing a

value only when the pulse changes (0 to 1, or 1 to 0)
 Flip-flops are edge triggered devices
+
Flip-Flops

 One way of overcoming the problem is to use a pulse

generator.

 A pulse generator will use the clock signal to generator a

very short pulse on the transition of the main pulse from 0
to 1, or from 1 to 0.

This is an
example of a
pulse
generator
+
Flip-Flops
◼ Another approach to the problem uses two latches to
create a master-slave flip-flop as shown below.

◼ The second latch is called a slave because it follows the

first latch (the master).
+
Flip-Flops

◼ When the pulse is high the data at the input of the circuit is
stored in the first latch but does not affect the second latch.

1 0

Flip!!
+
Flip-Flops

◼ As the pulse goes to 0 the second latch reads its inputs. The
first latch is now turned off. No changes at the inputs of the
circuit will be recorded.

1
0

Flop!!
+
Flip-Flops

◼ Thereare several features of the Master-Slave flip-flop that

make it interesting for a discussion of how data is stored in
a computer system.

◼ In
fact, the Master-Slave flip-flop is ideal for building
registers.

◼ Wewill use our description of the Master-Slave flip-flop to

describe how registers work.
+
Registers
• A single flip-flop stores a single bit of
data.
• Just as we did with the Adder, we
can connect n flip-flops together to
store n-bits.
• The device thus created is called an
n-bit register.
• Typically, the block diagram at
bottom right will be used to depict a
register in circuits instead of showing
the details of the flip-flops.
+
Registers

• Registers are used to store values in a digital logic

circuit.
• When a register is used in a digital logic circuit the
input that controls the loading of values into the
register is typically labeled with the word Load.
• Another control that is used on a register is the
Output Enable control (OE for short) which is used
to cause the register to place its stored value at its
output.
• These two signals are used to control the
operations of a register when it is used in a circuit.
+
Registers
• Register will store the
inputs if the Load signal
is asserted (set to 1)
Reset
• The register will present
its stored value at its
output only if OE is
asserted (set to 1) Load OE

• Some registers will also

carry a Reset control
that can be used to set
the contents of the
register to 0 (all bits 0)
+
Timing
• The operations of a processor are carefully sequenced by a clock
which generates pulses at a predetermined rate (frequency). A cycle of
the clock is counted from one point of the signal to the next
corresponding point on the signal
• Typically, we will start counting a cycle when the clock starts
asserting low.

t =0 (one cycle) t =1 (one cycle) t =2 (one cycle)

+
Timing
A register holds it value during the clock cycle
• If a value is to be loaded it only loaded at the end of the
cycle
• Thus, values that are input to a register only settle in the
register at the end of the current cycle and become
available for use at the start of the next cycle of the
clock.
A register will load its inputs at this point of the
cycle. Just before the start of the next cycle

t =0 (one cycle) t =1 (one cycle) t =2 (one cycle)

 Other Sequential Logic Circuits

• The JK flip-flop (named after

its inventor Jack Kilby) has
three inputs (J input, K input,
and Clock)
• The JK flip-flop responds to
the J input in the same way an
SR latch responds to its S
input (set output to 1)
• A 1 on the K input, 0 on the J
input sets the output to 0
• A 1 on both inputs “toggles”
the output (becomes 1 if it was
0, or becomes 0 if it was 1)
 Other Sequential Logic Circuits
• The J-K flip-flop is very useful for implementing circuits which generate a next
state on pulses (state machines).
• A binary counter is a circuit that counts
•On each pulse the circuit adds 1 to its previous output
•A 4-bit binary counter will generate outputs as follows:
Time Output
t=0 0000
t=1 0001
t=2 0010
t=3 0011
t=4 0100
t=5 0101
t=6 0110
…
t = 15 1111
t = 16 0000
 Other Sequential Logic Circuits

• This is the circuit for a 4-bit counter using 4 JK flip-flops

Next….

• We now have:
• The Arithmetic and Logic Unit to perform computations
•Registers with which store values
•A clock that sequences the operations of a sequential
circuit
• These are three of the four components of a processor
Processor = Control Unit + ALU + Registers + Clock
• We will discuss how the registers and the ALU are used to
form a data path (the part of the processor where data is
manipulated).
+ Summary
Sequential Logic
Lecture 5

◼ Bistable devices
◼ SR Latch
◼ D Latch
◼ Clocked D Latch
◼ Flip-Flop
◼ Register

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.