COMP2340

+ Lecture 7

Microprogramming
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Registers for Memory Operations

▪ The data path we have discussed thus far has several

deficiencies.
▪ For one we assumed that there was some data in
each register so that our micro-routine could
perform an addition.
▪ Where does this data come from and how does it
get placed into the register?
▪ The answer to this question is that all values that are
used in operations on the data path of a processor, are
transferred to and from memory (RAM).
Memory

▪ To a processor memory is a collection of bytes (sort of like an

array).
▪ Each byte stores a number of bits .
▪ Each byte on memory has a unique address (like the index of an
item in an array).
▪ The processor gets a value from memory by telling memory the
address at which the requested byte is located.
▪ Memory responds by returning the value at the specified
location.
▪ The processor does the converse to store a value to a location in
memory.
Registers for Memory Operations

▪ The registers we have discussed thus far are a sub-set of the

registers that are to be found in a typically processor.
▪ Every processor has a set of registers that are responsible for
transferring values between the processor and RAM.
▪ These are special purpose registers that are given special names:
1. The Memory Address Register (MAR) - Stores an address
in memory from which a value is to be retrieved, or to which a
value is to be stored.
2. The Memory Data Register (MDR) - Stores a value that has
been retrieved from memory, or a value that is to be stored to
memory.
Registers for Memory Operations

This is a
typical
CPU RAM diagram of
a computer
The processor system.
communicates
with RAM along
the System Bus

Values are
retrieved and Other
Mouse Display
stored by being Keyboard … Peripheral
transferred along
the System Bus
Registers for Memory Operations

CPU RAM

This bus is
actually three
Data bus carries
buses:
the values (data)
that are
stored/retrieved
Address bus carries a to/from memory.
value that is the
location in memory
where the data is to be Control bus carries signals to memory to
stored/retrieved from. indicate the type of memory operation that
is being requested. Also carries signals
from memory to the processor.
Registers for Memory Operations

▪ To retrieve a value from memory (Memory Read)

1. Processor places memory address where the value is to be
found on the Address Bus.
2. Processor sends the signal that indicates a Read operation
down the Control Bus.
3. Memory responds by sending the requested value along the
Data Bus to the processor.
Registers for Memory Operations

▪ To store a value to RAM

1. Processor places the value that is to be stored to memory on
the Data Bus.
2. Processor places address in memory where the value is to
stored on its Address Bus.
3. Processor sends the signal that indicates a Write operation
down the Control Bus.
4. Memory responds by storing the value that is on the Data Bus
into the specified memory location.
Registers for Memory Operations
In Out
8

▪ The MDR is connected to the LDMAR T

data path and also to the Data OE2 MDR
Bus. 8
In Out
8
8
O
▪ The MAR is connected to the LDMDR
processor’s data path and also to OEMDR
the Address Bus. R
▪ The Control Bus is actually D2
.
connected to the processor’s
A
Control Unit (not shown here), Read Write 8
D1 88
. M
D0 Out
▪ This bus will have several wires. To
We are only interested in two of
Control
these:
Unit F1
A
▪ Read = 1 to read from B

memory 8-bit ALU F0

Output
▪ Write = 1 to write to
memory Carry In
Accessing Memory

Imagine we have the following task to execute:

▪ Add two numbers stored in consecutive memory locations (starting
at location 100) and store the result in a third location which is right
after the second. One way of doing this is to :
1. Retrieve a value from memory location 100 and store it in D1.
2. Retrieve a value from memory location 101 and store it in D2.
3. Add the value in D2 to the value in D1 (i.e., save result in D1).
4. Store the result to memory location 102.
Accessing Memory

The task can be accomplished as follows:

{First, place the value 100 into the MAR}
1. Read from memory location 100 into D1
a. Read from memory
b. Move value in MDR into register D1
2. Read from memory location 101 into D2
a. Read from memory
b. Move value in MDR into register D2
3. Add value in D1 to value in D2 (We can put the answer in
D1)
4. Move the value in D1 to the MDR
5. Write to memory location 102
Accessing Memory

Group A – Output Enable Group B – Load Registers

D1 D2 MAR MDR PC IR D0 D1 D2 MAR MDR PC IR R W F1 F0 Cin
E R
A I
D T
E

These bits are These bits control

activated to the ALU
read/write memory

Control word now has 17 bits

▪ There is no Output Enable bit for D0 (not needed since D0 is always
connected to ALU’s A input)
▪ We have also added controls for two new registers (PC & IR) which
will be added to our data path soon.
Accessing Memory

Group A – Output Enable Group B – Load Registers

D1 D2 MAR MDR PC IR D0 D1 D2 MAR MDR PC IR R W F1 F0 Cin
E R
A I
D T
E

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0

F1 F0 OUTPUT
0 0 A
0 1 B
1 0 B+1
Step 1 - Send Read Step 2 - Move 1 1 A + B (SUM)
signal to memory value in MDR to D1

Steps 1 and 2 could be implemented as above,

but most likely it will not work … Why?
Accessing Memory

▪ Memory is typically much slower than the processor.

▪ There will be a delay between the time a signal is sent to memory
and the time a response is received.
▪ A memory cycle (the time it takes memory to respond) can be
several clock cycles.
▪ For our examples, we will assume that memory takes one clock
cycle to respond.
▪ Processor could do nothing while waiting (1 clock cycle)
▪ Can we do something else while waiting for the value from memory
to reach the MDR?
▪ Yes! We can increment the address that is stored in the
MAR.
Accessing Memory

Group A – Output Enable Group B – Load Registers

D1 D2 MAR MDR PC IR D0 D1 D2 MAR MDR PC IR R W F1 F0 Cin
E R
A I
D T
E

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0

Add 1 to value in MAR and ALU set to B + 1 operation

store result back into the
MAR

A more workable approach!

 Accessing Memory
All Tasks Together

Group A – Output Enable Group B – Load Registers

D1 D2 MAR MDR PC IR D0 D1 D2 MAR MDR PC IR R W F1 F0 Cin

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
2 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0
3 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0
4 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0
5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

1. Get value at location 100 and store in register D1 (3 clock cycles)

2. Get value at location 101 and store in register D2 (3 clock cycles) Entire operation takes
3. Transfer value from D1 into D0 (getting ready to add) (1 clock cycle) 9 clock cycles!
4. Add value in D2 to value on D0 and store result in D1. Since we are
going to write it to memory, we also store it in the MDR (1 clock cycle)
5. Store value in MDR to memory location 102 (1 clock cycle)
Instructions

▪ The preceding sequence of microinstructions accomplish a

specific task:

1. Get a value from memory

2. Store the value in a register
3. Get a second value from memory
4. Store the value in a second register
5. Add the two values together
6. Store the result to a location in memory

▪ A task such as this is the processor’s response to a command,

an instruction, such as Z = X + Y
▪ More specifically the command might be in the form
ADD X,Y,Z
Instructions

▪ An instruction is a set of bits in a predefined format. The bits

in an instruction tell the processor what to do.
▪ A program that is run on a computer is a of set instructions
that are kept in memory.
▪ Each instruction has a location in the program.
▪ The micro-architecture of a processor is organized to fetch
and execute each instruction in the program.
▪ We now consider two special registers that are used to fetch
instructions from memory.
The Program Counter

▪ The Program Counter (PC) is a special register that is used to

“point” to a location in memory from which the next
instruction in a program is to be fetched.
▪ The value that is stored in the Program Counter will be
the address in memory from which the next instruction
in a program is to be fetched.
▪ As an instruction is fetched from memory the Program
Counter is automatically incremented to point to the location
that follows the one just fetched.
▪ Depending on the logic of the program the next
instruction might not be the one immediately following.
The Instruction Register

▪ When an instruction is fetched it is stored in a special register

– the Instruction Register.
▪ The Instruction Register is wired so that some of its bits are
automatically output to the Control Unit of the processor.
▪ The Control Unit gets the part of the instruction which tells
the processor to carry out an operation and fires off the
microinstructions that are needed to achieve the operation
▪ For example, to add the contents of two registers.
A Simple Processor
(Instruction Register and Program Counter Added)
In MAR Out
8

8 8
MDR
To RAM
Control In PC Out
8

Unit 8 8
IR

Bits in instruction tell

8
D2
.
8

8
Control Unit what to do 8
8
D1 8
.
D0 Out

Control Unit responds

by sending A B F1
microinstructions to 8-bit ALU F0
Output
the data path
Carry In
Instruction Fetch

▪ The operation of fetching an instruction from memory is

called an Instruction Fetch.
▪ How this is done will depend on the processor’s micro-
architecture.
▪ For the simple processor that we are describing here, an
Instruction Fetch is accomplished as follows:
▪ Transfer the value in the Program Counter to the MAR.
▪ Read from memory and increment the Program Counter
while waiting for memory.
▪ Transfer the value in the MDR to the Instruction Register.
Instruction Fetch

▪ Microinstructions for the Instruction Fetch. This operation takes 3 clock

cycles.
Output Enable Signals Load Register Signals Mem. ALU
D1 D2 MAR MDR PC IR D0 D1 D2 MAR MDR PC IR R W F1 F0 Cin

0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0
0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0
0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0

1. The value in the PC is sent through the ALU and stored in the MAR. The MAR now has the
address of the next instruction that is to be fetched from memory.

2. A Read signal is sent to memory. Memory will respond (after 1 clock cycle) by placing a value
on the data bus, to be stored in the MDR. At the same time the value in the PC is sent
through the ALU, incremented by 1 and stored back into the PC. The next instruction that
the processor fetches will be the one following the one that is now being fetched.

3. The instruction from memory has arrived in the MDR. The bits in the instruction are
transferred from the MDR to the Instruction Register (IR).
Instruction Fetch

▪ Once the instruction has been fetched the processor must determine
what “command” the instruction gives.
▪ This is referred to as decoding the instruction.
▪ The bits in the instruction are a code that the processor decodes.
▪ Instruction Decode is carried out by the processor’s Control Unit.
▪ This can be quite complex but will usually involve the controller selecting
a specific micro-routine that carries out the requested operations.
▪ For example, if the instruction is ADD X, Y, Z then the micro-routine that
was discussed earlier will be selected.
Instruction Fetch

▪ After the instruction has been fetched and decoded, the

instruction is executed.
▪ This step is referred to as the Instruction Execute step and
the step where the control unit sends one microinstruction in
the micro-routine to accomplish the requested operation.
▪ Then the processor fetches the next instruction in the
program thus repeating the Fetch -> Decode -> Execute cycle.
Microprogrammed Processors

▪ The steps we have discussed are typical of the organization of

microprogrammed processors.
▪ The Control Unit of a microprogrammed processor has a small memory
(called a Control Store).
▪ Each location in the Control Store stores a control word (the groups
of bits that make up a microinstruction).
▪ In the case of the example, we have discussed each location would
store 18 bits.
▪ Each location has an address (the first location is addressed as
location 0)
▪ Each micro-routine is stored in a set of consecutive locations
starting with the location of the first microinstruction in the micro-
routine
Microprogrammed Processors

▪ A sequencer (part of the controller) determines which microinstruction is

to be run on each tick of the clock.
▪ When the clock ticks the sequencer determines which
microinstruction is to be sent to the data path, selects the
microinstruction from the control store and sends the bits in the
microinstruction along wires that connect the control unit to the
data path.
 Microprogrammed Processors
▪ On each tick of the clock
Bits from the 3. The bits of the control word (a
Instruction Register
microinstruction) are sent out of the
Control Unit to the data path.

Control Store - stores

…. microinstructions. Each
D1

microinstruction is stored in a D2

control word. MAR

Sequencer
….

MDR

D2

….
1. Sequencer sends an F1

address (binary value) to F0

the Control Store.
Cin

2. The address from the sequencer selects

one control word.
 Microprogrammed Processors
▪ Consider that the Control Store of our processor is organized as shown. The
sequence of control store addresses for execution of the ADD X,Y,Z
instruction might be as shown in the table below.
Clock Location of
Microinstructions that Cycle microinstruction
fetch an instruction.
The first is at location 1 0000 0000

0. There were 3. 2 0000 0001

3 0000 0010

…
4 0010 0000
5 0010 0001
Microinstructions that
6 0010 0010
carry out the instruction
7 0010 0011
ADD X,Y,Z 8 0010 0100

These are at the 9 0010 0101

locations starting at 32. 10 0010 0110
From our example there 11 0010 0111
were 9 of these. Fetch another 12 0010 1000
instruction 13 0000 0000
14
Microprogrammed Processors

▪ In general, the micro-architecture of a processor is said to interpret the

instructions of a program.
▪ A microprogrammed processor requires several clock cycles to interpret
each instruction.
▪ The range of instructions the processor can interpret is determined by
the microinstructions in its control store.
▪ The microinstruction in the processor’s control can be changed to
interpret new, or different instructions.
▪ For this reason, microprogrammed processors are very flexible (more on
this in subsequent discussions of CISC).
Hardwired Controllers

▪ The Control Unit of a processor can

be distinguished from the data paths
of the processor.
▪ In fact, we can view the processor as
consisting of The Data Path +
Controller. Controller

▪ Each may be implemented

separately as long as the controller
provides the signals that are
necessary to influence the state of
the data path.
Hardwired Controllers

▪ The Control Unit of a processor can

be built entirely from hardware:
▪ Micro-routines are
permanently wired into the
digital logic circuits that make
up the unit. Controller

▪ This type of controller is

referred to as a hardwired
controller.
Clock signal
▪ Can issue microinstructions
faster.
▪ Not flexible since once logic is
wired in it cannot be changed.
Single Cycle Architectures

▪ The time it takes for a microprogrammed processor to fetch

and execute an instruction will vary depending on the
number of microinstructions that are required to interpret
each instruction.
▪ Single cycle architectures interpret each instruction in one
cycle.
▪ Single cycle architectures typically use hardwired controllers.
▪ Single cycle processors are simpler to construct but cycle
has to be as long as the time taken to process the
longest instruction.
Real Microarchitectures

▪ The micro-architecture of a real processor is much more complex than

the simple processor we have discussed.
▪ A real processor has many more registers (at least 16 in most
cases).
▪ Most modern processors use 32-bit or 64-bit registers.
▪ A modern processor has several computational units including
several ALU’s and a unit for computation involving real numbers
(Floating Point Unit, or FPU), a special unit that interfaces with
memory (Memory Management Unit – MMU), cache memory, a
graphics processing unit (GPU), and others.
▪ However, the general principles we have discussed will apply in most
cases.
Real Microarchitectures

▪ A processor is described by:

▪ How fast the processor can be clocked. A 1 GHz processor can be
used in a system with a clock that generates pulses (ticks) at a rate
of 1 GHz (1 billion ticks per second)
▪ The size of its registers. For example, a 32-bit processor is one that
has 32-bit registers
▪ Type of controller it uses. Hardwired controller vs.
microprogrammed controller.
▪ The number of bits it uses to address memory. For example, a 16-
bit processor can generate 32-bit addresses by placing the address
on the address bus in two steps.
Performance

▪ The organization of the units in a processor can impact on its

performance.
▪ For example, the manner in which the different buses are arranged
can increase the number of clock cycles that are required for the
interpretation of instructions.
▪ Modern processors have more buses than the simple 3 bus system
we have discussed.
▪ As the speed at which a processor operates is increased, the amount of
heat it generates also increases.
▪ The number of pins on a processor.
Conclusion

▪ Special registers are used to implement the fetch -> decode -

> execute cycle for a group of instructions.
▪ Instructions in memory read from memory may normally
need to be decomposed more.
▪ Decomposition performed using a controller (either
hardwired or microprogrammed).
▪ Various metrics used to judge the performance capability of
processors.
▪ Next - Instruction Set Architectures
+ Summary
Microprogramming
Lecture 7

◼ Registers for Memory ◼ Microprogrammed Processors

Operations ◼ Hardwired Controllers
◼ Accessing Memory ◼ Single Cycle Architectures
◼ Instructions ◼ Real Microarchitectures
◼ The Program Counter
◼ The Instruction Register
◼ Instruction Fetch
◼ Instruction Decode
◼ Instruction Execute

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.