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Behavioral Modeling

The document describes several digital logic components including a 4-bit comparator, JK flip-flop with asynchronous clock, 4-bit ring counter, clock generator, and D and T flip-flops with and without synchronous and asynchronous resets.

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Mahak Bansal
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17 views11 pages

Behavioral Modeling

The document describes several digital logic components including a 4-bit comparator, JK flip-flop with asynchronous clock, 4-bit ring counter, clock generator, and D and T flip-flops with and without synchronous and asynchronous resets.

Uploaded by

Mahak Bansal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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4 bit comparator

module comperator(a,b,equal,greater,smaller);
output equal;
reg equal;
output greater;
reg greater;
output smaller;
reg smaller;
input wire [3:0]a;
input wire[3:0]b;
always@(a or b)begin
if(a<b) begin
equal=0;
smaller=1;
greater=0;
end
else if(a==b)begin
equal=1;
smaller=0;
greater=0;
end
else begin
equal=0;
smaller=0;
greater=1;
end
end
endmodule
jk flipflop negative edge triggered and asynchronous clock
module jkff(clk,j,k,reset,q);
input clk,reset,j,k;
output reg q;

always @ (negedge clk or negedge reset)begin


if(~reset)
q <= 0;
else begin
case({j,k})
2'b00:
q <= q;
2'b01:
q <= 0;
2'b10:
q <= 1;
2'b11:
q <= ~q;
default:
q <= q;
endcase
end
end

endmodule
4 bit Ring counter
module ringcounter(clk, rstn,out,num);
input clk;
input rstn;
input [3:0]num;
output reg [3:0] out;
integer i;

always @ (posedge clk) begin


if (rstn)
out <= num;
else begin
out[3] <= out[0];
for (i = 0; i < 3; i=i+1) begin
out[i] <= out[i+1];
end
end
end
endmodule
Clock generation time period 10ns and duty cycle is 40%

module clock(clk);
output reg clk;
initial
clk=1'b0;
always
begin
#6 clk=~clk;
#4 clk=~clk;
end
initial
#100 $finish;
endmodule
D FLIP FLOP WITHOUT RESET

module dff(clk,d,q);
input clk,d;
output reg q;

always @ (posedge clk)begin


q <= d;
end

endmodule
D flip-flop with synchronous reset

module dff(clk,reset,d,q);
input clk,reset,d;
output reg q;

always @ (posedge clk)begin


if(reset)
q <= 0;
else
q <= d;
end

endmodule
D flip-flop with asynchronous reset

module dff(clk,reset,d,q);
input clk,reset,d;
output reg q;

always @ (posedge clk or negedge reset)begin


if(~reset)
q <= 0;
else
q <= d;
end

endmodule
T flip flop without reset

module tff(clk,t,q);
input clk,t;
output reg q;

always @ (posedge clk)begin


if(t == 0)
q <= q;
else
q = ~q;
end

endmodule
T flip flop with synchronous reset

module tff(clk,reset,d,q);
input clk,reset,t;
output reg q;

always @ (posedge clk)begin


if(reset)
q <= 0;
else begin
if(t == 0)
q <= q;
else
q = ~q;
end
end

endmodule
T flip-flop with asynchronous reset

module tff(clk,reset,d,q);
input clk,reset,d;
output reg q;

always @ (posedge clk or negedge reset)begin


if(~reset)
q <= 0;
else begin
if(t == 0)
q <= q;
else
q = ~q;
end
end

endmodule

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