8086 MICROPROCESSOR

Pinouts

I-46
 8086 Pins
The 8086 comes in a 40 pin package which means that some pins have
more than one use or are multiplexed. The packaging technology of time
limited the number of pin that could be used.

In particular, the address lines 0 - 15 are multiplexed with data lines 0-15,
address lines 16-19 are multiplexed with status lines. These pins are

AD0 - AD15, A16/S3 - A19/S6

The 8086 has one other pin that is multiplexed and this is BHE’/S7.
BHE stands for Byte High Enable. This is an active low signal that is
asserted when there is data on the upper half of the data bus.

The 8086 has two modes of operation that changes the function of some pins.
The SDK-86 uses the 8086 in the minimum mode with the MN/MX’ pin tied to
5 volts. This is a simple single processor mode. The IBM PC uses an 8088
in the maximum mode with the MN/MX” pin tied to ground. This is the mode
required for a coprocessor like the 8087.

I-47
8086 Pins
In the minimum mode the following pins are available.

HOLD When this pin is high, another master is requesting control of the
local bus, e.g., a DMA controller.

HLDA HOLD Acknowledge: the 8086 signals that it is going to float

the local bus.

WR’ Write: the processor is performing a write memory or I/O operation.

M/IO’ Memory or I/O operation.

DT/R’ Data Transmit or Receive.

DEN’ Data Enable: data is on the multiplexed address/data pins.

ALE Address Latch Enable: the address is on the address/data pins.

This signal is used to capture the address in latches to establish the
address bus.

INTA’ Interrupt acknowledge: acknowledges external interrupt requests.

I-48
8086 Pins
The following are pins are available in both minimum and maximum modes.

VCC + 5 volt power supply pin.

GND Ground

RD’ READ: the processor is performing a read memory or I/O operation.

READY Acknowledgement from wait-state logic that the data transfer will
be completed.

RESET Stops processor and restarts execution from FFFF:0. Must be high
for 4 clocks. CS = 0FFFFH, IP = DS = SS = ES = Flags = 0000H, no
other registers are affected.

TEST’ The WAIT instruction waits for this pin to go low. Used with 8087.

NMI Non Maskable Interrupt: transition from low to high causes an

interrupt. Used for emergencies such as power failure.

INTR Interrupt request: masked by the IF bit in FLAG register.

CLK Clock: 33% duty cycle, i.e., high 1/3 the time.
I-49
 8086 Features
• 16-bit Arithmetic Logic Unit

• 16-bit data bus (8088 has 8-bit data bus)

• 20-bit address bus - 220 = 1,048,576 = 1 meg

The address refers to a byte in memory. In the 8088, these bytes come in on
the 8-bit data bus. In the 8086, bytes at even addresses come in on the low
half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper
half of the data bus (bits 8-15).

The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations. The 8088 needs two operations in either case.

The least significant byte of a word on an 8086 family microprocessor is at the

lower address.

I-8
 8086 Architecture
• The 8086 has two parts, the Bus Interface Unit (BIU) and the
Execution Unit (EU).

• The BIU fetches instructions, reads and writes data, and computes the
20-bit address.

• The EU decodes and executes the instructions using the 16-bit ALU.

• The BIU contains the following registers:

IP - the Instruction Pointer

CS - the Code Segment Register
DS - the Data Segment Register
SS - the Stack Segment Register
ES - the Extra Segment Register

The BIU fetches instructions using the CS and IP, written CS:IP, to contruct
the 20-bit address. Data is fetched using a segment register (usually the DS)
and an effective address (EA) computed by the EU depending on the
addressing mode.

I-9
8086 Block Diagram

I-10
 8086 Architecture
The EU contains the following 16-bit registers:

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register
SP - the Stack Pointer \ defaults to stack segment
BP - the Base Pointer /
SI - the Source Index Register
DI - the Destination Register

These are referred to as general-purpose registers, although, as seen by

their names, they often have a special-purpose use for some instructions.

The AX, BX, CX, and DX registers can be considers as two 8-bit registers, a
High byte and a Low byte. This allows byte operations and compatibility with
the previous generation of 8-bit processors, the 8080 and 8085. 8085 source
code could be translated in 8086 code and assembled. The 8-bit registers are:

AX --> AH,AL
BX --> BH,BL
CX --> CH,CL
DX --> DH,DL
I-11
 Flag Register
 Flag register contains information reflecting the current status of a
microprocessor. It also contains information which controls the
operation of the microprocessor.
15 0
 NT IOPL OF DF IF TF SF ZF  AF  PF  CF

 Control Flags  Status Flags

IF: Interrupt enable flag CF: Carry flag
DF: Direction flag PF: Parity flag
TF: Trap flag AF: Auxiliary carry flag
ZF: Zero flag
SF: Sign flag
OF: Overflow flag
NT: Nested task flag
IOPL: Input/output privilege level
 Flags Commonly Tested During the Execution of
Instructions
 There are five flag bits that are commonly tested during the execution
of instructions

 Sign Flag (Bit 7), SF: 0 for positive number and 1 for negative number

 Zero Flag (Bit 6), ZF: If the ALU output is 0, this bit is set (1); otherwise,
it is 0

 Carry Flag (Bit 0), CF: It contains the carry generated during the execution

 Auxiliary Carry, AF: Depending on the width of ALU inputs, this flag
(Bit 4) bit contains the carry generated at bit 3 (or, 7, 15)
of the 8088 ALU

 Parity Flag (bit2), PF: It is set (1) if the output of the ALU has even number
of ones; otherwise it is zero
 Direction Flag
 Direction Flag (DF) is used to control the way SI and DI are adjusted during the
execution of a string instruction
— DF=0, SI and DI will auto-increment during the execution; otherwise, SI and DI
auto-decrement
— Instruction to set DF: STD; Instruction to clear DF: CLD

— Example:

CLD DS : SI
MOV CX, 5 0510:0000 53 S SI CX=5
REP MOVSB 0510:0001 48 H SI CX=4
0510:0002 4F O SI CX=3
0510:0003 50 P SI CX=2
At the beginning of execution, 50 P SI CX=1
0510:0004
DS=0510H and SI=0000H
0510:0005 45 E SI CX=0
0510:0006 52 R
Source String
 8086 Programmer’s Model
ES Extra Segment
BIU registers
(20 bit adder) CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer

AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
EU registers SI Source Index Register
16 bit arithmetic DI Destination Index Register
FLAGS

I-13
 Memory Address Calculation

 Segment addresses must be stored Segment address 0000

in segment registers
 Offset is derived from the combination + Offset

of pointer registers, the Instruction Memory address

Pointer (IP), and immediate values

 Examples

CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction address 3 8 A B 4 Stack address 5 F F E 0

DS 1 2 3 4 0
DI + 0 0 2 2
Data address 1 2 3 6 2
 EEE/CSE 226
Segments
Address
Segment Starting address is segment 0H
register value shifted 4 places to the left.

CODE
64K Data
STACK Segment

DATA

EXTRA ← CS:0
64K Code
Segment
Segment
Registers

Segments are < or = 64K,

can overlap, start at an address
that ends in 0H. 0FFFFFH
MEMORY
I-14
 8086 Memory Terminology
Memory Segments
Segment 0H
Registers
01000H
DS: 0100H DATA
10FFFH

0B2000H
SS: 0B200H STACK
0C1FFFH

ES: 0CF00H 0CF000H

EXTRA
0DEFFFH

CS: 0FF00H
0FF000H
CODE
0FFFFFH

Segments are < or = 64K and can overlap.

Note that the Code segment is < 64K since 0FFFFFH is the highest address.
I-15
The Code Segment 0H

4000H
CS: 0400H

IP 0056H 4056H
CS:IP = 400:56
Logical Address

Memory
0400 0
Segment Register

Offset + 0056
Physical or 04056H
0FFFFFH

Absolute Address

The offset is the distance in bytes from the start of the segment.
The offset is given by the IP for the Code Segment.
Instructions are always fetched with using the CS register.

The physical address is also called the absolute address.

I-16
The Stack Segment 0H

0A000H
SS: 0A00

0A100H
SP 0100 SS:SP

Memory
0A00 0
Segment Register

Offset + 0100
0FFFFFH
Physical Address 0A100H

The offset is given by the SP register.

The stack is always referenced with respect to the stack segment register.
The stack grows toward decreasing memory locations.
The SP points to the last or top item on the stack.

PUSH - pre-decrement the SP

POP - post-increment the SP

I-17
The Data Segment 0H

05C00H
DS: 05C0

05C50H
EA 0050 DS:EA

Memory
05C0 0
Segment Register

Offset + 0050

Physical Address 0FFFFFH

05C50H

Data is usually fetched with respect to the DS register.

The effective address (EA) is the offset.
The EA depends on the addressing mode.

I-18
8086 memory Organization
Even addresses are on the low half
of the data bus (D0-D7).

Odd addresses are on the upper

half of the data bus (D8-D15).

A0 = 0 when data is on the low

half of the data bus.

BHE’ = 0 when data is on the upper

half of the data bus.
 MAX and MIN Modes
• In minmode, the 9 signals correspond to
control signals that are needed to operate
memory and I/O devices connected to the
8088.
• In maxmode, the 9 signals change their
functions; the 8088 now requires the use of
the 8288 bus controller to generate
memory and I/O read/write signals.
 Why MIN and MAX modes?
• Minmode signals can be directly decoded
by memory and I/O circuits, resulting in a
system with minimal hardware
requirements.
• Maxmode systems are more complicated,
but obtain the new signals that allow for bus
grants (e.g. DMA), and the use of an 8087
coprocessor.
 The 9 pins (min)
• **ALE: address latch enable (AD0 – AD7)
• **DEN: data enable (connect/disc. buffer)
• **WR: write (writing indication)
• *HOLD
• *HDLA: hold acknowledge
• *INTA: interrupt acknowledge
• IO/M: memory access or I/O access
• DT/R: data transmit / receive (direction)
• SSO: status
 The 9 pins (max)
• S0, S1, S2: status
• *RQ/GT0, RQ/GT1: request/grant
• *LOCK: locking the control of the sys. bus
• *QS1, QS0: queue status (tracking of
internal instruction queue).
• HIGH
 Instruction Types

 Data transfer instructions

 String instructions
 Arithmetic instructions
 Bit manipulation instructions
 Loop and jump instructions
 Subroutine and interrupt instructions
 Processor control instructions
 Addressing Modes

Addressing Modes Examples

 Immediate addressing MOV AL, 12H
 Register addressing MOV AL, BL
 Direct addressing MOV [500H], AL
 Register Indirect addressing MOV DL, [SI]
 Based addressing MOV AX, [BX+4]
 Indexed addressing MOV [DI-8], BL
 Based indexed addressing MOV [BP+SI], AH
 Based indexed with displacement addressing MOV CL, [BX+DI+2]

Exceptions
 String addressing
 Port addressing (e.g. IN AL, 79H)
 Data Transfer Instructions
 MOV Destination, Source
— Move data from source to destination; e.g. MOV [DI+100H], AH
— It does not modify flags
 For 80x86 family, directly moving data from one memory location to
another memory location is not allowed

MOV [SI], [5000H]

 When the size of data is not clear, assembler directives are used

MOV [SI], 0
 BYTE PTR MOV BYTE PTR [SI], 12H
 WORD PTR MOV WORD PTR [SI], 12H
 DWORD PTR MOV DWORD PTR [SI], 12H

 You can not move an immediate data to segment register by MOV

MOV DS, 1234H
 Instructions for Stack Operations
 What is a Stack ?
— A stack is a collection of memory locations. It always follows the rule of
last-in-firs-out
— Generally, SS and SP are used to trace where is the latest date written into stack

 PUSH Source
— Push data (word) onto stack
— It does not modify flags
— For Example: PUSH AX (assume ax=1234H, SS=1000H, SP=2000H
before PUSH AX)

1000:1FFD ?? 1000:1FFD ??
1000:1FFE ?? SS:SP 1000:1FFE 34
1000:1FFF ?? 1000:1FFF 12
SS:SP 1000:2000 ?? 1000:2000 ?? 12 34

Before PUSH AX, SP = 2000H After PUSH AX, SP = 1FFEH AX

 Decrementing the stack pointer during a push is a standard way of implementing stacks in hardware
 Instructions for Stack Operations
 PUSHF
— Push the values of the flag register onto stack
— It does not modify flags

 POP Destination
— Pop word off stack
— It does not modify flags
— For example: POP AX

1000:1FFD ?? 1000:1FFD ??
SP 1000:1FFE 34 1000:1FFE 34
1000:1FFF 12 1000:1FFF 12
1000:2000 EC SP 1000:2000 EC 12 34

After POP AX, SP = 2000H AX

Before POP, SP = 1FFEH

 POPF
— Pop word from the stack to the flag register
— It modifies all flags
 Data Transfer Instructions
 SAHF
— Store data in AH to the low 8 bits of the flag register
— It modifies flags: AF, CF, PF, SF, ZF

 LAHF
— Copies bits 0-7 of the flags register into AH
— It does not modify flags

 LDS Destination Source

— Load 4-byte data (pointer) in memory to two 16-bit registers
— Source operand gives the memory location
— The first two bytes are copied to the register specified in the destination operand;
the second two bytes are copied to register DS
— It does not modify flags

 LES Destination Source

— It is identical to LDS except that the second two bytes are copied to ES
— It does not modify flags
 Data Transfer Instructions
 LEA Destination Source
— Transfers the offset address of source (must be a memory location) to the
destination register
— It does not modify flags

 XCHG Destination Source

— It exchanges the content of destination and source
— One operand must be a microprocessor register, the other one can be a register
or a memory location
— It does not modify flags

 XLAT
— Replace the data in AL with a data in a user defined look-up table
— BX stores the beginning address of the table
— At the beginning of the execution, the number in AL is used as the
index of the look-up table
— It does not modify flags
 String Instructions
 String is a collection of bytes, words, or long-words that can be up to 64KB
in length
 String instructions can have at most two operands. One is referred to as source
string and the other one is called destination string
— Source string must locate in Data Segment and SI register points to the current
element of the source string
— Destination string must locate in Extra Segment and DI register points to the current
element of the destination string
DS : SI ES : DI
0510:0000 53 S 02A8:2000 53 S
0510:0001 48 H 02A8:2001 48 H
0510:0002 4F O 02A8:2002 4F O
0510:0003 50 P 02A8:2003 50 P
0510:0004 50 P 02A8:2004 50 P
0510:0005 45 E 02A8:2005 49 I
0510:0006 52 R 02A8:2006 4E N
Source String Destination String
 Repeat Prefix Instructions
 REP String Instruction
— The prefix instruction makes the microprocessor repeatedly execute the string instruction
until CX decrements to 0 (During the execution, CX is decreased by one when the string
instruction is executed one time).
— For Example:

MOV CX, 5
REP MOVSB
By the above two instructions, the microprocessor will execute MOVSB 5 times.

— Execution flow of REP MOVSB::

While (CX!=0) Check_CX: If CX!=0 Then

{ CX = CX –1;
CX = CX –1; OR MOVSB;
MOVSB; goto Check_CX;
} end if
 String Instructions
 MOVSB (MOVSW)
— Move byte (word) at memory location DS:SI to memory location ES:DI and
update SI and DI according to DF and the width of the data being transferred
— It does not modify flags
—Example:

DS : SI ES : DI
MOV AX, 0510H 0510:0000 53 S 0300:0100
MOV DS, AX 0510:0001 48 H
MOV SI, 0
0510:0002 4F O
MOV AX, 0300H
MOV ES, AX 0510:0003 50 P
MOV DI, 100H 0510:0004 50 P
CLD 0510:0005 45 E
MOV CX, 5
0510:0006 52 R
REP MOVSB
Source String Destination String
 String Instructions
 CMPSB (CMPSW)
— Compare bytes (words) at memory locations DS:SI and ES:DI;
update SI and DI according to DF and the width of the data being compared
— It modifies flags
—Example:

Assume: ES = 02A8H DS : SI
DI = 2000H ES : DI
0510:0000 53 S 02A8:2000 53 S
DS = 0510H
SI = 0000H 0510:0001 48 H 02A8:2001 48 H
0510:0002 4F O 02A8:2002 4F O
CLD 0510:0003 50 P 50
02A8:2003 P
MOV CX, 9 50 P 50 P
0510:0004 02A8:2004
REPZ CMPSB 0510:0005 45 E I
49
02A8:2005
0510:0006 52 R 02A8:2006 4E N
What’s the values of CX after
Source String Destination String
The execution?
 String Instructions
 SCASB (SCASW)
— Move byte (word) in AL (AX) and at memory location ES:DI;
update DI according to DF and the width of the data being compared
— It modifies flags

 LODSB (LODSW)
— Load byte (word) at memory location DS:SI to AL (AX);
update SI according to DF and the width of the data being transferred
— It does not modify flags

 STOSB (STOSW)
— Store byte (word) at in AL (AX) to memory location ES:DI;
update DI according to DF and the width of the data being transferred
— It does not modify flags
 Repeat Prefix Instructions
 REPZ String Instruction
— Repeat the execution of the string instruction until CX=0 or zero flag is clear

 REPNZ String Instruction

— Repeat the execution of the string instruction until CX=0 or zero flag is set

 REPE String Instruction

— Repeat the execution of the string instruction until CX=0 or zero flag is clear

 REPNE String Instruction

— Repeat the execution of the string instruction until CX=0 or zero flag is set
 Loops and Conditional Jumps
All loops and conditional jumps are SHORT jumps, i.e., the target must
be in the range of an 8-bit signed displacement (-128 to +127).

The displacement is the number that, when added to the IP, changes the
IP to point at the jump target. Remember the IP is pointing at the next
instruction when this occurs.

The loop instructions perform several operations at one time but do not
change any flags.

LOOP decrements CX and jumps if CX is not zero.

LOOPNZ or LOOPNE -- loop while not zero or not equal: decrements CX
and jumps if CX is not zero or the zero flag ZF = 0.
LOOPZ or LOOPE -- loop while zero or equal: decrements CX and jumps
if CX is zero or the zero flag ZF = 1.

The conditional jump instructions often follow a compare CMP or TEST

instruction. These two instructions only affect the FLAG register and not
the destination. CMP does a SUBtract (dest - src) and TEST does an AND.

For example, if a CMP is followed by a JG (jump greater than), then the

jump is taken if the destination is greater than the source.
Test is used to see if a bit or bits are set in a word or byte such as when
determining the status of a peripheral device.
I-39
 Conditional Jumps
Name/Alt Meaning Flag setting
JE/JZ Jump equal/zero ZF = 1
JNE/JNZ Jump not equal/zero ZF = 0
JL/JNGE Jump less than/not greater than or = (SF xor OF) = 1
JNL/JGE Jump not less than/greater than or = (SF xor OF) = 0
JG/JNLE Jump greater than/not less than or = ((SF xor OF) or ZF) = 0
JNG/JLE Jump not greater than/ less than or = ((SF xor OF) or ZF) = 1
JB/JNAE Jump below/not above or equal CF = 1
JNB/JAE Jump not below/above or equal CF = 0
JA/JNBE Jump above/not below or equal (CF or ZF) = 0
JNA/JBE Jump not above/ below or equal (CF or ZF) = 1

JS Jump on sign (jump negative) SF = 1

JNS Jump on not sign (jump positive) SF = 0
JO Jump on overflow OF = 1
JNO Jump on no overflow OF = 0
JP/JPE Jump parity/parity even PF = 1
JNP/JPO Jump no parity/parity odd PF = 0

JCXZ Jump on CX = 0 ---

I-40