VLSI Testing

積體電路測試

Design For Testability

Part 2: External Scan (JTAG)
Professor James Chien-Mo Li 李建模
Lab. of Dependable Systems
Graduate Institute of Electronics Engineering
National Taiwan University

1 VLSI Test 12.1 © National Taiwan University

 Course Roadmap (Design Topics)

DFT Built-in Self Test

Test Compression Memory Testing

SOC Testing FunctionTests

2 VLSI Test 12.1 © National Taiwan University

 Motivating Problem
• You buy 6 chips and assemble a board
 Your manager asks you to test the board and chips, how?

chip #1 chip #2 chip #3

TDI
TMS
TCK
TDO

chip#6 chip #5 chip #4

3 Board
VLSI Test 12.1 © National Taiwan University
 Why Am I Learning This?
• This chapter allows us to understand
 JTAG, IEEE 1149.1 standard
 board-level testing

“In school we learn things then take the test,

In life we take the test then learn things.”

(Admon Israel)
4 VLSI Test 12.1 © National Taiwan University
 DFT – Part 2
• Introduction
• JTAG Architecture and Components
• JTAG Instructions
• Conclusion

IC #1 IC #2 IC #3

TDI
TMS
TCK
TDO

IC #4 IC #5 IC #6

5 VLSI Test 12.1 © National Taiwan University

 What is External Scan ?
• External scan
 Stitch system input/output pins into a shift register
 as opposed to internal scan
 also known as boundary scan

System
Inputs {
System
Logic
} System
Outputs

TMS TAP Control

TCK Controller signals Boundary scan
MUX Internal scan
Instruction Decoder
TDO
Instruction Register
TDI Bypass Register

6 VLSI Test 12.1 © National Taiwan University

 Boundary Scan
• Boundary scan standard is needed
Allow chips from different vendors to be tested together
• IEEE 1149.1-1990
 Boundary scan standard
 aka JTAG
• Why use boundary scan?
 1. Board-level test and diagnosis
 2. Test on-board interconnect among chips
 3. Test on-chip system logic

7 VLSI Test 12.1 © National Taiwan University

 Board Level Test and Diagnosis
• All chips are stitched into one JTAG scan chain
• Off-line testing and on-line debug are supported

chip #1 chip #2 chip #3

TDI
TMS
TCK
TDO

chip#6 chip #5 chip #4

8 Board
VLSI Test 12.1 © National Taiwan University
 Test On-board Wires Among Chips

chip #1 chip #2

1 1/0 =D
0 0
1 1/0

Input: X X X X 1 0 1 X X X X X X X X X First scan in

Output: X X X X X X X X X D 0 D X X X X First scan out

*assume wired-AND fault model

9 VLSI Test 12.1 © National Taiwan University

 Test On-chip System Logic
• How to test a chip already assembled on board. Cannot use ATE

First scan out

First scan in

Input: X 1 1 X X X X X Good Output: X X X X X X 1 X

Input: X 0 1 X X X X X Good Output: X X X X X X 0 X
Input: X 1 0 X X X X X Good Output: X X X X X X 0 X

10 VLSI Test 12.1 © National Taiwan University

 Quiz
Q: Which of the following is NOT true about boundary scan?
A. Boundary scan enables board-level testing
B. Requires standard because chips are from different vendors
C. Boundary scan can replace internal scan

ANS:

11 VLSI Test 12.1 © National Taiwan University

 DFT – Part 2
• Introduction
• JTAG Architecture and Components

TAP
 TAP controller
 Registers
 Instruction Decoder
• JTAG Instructions
• Conclusion
IC #1 IC #2 IC #3

TDI
TMS
TCK
TDO

IC #4 IC #5 IC #6

12 VLSI Test 12.1 © National Taiwan University

 JTAG Architecture
• JTAG Components
 1. Test Access Port (TAP)
 2. TAP controller
 3. Registers
 Instruction Register, Boundary Scan Register, Bypass Register…
 4. Instruction Decoder

{ }
System
System System
Logic
Inputs Outputs

TMS TAP Control

TCK Controller signals Boundary scan
Internal scan
Instruction Decoder MUX
TDO
Instruction Register
TDI Bypass Register
Optional Register

13 VLSI Test 12.1 © National Taiwan University

 Test Access Port, TAP
• 4 mandatory TAP • 1 optional TAP
 TDI, Test Data Input  TRST, Reset of Test Logic
 TDO, Test Data Output ( Active Low)
 TCK, Test Clock
 TMS, Test Mode Select

System
Primary Primary
Logic
Inputs Outputs

TMS TAP Control

TCK Controller signals

MUX
Instruction Decoder
TAP TDO
Instruction Register
TDI Bypass Register

14 VLSI Test 12.1 © National Taiwan University

 TAP Controller TMS
1
Test-Logic-
Reset
DR=Data IR=Instruction
• Control JTAG operation 0 Register Register

• 16-state Finite State Machine Run-Test/ 1 Select- 1 Select- 1

0
Idle DR-Scan IR-Scan


Clock is TCK 0

1 1
 Input is TMS Capture-DR Capture-IR

• Test-Logic-Reset 0 0

 Reset JTAG Circuits Shift-DR 0 Shift-IR 0

 How to reset JTAG? 1 1

 TMS=111..., or
1 1
Exit1-DR Exit1-IR

 TRST = 0 0 0

Pause-DR 0 Pause-IR 0

1 1
System
Logic 0 0
Exit2-DR Exit2-IR
Note: TMS TAP Control 1 1
State transition TCK Controller
signals

MUX
occurs at rising Instruction Decoder
TDO Update-DR Update-IR
Instruction Register
edge of TCK
TDI Bypass Register
1 0 1 0

15 VLSI Test 12.1 © National Taiwan University

 Summary
• IEEE 1149.1-1990

Boundary scan standard
 aka JTAG (Joint Test Action Group)
• Why use boundary scan?
 Board-level, interconnect, system logic
• JTAG components
 1. Test Access Port (TAP)
 2. TAP controller (16-state FSM)
 3. Registers
 4. Instruction Decoder

16 VLSI Test 12.1 © National Taiwan University

 FFT 1
Test-Logic-
Reset
0
• Q: What is mini number of 1’s
TMS
Run-Test/ 1 Select- 1 Select- 1
0
Idle DR-Scan IR-Scan
needed to initialize JTAG?
0
Regardless of initial state. 1 1
Capture-DR Capture-IR
 TMS=111…
0 0

Shift-DR 0 Shift-IR 0

1 1

1 1
Exit1-DR Exit1-IR

0 0

Pause-DR 0 Pause-IR 0

1 1

0 0
Exit2-DR Exit2-IR

1 1

Update-DR Update-IR

1 0 1 0

17 VLSI Test 12.1 © National Taiwan University