AN5780

Application note

Migration of applications from ATMEGA328 family to STM32C0 series

microcontrollers

Introduction

This application note provides some guidelines and methodology to migrate easily an Arduino® application from the
ATMEGA328 family to the STM32C0 series platform. It groups together all the most important information and lists the main
aspects that must be addressed, providing guidelines on the hardware, firmware and peripheral migration.
For a better understanding, the user needs to be familiar with STM32 microcontrollers.
For additional information, refer to the documents in Table 1.

AN5780 - Rev 1 - December 2022 www.st.com

For further information contact your local STMicroelectronics sales office.
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General information

1 General information

This document applies to all STM32C0 series devices. All these products are Arm®-based microcontrollers.
Note: Arm® is a registered trademark of Arm® Limited (or its subsidiaries) in the US and/or elsewhere.

Table 1. Document and website references

Reference Document

RM0490 STM32C0x1 advanced Arm®-based 32-bit MCUs(1)

Arm® Cortex®-M0+ 32-bit MCU, 32 KB flash, 6 KB RAM, 2 x USART, timers, ADC,

DS13866
communication interface I/Fs, 2-3.6V(1)

Arm® Cortex®-M0+ 32-bit MCU, 32 KB flash, 12 KB RAM, 2x USART, timers, ADC,

DS13867
communication interface I/Fs, 2-3.6V (1)

Cortex®-M0+ programming manual for STM32C0, STM32L0, STM32G0, STM32WL and

PM0223
STM32WB series(1)

AN5373 Getting started with STM32C0 series hardware development (1)

AN4894 EEPROM emulation techniques and software for STM32 microcontrollers
STM32CubeProg https://www.st.com/stm32cubeprog
Wiki: https://github.com/stm32duino/wiki/wiki
STM32duino Forum: https://www.stm32duino.com/
Arduino_Core_STM32:‑https://github.com/stm32duino/Arduino_Core_STM32(2)

Getting started https://github.com/stm32duino/wiki/wiki/Getting-Started#installing-stm32-cores (2)

Open Bootloader library

1. Available at www.st.com. Contact STMicroelectronics when more information is needed

2. This URL belongs to a third party. It is active at document publication, however STMicroelectronics shall not be liable for any
change, move or inactivation of the URL or the referenced material.

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STM32C0 series overview

2 STM32C0 series overview

The STM32C0 series include all ATMEGA328 standard peripherals like SPI, UART (see Table 5 for more details).
But also a set of peripherals with advanced features and optimized power consumption level like:
The STM32C0 devices include a set of peripherals with advanced features and optimized power consumption
compared to the ATMEGA328:
• 32-bit CPU with CPU frequency at 48 MHz
• DMA
• 12-bit ADC

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Hardware migration

3 Hardware migration

3.1 Pinout compatibility

STM32C0 devices use a different system of power distribution (single supply pair), with the merging of VDDA and
VDD. The STM32C0 has better GPIO density than the ATMEG328 (5 V supply voltage).
Due to the significant difference between ATMEG328 and STM32C0, there is no pin to pin compatible. In case of
replacement, the PCB routing needs to be reworked or use an STM32C031C6 discovery kit (see Section 3.2 ).

Table 2. Additional IOs for STM32C0 vs ATMEG328

Package pin count GPIO number in STM32C0 GPIO number in ATMEG328 Difference I/Os

28 26 23 +3
32 30 25 +5

Table 3. Package type

Package pins STM32C0 family ATMEG328

8 SO8N -
12 WLCSP -
20 TSSOP/UFQFPN -
28 UFQFPN VQFPN / SDIP
32 UFQFPN / LQFP VQFPN / TQFN
48 UFQFPN / LQFP -

3.2 Board migration

To help the user to migrate easily from the ATMEGA328 to the STM32C0, a special STM32C0316-DK discovery
board has been designed with a DIP28 Arduino®-compatible pinout. The Arduino® Uno board or homemade PCB
can be easily plug-in at the place of the ATMEGA328 as shown in Figure 1:

Figure 1. Arduino® uno board with STMC0316-DK

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Board migration

The two MCUs do not use the same pin name. Table 4 shows a comparison between the two architectures.
The biggest difference is concerning the ADC reference voltage pin. In the STM32 discovery board VREF is
connected to VDD, so it can be impossible to use it in the Arduino® board or homemade PCB. Otherwise, with the
help of STM32duino, the Arduino® core supports the STM32C0.

Table 4. Arduino® pin comparison

Arduino® pin STM32C0 ATMEGA328

RESET PF2-NRESET PC6

A5 PB10 PC5
A3 PA9 PC3
A2 PA10 PC2
A1 PA5 PC1
A4 PB11 PC4
A0 PA4 PC0
AREF Not connected AREF
D19/SCL PB11 PC5
D18/SDA PB10 PC4
D13 PA1 PB5
D12 PA6 PB4
D11 PA7 PB3
D10 PB0 PB2
D9 PA8 PB1
D8 PD3 PB0
D7 PD2 PD7
D6 PD1 PD6
D5 PD0 PD5
D4 PA0 PD4
D3 PC7 PD3
D2 PC6 PD2
D1 PA2 PD1
D0 PA3 PD0

If the user use shield like Arduino® or ST extension board (compatible with Arduino® R3 connector), it is
necessary to raise the header with a shield-stacking header.

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Board migration

Figure 2. Arduino® shield-stacking header

Note: If the application needs to use A4 and A5 as ADC input, it is mandatory to unsolder R8 and R9 resistors. These
pull-up resistors are used as I2C as default.

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Boot mode selection

4 Boot mode selection

The boot configuration of the STM32C0 is based on the STM32 M0+ core products.
In the ATMEGA328 family the software can boot only from flash memory or bootloader while STM32C0 series
permits to locate the BOOT vector in flash memory, system memory (boot loader) or RAM, based on the Table 4.
In fact it relocates the boot memory start address, for example if the user chose to boot from the main flash
memory, this memory area is aliased in the boot memory space (0x0000 0000), but still accessible from its
original memory space (0x0800 0000). It is reciprocal to other boot area.
The ATMEGA328 does not integer a system bootloader like in the STM32C0 (bootloader programmed during
production) but something close to the open bootloader in other words the user need to add is own code. If the
user wants to know more about the open bootloarder on the STM32: Open Bootloader library
A feature to check if the device is virgin has been implemented on the STM32C0 series. If the BOOT0 pin is
defining main flash memory as the target boot area and after loading option byte, the flash memory interface
checks if the first location of the main memory is programmed and return the result on FLASH_ACR register.

Table 5. Boot mode configuration

Boot mode configuration Selected boot

BOOT_LOCK bit nBOOT1 bit BOOT0 pin nBOOT_SEL bit nBOOT0 bit area

0 X 0 0 X Main flash memory

0 1 1 0 X System memory
0 0 1 0 X Embedded SRAM
0 X X 1 1 Main flash memory
System
0 1 X 1 0
memory
Embedded
0 0 X 1 0
SRAM
Main flash memory
1 X X X X
forced

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Peripheral migration

5 Peripheral migration

5.1 STM32 product cross-compatibility

The STM32C0 and the ATMEGA328 shared the same set of peripherals with a few exceptions. The STM32C0
has: four timer 16 bit, DMA, RTC, I2C. But it does not have a comparator like ATMEGA328.

Table 6. Peripheral summary of STM32C0 series and ATMEGA328

Peripheral STM32C0 series ATMEGA328

Power supply See Table 8 power supply

Core Cortex® M0+ megaAVR

Maximum frequency 48 MHz 20 MHz

flash memory Up to 32 kBytes 32 kBytes
SRAM Up to 12 kBytes 2 kBytes
Emulated in the flash
EEPROM 1 kBytes
memory(1)
General purpose 4 -
TIMER Advanced 1 1
Basic - 1
ADC 1 1
DMA (number of independently configurable channels
3 -
request)
USART 2 1
SPI 1 1

I2C 1 1

I2S (Inter-IC-sound) 1 -
CRC X -
RTC X -
WWDG X X
IWDG X -

Comparotor -(2) X

1. Refer to AN4894
2. STM32G0 series support this feature.

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System architecture

5.2 System architecture

The STM32C0 series implement an Arm® 32-bit architecture with the M0+ core. While the ATMEGA328 family
uses the Atmel AVR propriety core. The first one uses a Von Neumann architecture and the second one uses a
Harvard architecture.

Table 7. Comparison of CPU core

Feature M0+ megaAVR

Data path 32-bit 8-bit

Architecture Von Neumann Harvard
Pipeline Two stages One level
Instruction set RISC RISC
Program bus data width 32-bit 8-bit
Pre-fetch buffer 2 x 32-bit 16-bit
Debug interface 2-wire (SWD) 1-wire
ALU - YES
Cache instruction 16 bytes -

5.3 Debug
In addition to use the Arduino® API, it can be used the STM32 family Arm® debug tool. Two wires are needed to
debug the MCU.
The new debug methodology allows:
• SW-DP: serial wire
• BPU: break point unit
• DWT: data watchpoint trigger
• Flexible debug pinout assignment
• NVIC debug
• MCU debug box (support for low-power modes, control over peripheral clocks, etc.)

Figure 3. Block diagram of STM32C0 MCU and Arm® Cortex®-M0+-level debug support

STM32 MCU debug support

Cortex-M0 debug support

Bus matrix System

interface
Cortex-M0
Core

Debug AP

Bridge DBGMCU
SWDIO SW-DP
SWCLK Debug AP
NVIC

DWT

BPU
DT19240V1

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Power control peripheral

5.4 Power control peripheral

In the STM32C0 series, the PWR controller presents some differences versus ATMEGA328. The differences are
summarized on the Table 8.

Table 8. Power control peripheral

PWR STM32C0 ATMEGA328

• VDD: 2.0 V to 3.6 V is the

external power supply for the
internal regulator and the system
analog such as reset, power • VCC: 2.7 V to 5.5 V is the digital
management and internal clocks supply voltage
• VDDA: is the analog power supply • AVCC: 2.7 V to 5.5 V is the supply
Power supplies
for the A/D converter and shorted voltage pin for the A/D converter.
to VDD due to the low number of It is mandatory to have it between
pins VCC-0.3 or VCC+0.3
• VDDIO: is the power supply for the
I/Os and shorted to VDD due to
the low number of pins
• Integrated POR/PDR/BOR
Power supply supervisor • Integrated POR and BOR circuitry
circuitry

5.5 Power consumption mode

The STM32C0 series and the STM32 family generally have different low-power mode. There are four different
low modes: sleep, stop, standby and shutdown. The STM32C0 series has better dynamic and ultra-low power
consumption than the ATMEGA328. Below there is a description of a different power consumption mode. All data
is typical values contained in the datasheet (VDD=3 V and temperature=25°C).
The dynamic consumption of the STM32C0 is better, for example the ATMEGA3238 has a power consumption at
8 MHz as much as the STM32C0 has a power consumption at 48 MHz.
The low-power modes use different names. But they have similarities, so it is easy to compare them.

Table 9. Power consumption comparison

Consumption mode Clock STM32C011/31 ATMEGA328 Unit

8 MHz 0.655 4.2

Run mode 4 MHz 0.365 1.2 mA
1 MHz 0.225 0.2
8 MHz 0.200 1.2
Idle/sleep mode 4 MHz 0.135 0.3 mA
1 MHz 0.089 0.04
Stop/power-save mode Low speed clock on 74 4.2 μA
Standby/power down
All clock off 7450 900 nA
mode
Shutdown mode All clock off 19 - nA

• Sleep mode corresponds to the ATMEGA328 idle mode. The CPU is clocked off, but other peripherals and
interrupt controller continue to run. Moreover, in the STM32C0 is possible to have the memory.
• Stop mode is similar to the active power save mode. The high-speed clock is stopped, and the SRAM is
retained. In both products it is possible to wake-up the product with a timer.
• Standby mode is similar to the power-down mode. The high-speed clock is off, the low-speed clock can
be running if the application uses IWDG, but the main difference is that the RAM is powered off in the
STM32C0.

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Power consumption mode

• Shutdown mode has no equivalent in the ATMEGA328. It Is the ultimate low-power mode. All clocks and
peripherals are off.
• Wake-up source: the Table 10 shows the wake-up source comparison.

Table 10. Wake-up source comparison

PWR STM32C0 ATMEGA328

Idle:
– Internal and external interrupts
– WDT (watch dog timer)
– Reset
ADC noise reduction:
– WDT
– Reset
– BOR reset
– Internal interrupt (TWI address
match, Timer/Counter2 SPM/
Sleep mode: EEPROM ready)
– Peripheral event/interrupt – External interrupt (INT0 or INT1)
– EXTI interrupt/event Power-down:
– NVIC IRQ interrupt – WDT
– IWDG – Reset
– nReset – BOR reset
Stop mode: – Internal interrupt (TWI address
– Peripheral event/interrupt match)
– EXTI interrupt/event – External interrupt (INT0 or INT1)
Power-save:
Low-power modes and wake-up sources – NVIC IRQ interrupt
– IWDG – WDT
– nReset – Reset
Standby mode: – BOR reset
– Wake-up pins – Internal interrupt (TWI address
match, Timer/Counter2)
– IWDG
– External interrupt (INT0 or INT1)
– nReset
Standby:
Shutdown mode:
– WDT
– Wakeup pins
– Reset
– nReset
– BOR reset
– Internal interrupt (TWI address
match)
– External interrupt (INT0 or INT1)
Extended standby:
– WDT
– Reset
– BOR reset
– Internal interrupt (TWI address
match, Timer/Counter2)
– External interrupt (INT0 or INT1)

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Reset and clock controller (RCC) interface

5.6 Reset and clock controller (RCC) interface

5.6.1 Clocks

Table 11. Clock configuration STM32C0 vs ATMEGA328

RCC STM32C0 ATMEGA328

HSI48 high-speed fully integrated RC oscillator at 48 MHz -

HSI8 - 8 MHz internal RC oscillator
LSI low-speed fully integrated RC oscillator at 32 kHz 128 kHz RC oscillator
HSE 4 to 48 MHz 0.4 to 16 MHz
LSE 32.768 kHz 32.768 kHz
System clock source HSI48, LSI, HSE, LSE HSI8, HSE, LSI, LSE

• Up to 48 MHz • Up to 16 MHz
System clock frequency
• 12 MHz after reset based on HSI • 1 MHz after reset
APB frequency Up to 24 MHz -
RTC clock source LSI, LSE or HSE clocks divided by 32 -
MCO (PIN1, PIN2): LSI, LSE, SYSCLK, HSI48, HSE LSCO (pin):
Clock output CLKO (PIN): System clock
LSI, LSE available in stop mode
Internal/external clock measurement inputs:
Internal oscillator
measurement and • TIM14 inputs: GPIO, RTC, HSE/32, MCO, MCO2 -
calibration • TIM16 inputs: GPIO, LSI, LSE, MCO2
• TIM17 inputs: GPIO, HSE/32, MCO, MCO2

Table 12. High and low speed clock accuracy comparison

Clock accuracy Temperature STM32C0 ATMEGA328

Full range -2.5% to 2% ±14%

HSI factory calibrated 0 to 85°C ±1% -
30°C -0.37% to 0.83% ±2%
LSI Full range -7.8% to 3% ±40%

The STM32C0 has a good clock accuracy compared to the ATMEGA328. This can permit to clock other
peripheral with the CCO output. HSI is used for USART communication.

5.6.2 Reset
In the STM32C0 series there are different types of resets.
The first one is the power reset, which set all register as their reset values excepted when exiting standby mode
where the register outside VCORE domain are not impacted (back up registers, IWDG, standby/shutdown mode
control).
The second one is the system reset, which reset all registers to their reset value excepted the reset flags, the
RTC registers and the back-up registers.
The last one is the RTC domain reset, which only affects the RTC domains (LSE oscillator, RTC and RCC_CSR1
register).
Through specific option bits, the STM32C0 has also the possibility to change the configuration the NRST pin as:
• Reset input/output
• Reset input
• GPIO

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Nested vectored interrupt controller (NVIC)

Table 13. Reset source comparison

Reset source STM32C0 series ATMEGA328

Power-on Reset/Power-down reset X(1)(2) X

Brown-out reset X(1) X

Exit from standby mode X(1) -

Exit from shutdown mode X(1) -

Low level on the NRST pin X(2) X

WWDG reset X(2) -

IWDG reset X(2) X

Software reset X(2) -

Low-power mode security reset X(2) -

Option byte loader reset X(2) -

1. Power reset
2. System reset

5.7 Nested vectored interrupt controller (NVIC)

As both products have a different core. The interrupt handler is different. The STM32C0 devices use a nested
vectored interrupt controller (NVIC). It is more advanced and therefore new feature like the trail chaining.
In the AVR core, when an interrupt occurs, all interrupts are disable by hardware whose means that it is not
possible to have multiple interrupts.
Unlike the Cortex M0+ where it is possible to have multiple interrupts in the same. Thanks to tail chaining
the program does not return to the main execution but jumps directly to the next interrupt, saving time by not
recovering again the context saving of the main execution.

Figure 4. Tail chaining

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DMA

Table 14. Interrupts features comparison

Parameter STM32C0 ATMEGA328

Interrupt vectors Up to 32 interrupt vectors (+ 5 system ones) Up to 26 interrupt vectors

Non-maskable interrupt Yes -
4 levels
Interrupt priorities The lower the address the higher is the priority
lower number = higher priority
Disable interrupts yes, apart from NMI and HardFault Yes
2 external interrupts linked to two IOs
External interrupts 16 external interrupt channels linked to IO lines
3 Pin change Interrupt linked to all IOs
Reset vector 4 bytes (address of the IRQ procedure) 3 bytes (boot reset address)
16 cycles to save context 4 cycles to save context
Interrupt latency
16 cycles to restore context 4 cycles to restore context
Tail chaining Yes No

The Cortex M0+ has six systems interrupt (five more than STM8). These interrupts are non-maskable, they are
always activated. The priority of Reset, NMI and HardFault are fixed, in contrast to SVC, PendSV and SysTick,
which are programmable.

Table 15. System interrupts comparison

Offset STM32C0 ATMEGA328

Reset – address of the

0x00 -
application start
0x04 Reset – address of the application start -
NMI– Non Maskable Interrupt connected to SRAM parity error, HSE and LSE clock
0x08 -
security systems (may be slightly different in other STM32 lines)
0x0C HardFault – reports all isues related to bus/memory accesses -
0x2C SVC – system service call – software interrupt. Used by operating systems -
PendSV – pendable request for system service software interrupt. Used by operating
0x38 -
systems
SysTick – interrupt from built in 24bit counter (part of the core) – used for delays,
0x3C -
timeouts and operating system timing

5.8 DMA
Direct memory access (DMA) is a new IP in the STM32C0 compared to the ATMEGA328P. It is clearly a major
asset to improve the product consumption and the CPU bandwidth. Data transfer without the CPU is allowed. It is
between peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-peripheral.
In the STM32C0, the DMA has three different channels. Each channel has four levels of priority (very high,
high, medium, and low), the channel one has priority over a request of channel two. Different transfer sizes are
available (byte, half-word, and word). A circular buffer management can be used.

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GPIO interface

5.9 GPIO interface

The STM32C0 has seven configurations bits while the ATMEGA has only three bits. So, it can be possible:
• To choose between four different output speeds
• To have pull-up or pull-down
• To choose between seven GPIO configuration:
– Input floating
– Input pull-up
– Input pull-down
– Analog
– Output open drain with pull-up or pull-down capability
– Output push-pull with pull-up or pull-down capability
– Alternate function push-pull with pull-up or pull-down capability
– Alternate function open drain with pull-up or pull-down capability
They have also different VIH/VIL value due to the huge different between their power supply architecture.

Table 16. GPIO input voltage comparison

Voltage STM32C0 ATMEGA328

VIL 0 V to 0.3xVDD -0.5 to 0.3xVDD

VIH 0.7xVDD to 5 V 0.6xVDD to VDD+0.5

5.10 RTC
The real time clock (RTC) is a new feature in STM32C0 that measure the time increasing. It can be clocked
by LSE, LSI or the HSE (divided by a prescaler), but to have the best accuracy it needs to use the LSE clock
source with 32.768 kHz external crystal. The RTC can measure the calendar date: sub-second, seconds, minutes,
hours (12 or 24 format), weekday, date with an automatic correction for 28, 29 (leap year), 30, and 31 days of the
month. It has one programmable alarm.
The RTC also can be used as timer to automatically wake up the product.

5.11 USART

Table 17. USART peripheral

Feature STM32C0 ATMEGA328

Configurable oversampling method 16 or 8 No

Programmable data word length 7, 8 or 9 bits 5,6,7,8 or 9 bits
Continuous communications using DMA
DMA Received/transmitted bytes are buffered in reserved -
SRAM using centralized DMA.
Separate signal polarity control for transmission and
X -
reception
Swappable Tx/Rx pin configuration X -
Wake-up from low-power mode X -

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I2C

5.12 I2C

Table 18. I2C configuration

Feature STM32C0 ATMEGA328

• Standard-mode (up to 100 kHz)

Communication speeds • Fast-mode (up to 400 kHz) Up to 400 kHz data transfer speed
• Fast-mode Plus (up to 1 MHz)
Addressing mode 7-bit and 10-bit 7-bit
SMBus 3.0 -
PMBus 1.3 -
DMA capability 1-byte buffer -
Clock choice PCLK, SYSCLK, HSIKER -

5.13 Flash memory

The STM32C0 has a maximum frequency at 48 MHz and the flash memory maximum frequency is 24 MHz. To
compensate the flash memory speed and to be sure to have valid and uncorrupted data, a wait state feature has
been added. It is not implemented on ATMEGA328 because the CPU speed does not go above the flash memory
speed.

Table 19. Flash memory

Feature STM32C0 ATMEGA328

Page size • 2 kbytes • 64 bytes

• Read protection activated by option (RDP)
• Two write protection areas, selected by option (WRP) • Two different areas (read while write
Security • Two proprietary codes read protection areas, selected by section and no read while write section)
option (PCROP) • Readout protection
• Securable memory area

5.14 SRAM

Table 20. SRAM density comparison

Maximum Flash memory density STM32C0 ATMEGA328

STM32C011x4: 6 Kbytes
16 Kbytes -
STM32C031x4:12 Kbytes
STM32C011x6: 6 Kbytes
32 Kbytes 2 Kbytes
STM32C031x6:12 Kbytes

5.15 Timer

Table 21. Timers available in STM32C0 series MCUs

Capture/
Counter Counter DMA request Complementary
Timer type Timer Prescaler factor compare
resolution type generation outputs
channels

Advanced Up, down, integer from 1 to 4

TIM1 16-bit YES 3
control up/down 65536 (6 internals)

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ADC

Capture/
Counter Counter DMA request Complementary
Timer type Timer Prescaler factor compare
resolution type generation outputs
channels

Up, down, integer from 1 to

TIM3 16-bit YES 4 -
up/down 65536

General integer from 1 to

TIM14 16-bit Up - 1 -
purpose 65536
TIM16 integer from 1 to
16-bit Up YES 1 1
TIM17 65536

Systick STK 24-bit Down HCLK/8 - - -

All timers in the STM32C0 are 16-bit and the maximum clock is now 48 MHz and one 24-bit timer inside the
Cortex M0+ core, which is generally used as 1 ms time base.

5.16 ADC

Table 22. ADC differences between STM32C0 series and ATMEGA328

Feature STM32C0 series ATMEGA 328

Resolution 12-bit, 10-bit, 8-bit, or 6-bit configurable 10 bits

Conversion time Up to 0.4 μs (2.5Msps) Up to 13 μs (76.9 ksps) and 15 ksps in full resolution
Self-calibration YES -
Programmable sampling time YES -
DMA support YES -
Conversion mode Single + Continuous Single
Oversampling YES -
Number of externa channel Up to 19 8
• Vsense (temp sensor)
• Vrefint • Vsense (temp sensor)
Internal channel
• VDDA • Vrefint
• VSSA

5.17 SPI

Table 23. SPI comparison

Feature STM32C0 ATMEGA328

Half-duplex synchronous transfer on two lines (with bidirectional data

X -
line)
Simplex synchronous transfers on two lines (with unidirectional data
X -
line)
Data size selection 4 to 16-bit data size selection Only 8 bits
Multi-master mode capability X -
Faster communication - Maximum SPI speed 12 MHz 10 MHz
SPI Motorola support X -
Two 32-bit embedded Rx and Tx
DMA capability -
FIFOs
CRC feature X -

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Watchdog

Feature STM32C0 ATMEGA328

Enhanced TI and NSS pulse modes support X -

I2S X -

Moreover, the STM32C0 is I2S compatible. If the application needs an audio interphase.

5.18 Watchdog
The STM32C0 series has two different watchdogs: the independent watchdog (IWDG) and one the system
window watchdog (WWDG). It is one more compared to the ATMEGA328.

Independent watchdog (IWDG)

The watchdog timer is integrated both in the ATMEGA328 and in the STM32C0. But in the ATMEGA328, it is not
possible to define the counter reload value, the user can just choose between different oscillator dividers.
Nevertheless, in the STM32C0 series, this watchdog can be driven in two different ways:
• Without the window option activated the IWDG works. The counter value is reloaded when the key is
written in IWDG_KR. And the chip reset, when the down counter value becomes lower than 0x000.
• With the window option activated the counter value can be reloaded by two different manners. With writing
a special key in IWDG_KR. The second and new way is to refresh the counter value, by a value written in
the window register. With this new feature it adds a new conditional reset in addition to the one described
before. The circuit is reset if the down counter is reloaded outside the window.

Table 24. IWDG comparison

Feature STM32C0 series ATMEGA328

Clock source LSI (32 kHz) 128 kHz

Down counter size 12-bit NA
Window option Yes -
Minimum time out period 125 µs 16 ms
Maximum time out period 32.76 s 8.0 s
Debug mode (suspend the IWDG when the core is halted) Yes -
Freeze IWDG in low power mode Yes (STOP and STANDBY) -

System window watchdog (WWDG)

The STM32C0 has another watchdog dedicated to detecting the occurrence of a software fault. Usually this fault
is generated by external interference or by unforeseen logical conditions, which causes the application program
to give up its normal sequence. The watchdog circuits generates an MCU reset on expiry of a programmed time,
unless the program refreshes the contents of the down-counter before the T6 bit becomes cleared.

Table 25. WWDG

Feature STM32C0 series

Clock source HSI, HSE, LSI, LSE

Static prescaler 4096
Variable prescaler 1-128
Minimum time out period for FWWDG=16 MHz 0.512 ms

Maximum time out period for FWWDG=16 MHz 2097.152 ms

WWDG interrupt Yes

Debug mode (suspend the WWDG when the core is halted) Yes

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Option and engineering bytes

5.19 Option and engineering bytes

The fuse and lock bits of the ATMEGA328 can be equivalent of the option bytes present in the STM32C0. These
bits are used to customize the configuration of the MCU like the flash protection, watchdog selection, lock the
debug capability.
The STM32C0 series has a dedicated programming protocol with a locking mechanism to protect the option bytes
from unwanted writes and they are complemented to maximize the robustness.

Table 26. Option bytes comparison

Feature STM32C0 series ATMEGA328

Register size 8x64-bits (32-bit option byte + 32-bit complemented option byte) 4x8-bits
• NRST pin, reset holder, BOR and low power mode entry
protection
• BOR
• Boot configuration
Peripheral • Boot size and configuration
• Multiple bonding
configuration • Watchdog selection
• Clock remapping
• Memory protection
• Watchdog selection and freeze option
• Flash protection (RDP, PCROP, WRP, SEC)

In addition to the option bytes, the STM32C0 has some engineering bytes that are visible to the user. They
contain some useful information that is written during production testing, such as:
• Unique device ID
• Flash size
• Package type
• Calibration value of internal voltage reference and temperature sensor

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Firmware migration using the Arduino® IDE

6 Firmware migration using the Arduino® IDE

To migrate an Arduino® application from the ATMEGA328 family to the STM32C0 series, it is necessary to install
STM32 Arduino® core and select the appropriate board as explained in Getting started. This core supports all
Arduino® software APIs from ATMEGA328, and even more.
This means that all Arduino® build-in examples can be used, like blinky, AnalogReadSerial, toneMelody.
Furthermore, the external Arduino® libraries (for sensor, shields, ...) can be used if they respect Arduino® API's
recommendation. If the application or the external libraries do not respect Arduino® API (for example with direct
register access), then porting is necessary.
Firstly, the user must install STM32CubeProgrammer (available in STM32CubeProg).
To program the STM32C0 microcontrollers with the IDE and STM32CubeProgrammer the user needs to use the
STLINK. Thus, with STM32C0316-DX it is necessary to use an external module like STLINK-V3 (MB1762) with
the B2B connector.

Figure 5. Arduino® uno board with STM32C0316-DK and STLINK

To know more about the use of STM32C0 and Arduino® core see more details in STM32duino.
In addition to the Arduino® standard API, the STM32 Arduino® core provides other APIs to get access to some of
STM32 hardware.
If needed, it is also possible to access to the STM32Cube drivers (HAL and LL) within Arduino® so that the
application can access to full STM32 hardware capabilities.

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 AN5780

Revision history
Table 27. Document revision history

Date Version Changes

19-Dec-2022 1 Initial release.

AN5780 - Rev 1 page 21/25

 AN5780
Contents

Contents
1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 STM32C0 series overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Hardware migration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Pinout compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Board migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Boot mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Peripheral migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 STM32 product cross-compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4 Power control peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.5 Power consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.6 Reset and clock controller (RCC) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.9 GPIO interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.10 RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.11 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.12 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.13 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.14 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.15 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.16 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.17 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.18 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.19 Option and engineering bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Firmware migration using the Arduino® IDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

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 AN5780
List of tables

List of tables
Table 1. Document and website references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Additional IOs for STM32C0 vs ATMEG328. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Package type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. Arduino® pin comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Peripheral summary of STM32C0 series and ATMEGA328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Comparison of CPU core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Power control peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Power consumption comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Wake-up source comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. Clock configuration STM32C0 vs ATMEGA328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 12. High and low speed clock accuracy comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 13. Reset source comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 14. Interrupts features comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 15. System interrupts comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 16. GPIO input voltage comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 17. USART peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 18. I2C configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 19. Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 20. SRAM density comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 21. Timers available in STM32C0 series MCUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 22. ADC differences between STM32C0 series and ATMEGA328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 23. SPI comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 24. IWDG comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 25. WWDG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 26. Option bytes comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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 AN5780
List of figures

List of figures
Figure 1. Arduino® uno board with STMC0316-DK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Arduino® shield-stacking header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram of STM32C0 MCU and Arm® Cortex®-M0+-level debug support. . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Tail chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Arduino® uno board with STM32C0316-DK and STLINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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 AN5780

IMPORTANT NOTICE – READ CAREFULLY

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