TPS73101, TPS73115, TPS73118

TPS73125, TPS73130, TPS73132

TPS73133, TPS73150
www.ti.com SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

Cap-Free, NMOS, 150mA Low Dropout Regulator

with Reverse Current Protection

FEATURES DESCRIPTION
• Stable with No Output Capacitor or Any Value The TPS731xx family of low-dropout (LDO) linear
or Type of Capacitor voltage regulators uses a new topology: an NMOS
• Input Voltage Range of 1.7V to 5.5V pass element in a voltage-follower configuration. This
topology is stable using output capacitors with low
• Ultralow Dropout Voltage: 30mV Typ
ESR, and even allows operation without a capacitor.
• Excellent Load Transient Response—with or It also provides high reverse blockage (low reverse
without Optional Output Capacitor current) and ground pin current that is nearly constant
• New NMOS Topology Provides Low Reverse over all values of output current.
Leakage Current The TPS731xx uses an advanced BiCMOS process
• Low Noise: 30µVRMS Typ (10kHz to 100kHz) to yield high precision while delivering very low
• 0.5% Initial Accuracy dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1µA and
• 1% Overall Accuracy over Line, Load, and ideal for portable applications. The extremely low
Temperature output noise (30µVRMS with 0.1µF CNR) is ideal for
• Less Than 1µA Max IQ in Shutdown Mode powering VCOs. These devices are protected by
• Thermal Shutdown and Specified Min/Max thermal shutdown and foldback current limit.
Current Limit Protection DBV PACKAGE
• Available in Multiple Output Voltage Versions SOT23
(TOP VIEW)
– Fixed Outputs of 1.2V, 1.5V, 1.8V, 2.5V, 3.0V,
3.3V, and 5.0V
IN 1 5 OUT
– Adjustable Outputs From 1.20V to 5.5V
– Custom Outputs Available GND 2

EN 3 4 NR/FB
APPLICATIONS
• Portable/Battery-Powered Equipment
• Post-Regulation for Switching Supplies
• Noise-Sensitive Circuitry such as VCOs
• Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
Optional Optional

VIN IN OUT VOUT

TPS731xx
EN GND NR

Optional

Typical Application Circuit for Fixed-Voltage Versions

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2003–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
TPS73133, TPS73150 www.ti.com
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

ORDERING INFORMATION
SPECIFIED
PACKAGE-LEAD PACKAGE ORDERING
PRODUCT VOUT (1) TEMPERATURE TRANSPORT MEDIA,
(DESIGNATOR) (2) MARKING NUMBER
RANGE QUANTITY
Adjustable TPS73101DBVT Tape and Reel, 250
TPS73101 SOT23-5 (DBV) -40°C to +125°C PWYQ
or 1.2V (3) TPS73101DBVR Tape and Reel, 3000
TPS73115DBVT Tape and Reel, 250
TPS73115 1.5V SOT23-5 (DBV) -40°C to +125°C T31
TPS73115DBVR Tape and Reel, 3000
TPS73118DBVT Tape and Reel, 250
TPS73118 1.8V SOT23-5 (DBV) -40°C to +125°C T32
TPS73118DBVR Tape and Reel, 3000
TPS73125DBVT Tape and Reel, 250
TPS73125 2.5V SOT23-5 (DBV) -40°C to +125°C PHWI
TPS73125DBVR Tape and Reel, 3000
TPS73130DBVT Tape and Reel, 250
TPS73130 3.0V SOT23-5 (DBV) -40°C to +125°C T33
TPS73130DBVR Tape and Reel, 3000
TPS73132DBVT Tape and Reel, 250
TPS73132 3.2V SOT23-5 (DBV) -40°C to +125°C T52
TPS73132DBVR Tape and Reel, 3000
TPS73133DBVT Tape and Reel, 250
TPS73133 3.3V SOT23-5 (DBV) -40°C to +125°C T34
TPS73133DBVR Tape and Reel, 3000
TPS73150DBVT Tape and Reel, 250
TPS73150 5.0V SOT23-5 (DBV) -40°C to +125°C T35
TPS73150DBVR Tape and Reel, 3000

(1) Custom output voltages from 1.3V to 4V in 100mV increments are available on a quick-turn basis for prototyping. Minimum order
quantities apply; contact factory for details and availability.
(2) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet.
(3) For fixed 1.2V operation, tie FB to OUT.

ABSOLUTE MAXIMUM RATINGS

over operating junction temperature range unless otherwise noted (1)
TPS731xx UNIT
VIN range -0.3 to 6.0 V
VEN range -0.3 to 6.0 V
VOUT range -0.3 to 5.5 V
Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, TJ -55 to +150 °C
Storage temperature range -65 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

2
 TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
www.ti.com
TPS73133, TPS73150
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

POWER DISSIPATION RATINGS (1)

DERATING FACTOR TA ≤ 25°C TA = 70°C TA = 85°C
BOARD PACKAGE RΘJC RΘJA
ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
Low-K (2) DBV 64°C/W 255°C/W 3.9mW/°C 390mW 215mW 155mW
High-K (3) DBV 64°C/W 180°C/W 5.6mW/°C 560mW 310mW 225mW

(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.

ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = -40°C to +125°C), VIN = VOUT(nom) + 0.5V (1), IOUT = 10mA, VEN = 1.7V, and COUT =
0.1µF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range (1) 1.7 5.5 V
VFB Internal reference (TPS73101) TJ = 25°C 1.198 1.20 1.210 V
Output voltage range (TPS73101) VFB 5.5 - VDO V
Nominal TJ = 25°C -0.5 +0.5
VOUT
Accuracy (1) VOUT + 0.5V ≤ VIN ≤ 5.5V; %
VIN, IOUT, and T -1.0 ±0.5 +1.0
10 mA ≤ IOUT≤ 150mA
∆VOUT%/∆VIN Line regulation (1) VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V 0.01 %/V
1mA ≤ IOUT ≤ 150mA 0.002
∆VOUT%/∆IOUT Load regulation %/mA
10mA ≤ IOUT ≤ 150mA 0.0005
Dropout voltage (2)
VDO IOUT = 150mA 30 100 mV
(VIN = VOUT (nom) - 0.1V)
ZO(DO) Output impedance in dropout 1.7 V ≤ VIN ≤ VOUT + VDO 0.25 Ω
ICL Output current limit VOUT = 0.9 × VOUT(nom) 150 360 500 mA
ISC Short-circuit current VOUT = 0V 200 mA
IREV Reverse leakage current (3) (-IIN) VEN ≤ 0.5V, 0V≤ VIN ≤ VOUT 0.1 10 µA
IOUT = 10mA (IQ) 400 550
IGND Ground pin current µA
IOUT = 150mA 550 750
ISHDN Shutdown current (IGND) VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5 0.02 1 µA
IFB FB pin current (TPS73101) 0.1 0.3 µA
Power-supply rejection ratio f = 100Hz, IOUT = 150 mA 58
PSRR dB
(ripple rejection) f = 10kHz, IOUT = 150 mA 37
Output noise voltage COUT = 10µF, No CNR 27 × VOUT
VN µVRMS
BW = 10Hz - 100kHz COUT = 10µF, CNR = 0.01µF 8.5 × VOUT
VOUT = 3V, RL = 30Ω
tSTR Startup time 600 µs
COUT = 1 µF, CNR = 0.01 µF
VEN(HI) Enable high (enabled) 1.7 VIN V
VEN(LO) Enable low (shutdown) 0 0.5 V
IEN(HI) Enable pin current (enabled) VEN = 5.5V 0.02 0.1 µA
Shutdown Temp increasing 160
TSD Thermal shutdown temperature °C
Reset Temp decreasing 140
TJ Operating junction temperature -40 125 °C

(1) Minimum VIN = VOUT +VDO or 1.7V, whichever isgreater.

(2) VDO is not measured for the TPS73115 (VO(nom) = 1.5V) since minimum VIN = 1.7V.
(3) Fixed-voltage versions only; refer to the Applications section for more information.

3
TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
TPS73133, TPS73150 www.ti.com
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

FUNCTIONAL BLOCK DIAGRAMS

IN

4MHz
Charge Pump

EN
Thermal
Protection
Ref
Servo
27kΩ
Bandgap
Error
Amp
Current
Limit OUT
8kΩ
GND
R1

R1 + R2 = 80kΩ R2

NR

Figure 1. Fixed Voltage Version

IN Table 1. Standard 1%
Resistor Values for
Common Output Voltages
VO R1 R2
4MHz
1.2V Short Open
Charge Pump
1.5V 23.2kΩ 95.3kΩ
EN
Thermal 1.8V 28.0kΩ 56.2kΩ
Protection
Ref
2.5V 39.2kΩ 36.5kΩ
Servo 2.8V 44.2kΩ 33.2kΩ
27kΩ 3.0V 46.4kΩ 30.9kΩ
Bandgap
Error
3.3V 52.3kΩ 30.1kΩ
Amp 5.0V 78.7kΩ 24.9kΩ
OUT
Current
NOTE: VOUT = (R1 + R2)/R2 × 1.204;
Limit
GND R1R2 ≅ 19kΩ for best
8kΩ 80kΩ
R1 accuracy.
FB

R2

Figure 2. Adjustable Voltage Version

4
 TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
www.ti.com
TPS73133, TPS73150
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

PIN ASSIGNMENTS
DBV PACKAGE
SOT23
(TOP VIEW)

IN 1 5 OUT

GND 2

EN 3 4 NR/FB

TERMINAL FUNCTIONS
TERMINAL
SOT23 DESCRIPTION
NAME (DBV)
PIN NO.
IN 1 Unregulated input supply
GND 2 Ground
EN 3 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to
IN if not used.
NR 4 Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the
internal bandgap, reducing output noise to very low levels.
FB 4 Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the
output voltage of the device.
OUT 5 Output of the regulator. There are no output capacitor requirements for stability.

5
TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
TPS73133, TPS73150 www.ti.com
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.

LOAD REGULATION LINE REGULATION

0.5 0.20
Referred to IOUT = 10mA Referred to VIN = VOUT + 0.5V at IOUT = 10mA
0.4 0.15
0.3
0.10
Change in VOUT (%)

Change in VOUT (%)

0.2 +25
C
+125
C
0.1 0.05

0 0
−0.1 −0.05
−0.2 −40
C
−0.10
−0.3
−0.4 −0.15

−0.5 −0.20
0 15 30 45 60 75 90 105 120 135 150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
IOUT (mA) VIN − VOUT (V)

Figure 3. Figure 4.

DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE

50 50
TPS73125DBV TPS73125DBV
+125
C
40 40

30 30
VDO (mV)

VDO (mV)

+25
C
20 20

10 10
−40
C

0 0
0 30 60 90 120 150 −50 −25 0 25 50 75 100 125
IOUT (mA) Temperature (
C)

Figure 5. Figure 6.

OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM

30 18
I OUT = 10mA
I OUT = 10mA 16 All Voltage Versions
25
14
Percent of Units (%)

Percent of Units (%)

20 12

10
15
8

10 6
4
5
2
0 0
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1

−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0

0
10
20
30
40
50
60
70
80
90
100

VOUT Error (%) Worst Case dVOUT/dT (ppm/
C)

Figure 7. Figure 8.

6
 TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
www.ti.com
TPS73133, TPS73150
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS (continued)

For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.

GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE

700 700
IOUT = 150mA
600 600

500 500
IGND (µA)

IGND (µA)
400 400

300 300

200 200 VIN = 5.5V

VIN = 5.5V VIN = 4V
100 VIN = 4V 100 VIN = 2V
VIN = 2V
0 0
0 30 60 90 120 150 −50 −25 0 25 50 75 100 125
I OUT (mA) Temperature (
C)

Figure 9. Figure 10.

CURRENT LIMIT vs VOUT GROUND PIN CURRENT in SHUTDOWN

(FOLDBACK) vs TEMPERATURE
400 1
VENABLE = 0.5V
350 VIN = VO + 0.5V
ICL
300
Current Limit (mA)

250
IGND (µA)

ISC
200 0.1

150

100

50
TPS73133
0 0.01
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 −50 −25 0 25 50 75 100 125
VOUT (V) Temperature (
C)

Figure 11. Figure 12.

CURRENT LIMIT vs VIN CURRENT LIMIT vs TEMPERATURE

500 500

450 450

400 400
Current Limit (mA)

Current Limit (mA)

350 350

300 300

250 250

200 200

150 150
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 −50 −25 0 25 50 75 100 125
VIN (V) Temperature (
C)

Figure 13. Figure 14.

7
TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
TPS73133, TPS73150 www.ti.com
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS (continued)

For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.

PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN - VOUT

90 40
IOUT = 100mA IOUT = 1mA
80 COUT = Any 35
COUT = 1µF
70 30
IOUT = 1mA
Ripple Rejection (dB)

60 COUT = 10µF
25

PSRR (dB)
IO = 100mA
50 CO = 1µF
IOUT = 1mA 20
40 C OUT = Any
15
30
10
20 I OUT = 100mA Frequency = 100kHz
IOUT = Any COUT = 10µF 5 COUT = 10µF
10
COUT = 0µF VOUT = 2.5V
0 0
10 100 1k 10k 100k 1M 10M 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Frequency (Hz) VIN − VOUT (V)

Figure 15. Figure 16.

NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY

CNR = 0µF CNR = 0.01µF
1 1

C OUT = 1µF
eN (µV/√Hz)

eN (µV/√Hz)

COUT = 0µF COUT = 1µF

0.1 0.1
COUT = 10µF

COUT = 0µF
COUT = 10µF

I OUT = 150mA I OUT = 150mA

0.01 0.01
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

Figure 17. Figure 18.

RMS NOISE VOLTAGE vs COUT RMS NOISE VOLTAGE vs CNR

60 140
VOUT = 5.0V
50 120
VOUT = 5.0V
100
40
VN (RMS)

VN (RMS)

80 VOUT = 3.3V
30 VOUT = 3.3V
60
20
40 VOUT = 1.5V
VOUT = 1.5V
10 20
CNR = 0.01µF COUT = 0µF
10Hz < Frequency < 100kHz 10Hz < Frequency < 100kHz
0 0
0.1 1 10 1p 10p 100p 1n 10n
COUT (µF) CNR (F)

Figure 19. Figure 20.

8
 TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
www.ti.com
TPS73133, TPS73150
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS (continued)

For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.

TPS73133 TPS73133
LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
VIN = 3.8V COUT = 0µF IOUT = 150mA
40mV/tick VOUT
COUT = 0µF
50mV/div VOUT
COUT = 1µF
40mV/tick VOUT

COUT = 10µF COUT = 100µF

40mV/tick VOUT 50mV/div VOUT

5.5V dVIN
150mA = 0.5V/µs
dt
25mA/tick IOUT 4.5V
10mA 1V/div VIN

10µs/div 10µs/div

Figure 21. Figure 22.

TPS73133 TPS73133
TURN-ON RESPONSE TURN-OFF RESPONSE
RL = 1kΩ RL = 20Ω
COUT = 0µF VOUT COUT = 10µF
RL = 20Ω R L = 20Ω
1V/div CO UT = 1µF 1V/div C OUT = 1µF
RL = 1kΩ
RL = 20Ω COUT = 0µF
COUT = 10µF
VOUT
2V 2V
VEN

1V/div 1V/div
0V 0V
VEN

100µs/div 100µs/div

Figure 23. Figure 24.

TPS73133
POWER UP / POWER DOWN IENABLE vs TEMPERATURE
6 10

5
VIN
4
VOUT
1
3
IENABLE (nA)
Volts

1
0.1
0

−1

−2 0.01
50ms/div −50 −25 0 25 50 75 100 125
Temperature (
C)

Figure 25. Figure 26.

9
TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
TPS73133, TPS73150 www.ti.com
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS (continued)

For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.

TPS73101 TPS73101
RMS NOISE VOLTAGE vs CADJ IFBvs TEMPERATURE
60 160

55 140

50 120

45 100
VN (rms)

IFB (nA)
40 80

35 60
VOUT = 2.5V
30 40
COUT = 0µF
25 R1 = 39.2kΩ 20
10Hz < Frequency < 100kHz
20 0
10p 100p 1n 10n −50 −25 0 25 50 75 100 125
CFB (F) Temperature (
C)

Figure 27. Figure 28.

TPS73101 TPS73101
LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION

CFB = 10nF VOUT = 2.5V

R1 = 39.2kΩ CFB = 10nF
COUT = 0µF COUT = 0µF
50mV/div VOUT 100mV/div VOUT

COUT = 10µF
100mV/div VOUT
COUT = 10µF
50mV/div VOUT
4.5V
150mA 3.5V
VIN
10mA
IOUT
25µs/div 5µs/div

Figure 29. Figure 30.

10
 TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
www.ti.com
TPS73133, TPS73150
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

APPLICATION INFORMATION

The TPS731xx belongs to a family of new generation

LDO regulators that use an NMOS pass transistor to INPUT AND OUTPUT CAPACITOR
achieve ultra-low-dropout performance, reverse cur- REQUIREMENTS
rent blockage, and freedom from output capacitor Although an input capacitor is not required for stab-
constraints. These features, combined with low noise ility, it is good analog design practice to connect a
and an enable input, make the TPS731xx ideal for 0.1µF to 1µF low ESR capacitor across the input
portable applications. This regulator family offers a supply near the regulator. This counteracts reactive
wide selection of fixed output voltage versions and an input sources and improves transient response, noise
adjustable output version. All versions have thermal rejection, and ripple rejection. A higher-value capaci-
and over-current protection, including foldback cur- tor may be necessary if large, fast rise-time load
rent limit. transients are anticipated or the device is located
several inches from the power source.
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the connections The TPS731xx does not require an output capacitor
for the adjustable output version (TPS73101). for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
Optional input capacitor. Optional output capacitor.
types and values of capacitors. In applications where
May improve source May improve load transient, VIN - VOUT < 0.5V and multiple low ESR capacitors
impedance, noise, or PSRR. noise, or PSRR. are in parallel, ringing may occur when the product of
VIN VOUT
COUT and total ESR drops below 50nΩF. Total ESR
IN OUT
includes all parasitic resistances, including capacitor
TPS731xx
ESR and board, socket, and solder joint resistance.
EN GND NR In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.

Optional bypass OUTPUT NOISE

capacitor to reduce
output noise. A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS731xx and
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions it generates approximately 32µVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
Optional input capacitor. Optional output capacitor.
same gain as the reference voltage, so that the noise
May improve source May improve load transient, voltage of the regulator is approximately given by:
impedance, noise, or PSRR. noise, or PSRR. (R  R2) V
V N  32
VRMS
1  32
VRMS
OUT
VIN IN OUT VOUT R2 VREF (1)
TPS731xx R1 CFB
Since the value of VREF is 1.2V, this relationship
EN GND FB reduces to:
R2

Optional capacitor
V N(
VRMS)  27 

V RMS
V


V OUT(V)
(2)
(R1 + R2)
VOUT = × 1.204 reduces output noise.
R2
for the case of no CNR.
Figure 32. Typical Application Circuit for An internal 27kΩ resistor in series with the noise
Adjustable-Voltage Versions reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
R1 and R2 can be calculated for any output voltage capacitor, CNR, is connected from NR to ground. For
using the formula shown in Figure 32. Sample re- CNR = 10nF, the total noise in the 10Hz to 100kHz
sistor values for common output voltages are shown bandwidth is reduced by a factor of ~3.2, giving the
in Figure 2. For best accuracy, make the parallel approximate relationship:
combination of R1 and R2 approximately 19kΩ.
V N(
VRMS)  8.5 
VV 
V
RMS
OUT(V)
(3)
for CNR = 10nF.

11
TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
TPS73133, TPS73150 www.ti.com
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

This noise reduction effect is shown as RMS Noise DROPOUT VOLTAGE

Voltage vs CNR in the Typical Characteristics section.
The TPS731xx uses an NMOS pass transistor to
The TPS73101 adjustable version does not have the achieve extremely low dropout. When (VIN - VOUT) is
noise-reduction pin available. However, connecting a less than the dropout voltage (VDO), the NMOS pass
feedback capacitor, CFB, from the output to the FB pin device is in its linear region of operation and the
will reduce output noise and improve load transient input-to-output resistance is the RDS-ON of the NMOS
performance. pass element.
The TPS731xx uses an internal charge pump to For large step changes in load current, the TPS731xx
develop an internal supply voltage sufficient to drive requires a larger voltage drop across it to avoid
the gate of the NMOS pass element above VOUT. The degraded transient response. The boundary of this
charge pump generates ~250µV of switching noise at transient dropout region is approximately twice the dc
~4MHz; however, charge-pump noise contribution is dropout. Values of VIN - VOUT above this line insure
negligible at the output of the regulator for most normal transient response.
values of IOUT and COUT.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
BOARD LAYOUT RECOMMENDATION TO recover from a load transient is a function of the
IMPROVE PSRR AND NOISE PERFORMANCE magnitude of the change in load current rate, the rate
To improve ac performance such as PSRR, output of change in load current, and the available head-
noise, and transient response, it is recommended that room (VIN to VOUT voltage drop). Under worst-case
the PCB be designed with separate ground planes for conditions [full-scale instantaneous load change with
VIN and VOUT, with each ground plane connected only (VIN - VOUT) close to dc dropout levels], the TPS731xx
at the GND pin of the device. In addition, the ground can take a couple of hundred microseconds to return
connection for the bypass capacitor should connect to the specified regulation accuracy.
directly to the GND pin of the device.
TRANSIENT RESPONSE
INTERNAL CURRENT LIMIT The low open-loop output impedance provided by the
The TPS731xx internal current limit helps protect the NMOS pass element in a voltage follower configur-
regulator during fault conditions. Foldback current ation allows operation without an output capacitor for
helps to protect the regulator from damage during many applications. As with any regulator, the addition
output short-circuit conditions by reducing current of a capacitor (nominal value 1µF) from the output pin
limit when VOUT drops below 0.5V. See Figure 11 in to ground will reduce undershoot magnitude but
the Typical Characteristics section for a graph of IOUT increase duration. In the adjustable version, the
vs VOUT. addition of a capacitor, CFB, from the output to the
adjust pin will also improve the transient response.
SHUTDOWN The TPS731xx does not have active pull-down when
The Enable pin is active high and is compatible with the output is over-voltage. This allows applications
standard TTL-CMOS levels. VEN below 0.5V (max) that connect higher voltage sources, such as alter-
turns the regulator off and drops the ground pin nate power supplies, to the output. This also results
current to approximately 10nA. When shutdown capa- in an output overshoot of several percent if the load
bility is not required, the Enable pin can be connected current quickly drops to zero when a capacitor is
to VIN. When a pull-up resistor is used, and operation connected to the output. The duration of overshoot
down to 1.8V is required, use pull-up resistor values can be reduced by adding a load resistor. The
below 50 kΩ. overshoot decays at a rate determined by output
capacitor COUT and the internal/external load resist-
ance. The rate of decay is given by:
(Fixed voltage version)
V OUT
dVdt 
C OUT
80k
(4)

12
 TPS73101, TPS73115, TPS73118
TPS73125, TPS73130, TPS73132
www.ti.com
TPS73133, TPS73150
SBVS034E – SEPTEMBER 2003 – REVISED SEPTEMBER 2004

(Adjustable voltage version) reliability, thermal protection should trigger at least

VOUT 35°C above the maximum expected ambient con-
dVdt  dition of your application. This produces a worst-case
C OUT
80k
 (R 1  R 2) (5) junction temperature of 125°C at the highest ex-
pected ambient temperature and worst-case load.
REVERSE CURRENT
The internal protection circuitry of the TPS731xx has
The NMOS pass element of the TPS731xx provides been designed to protect against overload conditions.
inherent protection against current flow from the It was not intended to replace proper heatsinking.
output of the regulator to the input when the gate of Continuously running the TPS731xx into thermal
the pass device is pulled low. To ensure that all shutdown will degrade device reliability.
charge is removed from the gate of the pass element,
the enable pin must be driven low before the input POWER DISSIPATION
voltage is removed. If this is not done, the pass
element may be left on due to stored charge on the The ability to remove heat from the die is different for
gate. each package type, presenting different consider-
ations in the PCB layout. The PCB area around the
After the enable pin is driven low, no bias voltage is device that is free of other components moves the
needed on any pin for reverse current blocking. Note heat from the device to the ambient air. Performance
that reverse current is specified as the current flowing data for JEDEC low- and high-K boards are shown in
out of the IN pin due to voltage applied on the OUT the Power Dissipation Ratings table. Using heavier
pin. There will be additional current flowing into the copper will increase the effectiveness in removing
OUT pin due to the 80kΩ internal resistor divider to heat from the device. The addition of plated
ground (see Figure 1 and Figure 2). through-holes to heat-dissipating layers will also im-
For the TPS73101, reverse current may flow when prove the heat-sink effectiveness.
VFB is more than 1.0V above VIN. Power dissipation depends on input voltage and load
conditions. Power dissipation is equal to the product
THERMAL PROTECTION of the output current times the voltage drop across
Thermal protection disables the output when the the output pass element (VIN to VOUT):
junction temperature rises to approximately 160°C, P D  (VIN  VOUT)
I OUT (6)
allowing the device to cool. When the junction tem-
perature cools to approximately 140°C, the output Power dissipation can be minimized by using the
circuitry is again enabled. Depending on power dissi- lowest possible input voltage necessary to assure the
pation, thermal resistance, and ambient temperature, required output voltage.
the thermal protection circuit may cycle on and off.
This limits the dissipation of the regulator, protecting Package Mounting
it from damage due to overheating. Solder pad footprint recommendations for the
Any tendency to activate the thermal protection circuit TPS731xx are presented in Application Bulletin
indicates excessive power dissipation or an inad- Solder Pad Recommendations for Surface-Mount De-
equate heatsink. For reliable operation, junction tem- vices (AB-132), available from the Texas Instruments
perature should be limited to 125°C maximum. To web site at www.ti.com.
estimate the margin of safety in a complete design
(including heatsink), increase the ambient tempera-
ture until the thermal protection is triggered; use
worst-case loads and signal conditions. For good

13
 PACKAGE OPTION ADDENDUM
www.ti.com 15-Feb-2005

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TPS73101DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73101DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73115DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73115DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73118DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73118DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73118DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73130DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73130DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73132DBVR ACTIVE SOT-23 DBV 5 3000 None Call TI Call TI
TPS73132DBVT ACTIVE SOT-23 DBV 5 250 None Call TI Call TI
TPS73133DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73133DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73150DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73150DBVT ACTIVE SOT-23 DBV 5 250 None Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
www.ti.com 15-Feb-2005

temperature.

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Addendum-Page 2
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