Data Conversion Fundamentals
Data Conversion Fundamentals
Data Conversion
Fundamentals
Technical Tutorial – Data Converters
Basic Level
June 2002
Vibration
Weight
Analog World
Digital World
Speed
Voltage
Current
Resistance
? 1001010010
1001101010
Pressure
Temperature
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How Do We Communicate With The
Microprocessor?
ADC
ADC µP
µP DAC
DAC
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How Does the Binary System Work?
3 2 1 0
2 2 2 2
8 4 2 1
5=4+1 0 1 0 1
7=4+2+1 0 1 1 1
3=2+1 0 0 1 1
The natural binary system uses a base 2 raised to a power from 0…N.
The chart shows how to convert a number from base 10 to base 2
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Binary vs Offset Binary
Binary (Unipolar) Offset Binary (Bipolar)
1…111111111 + FS 1…111111111
- FS 0…000000000
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Offset Binary vs 2’s
Complement
OBIN 2SC
MSB
1111 0111
1110 0110
1101 0101
The basic difference between offset
1100 0100
binary (OBIN) and 2’s complement 1011 0011
(2SC) is the inversion of the most 1010 0010
significant bit (MSB) 1001 0001
1000 0000
0111 1111
0110 1110
To convert from one code to the other, a 0101 1101
logic inverter is used. 0100 1100
0011 1011
0010 1010
0001 1001
0000 1000
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Other Codes
(Not An All-Inclusive List)
Rarely used
Gray code :
Sign + magnitude
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What is an Analog-Digital
Converter?
Analog
Analog –– Digital
Digital
Converter
Converter
Analog Input
DIGITAL OUTPUT CODE = x (2n - 1)
Reference Input
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What is a Digital-Analog Converter?
Digital
Digital -- Analog
Analog
Converter
Converter
Digital Code
ANALOG OUTPUT VOLTAGE = VREF x -----------------
2N
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Quantization
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Why Do We Need A-D Converters?
Micro/DSP Processor
Multiplexer
Analog Analog to
Op Amp Signal Digital
Processing Converter
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Why Do We Need D-A Converters?
Micro/DSP Processor
Digital to Analog
Op Amp
Converter
The D-A converter translates its digital input signals from the
computer into an analog AC or DC signal that is used for
reference or control
Typical D-A output ranges include 2.5V, 5V and 10V full scale,
either unipolar or bipolar.
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Where Are D-A Converters Used?
D-A
D-A Operating
Operating
Converter
Converter System
System
D-A
D-A High
High Voltage
Voltage
Converter
Converter Power
Power Supply
Supply
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Where Are D-A Converters Used?
Reference
Input
Digital
Input D-A
D-A
Converter
Converter
Voltage Attenuator
Digital
ROM
ROM Input D-A
D-A
Look-Up
Look-Up Converter
Converter
Table
Table
Waveform Reconstruction
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DC Specifications
¾ Resolution
¾ Gain error
¾ Offset error
¾ Integral non-linearity
¾ Differential non-linearity
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What is Resolution?
1/4 1/2 3/4 1/8 1/2 3/4
1 1
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ADC and DAC Resolution
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How is the LSB Value Determined?
A data converter can neither measure nor generate a signal on its own.
A voltage reference is required.
Voltage
Voltage
Reference
Reference
A-D
A-D D-A
D-A
Converter
Converter Converter
Converter
Voltage Reference
The LSB value is equal to ; N = number of bits
2N
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Ideal Transfer Functions – 3 Bit ADC
111
110
001
000
•
3/4 •
•
In an ideal DAC, the
1/2 •
the output voltage is
• the exact incremental
value at each code
1/4 •
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Gain and Offset Error
ADC and DAC gain and offset errors are analogous to the gain and offset
errors of operational amplifiers. The offset error produces a lateral shift in
the transfer function while the gain error produces a rotational shift in the
transfer function. Both the offset error and gain error can be trimmed out.
Actual Actual
Ideal Ideal
Error Error
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Integral Non-Linearity
Also referred to as relative accuracy, it also is analogous to the non-
linearity of an op amp. The use of the “best straight line method” shows
less of an error, but it is not practical in real life.
Linearity Error, X
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Differential Non-Linearity
n n
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Missing Codes
111
110
101
100
Missing
011
Code
010
001
000
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Monotonicity
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Key AC Specifications for
A-D and D-A Converters
Settling Time √
Glitch Impulse √
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A Review of Quantization Noise
The input to an A-D converter is an analog voltage, and so has infinite resolution.
The output of the A-D converter, however is a digital representation of the input
that has been quantized or divided into 2N discrete steps. Any analog input above
or below the “nominal” input range as shown will yield the same digital code. This
is called the quantization uncertainty.
ADC Output
Code
NOMINAL
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A Review of Quantization Noise
(con’t)
As a result of this quantization uncertainty, a linear ramp voltage applied to an
ADC will produce a quantization noise which may be represented by a sawtooth
waveform coincident with the code transitions.
101
ADC Output Code
100
010
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A Review of Quantization Noise
(con’t)
The RMS value of the quantization noise sawtooth is its peak value q÷2
divided by √ 3, or q ÷ √12, where q = 1 LSB
+q/2
0 volts
-q/2
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A Review of Quantization Noise
(con’t)
HARMONICS OF FSIGNAL
(EXAGGERATED FOR CLARITY)
OUTPUT
RMS
QUANTIZATION NOISE
FSIGNAL FS/2 FS
If the quantization noise is uncorrelated with the frequency of the AC input signal,
The noise will be spread uniformly over the Nyquist bandwidth of fs/2.
If, however the input signal is locked to a sub-multiple of the sampling frequency,
The quantization noise will no longer appear uniform, but as harmonics of the
fundamental frequency
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Signal-to-Noise Ratio
SNRactual - 1.76dB
ENOB =
6.02dB
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Effective Number of Bits (ENOB)
The ENOB gives us a truer indication of the dynamic performance of the
ADC, because it takes into account the distortion and noise in the DC to
FS/2 ( Nyquist) bandwidth.
Since noise and distortion tend to increase with frequency, the effective
resolution of a 12-bit A-D converter may in fact be reduced to 11 or even
10 bits!
Effective Number of Bits
12 bit
(ENOB)
10 bit
Frequency
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Full Power Bandwidth
A-D
A-D D-A
D-A
Converter
Converter Converter
Converter
0 dB
-3 dB
FPBW
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Sampling Clock Jitter
ADC
Analog Input
Slope = dv/dt Nominal “Held” Output
“Hold”
“Track”
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Effect on SNR and ENOB due to
Sampling Clock Jitter, tj
1
SNR = 20log10
100 2πftj 16
tj = 1 ps
14
80
tj = 10 ps 12
10
60
tj = 100 ps
8
40
tj = 1 ns 6
4
20
0
1 3 10 30 100
Settling time is defined as the time it takes the DAC’s output to respond to a step
change in the digital input, and come within and remain within a defined error
band.
ERROR
BAND
TIME
DEAD SLEW
RECOVERY TIME FINAL SETTLING
TIME TIME
SETTLING TIME
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Glitch Impulse
voltage
time
a -37-
DAC Transitions Showing Glitch
The figure on the left shows the ideal DAC code transition. The center figure
shows a doublet glitch caused by capacitive coupling. This type of glitch cancels
out in the long term and can be present with or without a reference. The unipolar
glitch on the right is caused by switch timing differences…its amplitude is
proportional to the reference voltage
v v v
t t t
Transition with Transition with
Ideal Transition
Doublet Glitch Unipolar (Skew) Glitch
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AD768 - Glitch Impulse
-0.470
RL = 50Ω
-0.472 VOUT = 0 TO -1V
-0.474
-0.476
-0.478
-0.480
-0.482
TIME - 2 ns/div
SWITCH
Low Pass • +
BUFFER •
Filter -
“1”
HOLD CAPACITOR
“0”
LOW PHASE
JITTER
STABLE
CLOCK SOURCE
D/A
D/A CONVERTER
CONVERTER
DIRECT
DIRECT DIGITAL
DIGITAL FFT
FFT
LATCH
LATCH ON
ON
SYNTHESIZER
SYNTHESIZER ANALYZER
ANALYZER
EVALUATION
EVALUATION BOARD
BOARD
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Fast Fourier Transform (FFT)
Analyzer
f1 f1
amplitude
2f1
3f1
amplitude
2f1
3f1
time frequency
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A “Typical” FFT Output
0dB
-10dB
-20dB
-30dB
-40dB
2
-50dB
4
3 5 6
-60dB 7 8
-70dB
-80dB
Start 0 Hz FSAMPLE = 20 MHz, FIN = 1.1MHz Stop 10 MHz
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Harmonic Distortion (THD)
Harmonic distortion in both DACs and ADCs can come from a number of sources:
(1) non-linearities in the ADC or DAC architecture; (2) spurious signals due to the
quantization process, and (3) code-dependent glitches in the DAC output.
0dB
-10dB
-20dB
Harmonics
-30dB
-40dB
2
-50dB
4
-60dB 3 5 6
7 8
-70dB
-80dB
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Intermodulation Distortion (IMD)
F1 F2
SECOND
ORDER
THIRD
PRODUCTS
ORDER
PRODUCTS
F2 - F1 F1 + F2
2F1 - F2 2F2 - F1
FREQUENCY F
a -45-
FFT Output
2-Tone Intermodulation Test
A 1 dB change in the fundamental output level equals a 3dB change in
the 3rd order intermodulation component
0dB
-10dB
-20dB
-30dB
-40dB
-50dB
-60dB
-70dB
-80dB
Start 0 Hz FSAMPLE = 20 MHz, FIN = 4.5MHz and 5.5 MHz Stop 10 MHz
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Spurious-Free Dynamic Range
(SFDR)
Spurious-free dynamic range (SFDR) is the distance, in dB, from the fundamental
level to the first “spur”. In the FFT image below, the SFDR is approximately -51 dB
due to the 2nd harmonic
0dB
-10dB
-20dB
SFDR
-30dB
-40dB
2
-50dB
4
-60dB 3 5 6
7 8
-70dB
-80dB
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Summary
Analog-digital and digital-analog converters communicate with
the host processor using a binary code system.
Key DC specifications for the A/D and D/A converter include, -
Resolution
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Want To Learn More?
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