Practical 1

Practical 1: Study and verify the truth table of various logic gates (NOT, AND, OR, NAND,
NOR, EX-OR, and EX-NOR).

Truth Table for NOT

A A’

0 1

1 0

Truth Table for AND

A B A.B

0 0 0

0 1 0

1 0 0

1 1 1

Truth Table for OR

A B A+B

0 0 0

0 1 1

1 0 1

1 1 1
Truth Table for NAND

A B A.B (A.B)’

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

Truth Table for NOR

A B A+B (A+B)’

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

Truth Table for EX-OR

A B A⊕B

0 0 0

0 1 1

1 0 1

1 1 0
 Practical 1

Truth Table for EX-NOR

A B A⊕B (A⊕B)’

0 0 0 1

0 1 1 0

1 0 1 0

1 1 0 1

Truth Table for BUFFER

A A

0 0

1 1
 Practical 2

Practical 2: Simplify given Boolean expression and realize it.

1) (A + B).(B + C) = A.B + A.C + B.B + B.C (Distributive Law)
=A.B + A.C + B + B.C (Since, B.B=B Idempotence)
=B(A + C + 1) + A.C (Distributive Law)
=B(1) + A.C (Since, A + 1=1 Null Elements)
=B + A.C (Since, B.1=B Identity)

A B C B+A.C
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

2) (A.B + C) D

A B C D (A.B+C)D
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
 Practical 2

3)A’.B + (B + C)’

A B C A’.B+(B+C)’
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

4)(A.B)’ + (C.D)’= ((A.B).(C.D))’ (Since, A’ + B’=(A.B)’ DeMorgan’s Rule)

=(A.B.C.D)’ (Distribution)

A B C D (A.B.C.D)’
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
 Practical 2

5)(B.C)’+ (A.B + C’)’ = B’ + C’ + (A.B)’ . C’’ (Since, (A.B)’=A’ + B’ and (A + B)’=A’.B’

. DeMorgan’s Rule)
= B’ + C’ + (A’ + B’) . C (Since, (A.B)’=A’ + B’ DeMorgan’s Rule
. and C’’=C Involution)
= B’ + C’ + A’.C + B’.C (Distributive Law)
=B’(1 + C) + C’ + A’.C (Distributive Law)
=B’(1) + C’ + A’.C (Since, A + 1=1 Null Elements)
=B’ + C’ + A’ (Since, A’ + A.B’=A’ + B’ Simplification)
=A’+B’+C’ (Commutative Law)

A B C A’+B’+C’
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

6) A’(B XOR C)

A B C A’(B XOR C)
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

7) A’.B’.C + A’.B + A.B’ + A.B.C = A’(B’.C + B) + A.B’ + A.B.C (Distributive Law)

=A’(B + C) + A.B’ + A.B.C (Since, A’.B + A= B + A Absorption)
=A’(B + C) + A(B’ + B.C) (Distributive Law)
= A’(B + C) + A(B’ + C) (Since, A.B + A’= B + A’ Absorption)
=A’.B + A’.C + A.B’ +A.C (Distribution)
=A’.B + A.B’ + A’.C + A.C (Commutative Law)
= A’.B + A.B’ + C(A’ + A) (Distributive Law)
= A’.B + A.B’ + C(1) (Since, A + A’=1 Complement)
= A’.B + A.B’ + C
 Practical 2

A B C A’.B+A.B’+C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1

8) A’ (A+BC)+(AC+ B’C)= A’.A+A’.B.C+A.C+B’.C (Distributive Law)

=0+A’.B.C+A.C+B’.C (Since, A.A’ = 0 Complement)
=A’.B.C + A.C + B’.C (Since, A + 0=A Identity)
=C(A’.B + A) + B’.C (Distributive Law)
=C(B + A) + B’.C (Since, A’.B + A= B + A Simplification)
=C.B + C.A + B’.C (Distribution)
=C(B + B’) + C.A (Distributive Law)
=C(1) + C.A (Since, A + A’ = 0 Complement)
=C + C.A (Since, A.1=A Identity)
=C (Since, A + A.B= A Absorption)

C C

0 0

1 1

9)X.Z’ + (Y + Y’.Z) + X.Y = X.Z’ +Y + Z +X.Y (Since, A + A’.B= A + B Simplification)

=(X.Y + Y) + Z +X.Z’ (Commutative Law)
=Y+( Z + X.Z’) (Since, A + A.B= A Absorption)
=Y + Z + X (Since, A + A’.B= A + B Simplification)
 Practical 2

X Y Z Y+Z+X
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

10)Y’(X’ + Y’) (X + X’.Y) = (Y’.X + Y’.Y’) (X + X’.Y) (Distributive Law)

= (Y’.X + Y’) (X + X’.Y) (Since, A.A=A Idempotence)
=Y’.X.X + Y’.X + Y’.X.X’.Y + Y’.X’.Y (Distributive Law)
=Y’.X + Y’.X + 0 + X’(0) (Since, A.A=A Idempotence
.. and A.A’=0 Complement )
=Y’.X (Since, A + A=A Idempotence)
=X.Y’ (Commutative Law)

X Y X.Y’

0 0 0

0 1 0

1 0 1

1 1 0
 Practical 3

Practical 3:Design and verify a half/full adder.

Half Adder

A B Sum Carry
A⊕B A.B

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Full Adder

A B C Sum Carry
A⊕B⊕C A.B+B.C+A.C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Practical 4

Practical 4: Design and verify half/full subtractor.

Half Subtractor

A B Difference Borrow
A⊕B A’.B
0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Full Subtractor

A B Bin Difference Bout

A⊕B⊕Bin BBin+A’B+A’Bin

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
 Practical 5

Practical 5: Design a 2 bit magnitude comparator using combinational circuits.

A1 A0 B1 B0 A<B A=B A>B

0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0

A<B
Practical 5

A=B

A>B
 Practical 6

Practical 6: Design and verify the operation of flip-flops using logic gates.
SR Flip Flop
S R Q Q’

0 0 Q prev Q’prev

0 1 0 1

1 0 1 0

1 1 Prohibited entry

CLOCKED SR Flip Flop

CLOCK S R Q Q’

0 X X Q prev Q’prev

1 0 0 Q prev Q’prev

1 0 1 0 1

1 1 0 1 0

1 1 1 Prohibited entry
 Practical 6

JK Flip Flop
CLOCK J K Q Q’ S R Q Q’
(Previous) (Previous) (J.Q’) (K.Q) (Present) (Present)

0 X X X X X X Q prev Q’prev
1 0 0 1 0 0 0 1 0
0 1 0 0 0 1
1 0 1 1 0 0 1 0 1
0 1 0 0 0 1
1 1 0 1 0 0 0 1 0
0 1 1 0 1 0
1 1 1 1 0 0 1 0 1
0 1 1 0 1 0

D Type Flip Flop

D J K Q Q’

0 0 1 0 1

1 1 0 1 0
 Practical 6

T Type Flip Flop

T J K Q Q’

0 0 0 Q prev Q’ prev

1 1 1 Q’ prev Q’’ prev

 Practical 7

Practical 7: Verify the operation of a counter(Asynchronous UP Counter).

3 bit Ripple up Counter

CLOCK Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
Practical 7
Practical 7
Practical 7
 Practical 7

Timing Diagram
 Practical 8

Practical 8: Verify the operation of a 4 bit shift register

1101

CLOCK D3 D2 D1 D0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 0 0
1 1 0 0 0 1 0 0 0
2 0 1 0 0 0 1 0 0
3 1 0 1 0 1 0 1 0
4 1 1 0 1 1 1 0 1
5 0 1 1 0 0 1 1 0
6 0 0 1 1 0 0 1 1
7 0 0 0 1 0 0 0 1
Practical 8