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2020 Ques End Advd

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42 views2 pages

2020 Ques End Advd

Uploaded by

SABUJ CHAKI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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End Semester Advanced VLSI Design 10:00 - 12:00 Sun 29 Nov 2020

Throughout the examination your google meet audio & video will remain switched on and your smart phones must remain
switched off for the entire duration. No one should enter the room where you are writing your examination, which should
be written within closed doors and in complete isolation and privacy. After completion of the examination you must switch
on your smart phone/tablet and take the pictures of your answer script (serially as the pages) infront of your google meet
camera and share those pictures at 9733420124. You must write your exam infront of google meet camera throughout your
exam, your camera getting disconnected, or if you are leaving the camera focus, or I cannot see you during the exam, for
whatever reason, cancels your paper. Write your name, institute ID# and whatsapp# legibly on the top margin of the
first page of your answer sheets. Put page numbers sequentially at the bottom of all the pages of your answer scripts. Take
photographs of all the pages of your answers scripts and send all the photos as whatsapp to 9733420124. All symbols used
in these questions denote their usual parameters. Correct answers without the relevant derivations and rough work will be
considered as resorting to unfair means and will result in cancellation of the entire paper.
1. Use the following timing parameters for the parts in this question.

Setup time Clock-to-Q delay D-to-Q delay Contamination delay Hold time
Flip-flops 65 ps 50 ps n/a 35 ps 30 ps
Latches 25 ps 50 ps 40 ps 35 ps 30 ps
Table for Question 1: Sequencing element parameters

(a) For each of the following sequencing styles, determine the maximum logic propagation delay available within a
500 ps clock cycle. Assume there is zero clock skew and no time borrowing takes place.
i. Flip-flops [2]
ii. Two-phase transparent latches [2]
iii. Pulsed latches with 80 ps pulse width [2]
(b) For each of the following sequencing styles, determine the maximum logic propagation delay available within a
500 ps clock cycle. If the clock skew between any two elements can be up to 50 ps.
i. Flip-flops [2]
ii. Two-phase transparent latches [2]
iii. Pulsed latches with 80 ps pulse width [2]
(c) For each of the following sequencing styles, determine the minimum logic propagation delay available within a
500 ps clock cycle. If the clock skew between any two elements can be up to 50 ps.
i. Flip-flops [2]
ii. Two-phase transparent latches with 50% duty cycle clocks [2]
iii. Two-phase transparent latches with 60 ps of nonoverlap between phases [2]
iv. Pulsed latches with 80 ps pulse width [2]

2. (a) Give the expression for the Vout for the pass transistor networks shown in the adjoining figure. Neglect the
body effect. [2×4=8]
(b) Suppose Vdd = 1.2 V and Vtn = 0.4 V, ignoring the body effect, determine the Vout in a single pass transistor
i. Vin = 0 V [2]

Figures for Question 2a

80 Marks MEL G623 Page 1 of 2


End Semester Advanced VLSI Design 10:00 - 12:00 Sun 29 Nov 2020

ii. Vin = 0.6 V [2]


iii. Vin = 0.9 V [2]
iv. Vin = 1.2 V [2]
3. In the static CMOS inverter transfer characteristics, assuming |Vtp | =
6 Vtn and βp 6= βn ,

(a) Solve for the value of Vin for the region where both the transistors are saturated. [6]
(b) Derive analytic expressions for Vout as a function of Vin for those regions where one of the transistors is in
saturation and the other in linear. [6]
4. Derive Vout for the pseudo-nMOS inverter as a function of the threshold voltages and beta values of the two tran-
sistors, with Vin = Vdd . Assume Vout < |Vtp |. [6]
5. (a) Find the rising and falling propagation delays of an AND-OR-INVERT gate using the Elmore delay model.
[2+2=4]
(b) Find the worst-case Elmore parasitic delay of an n-input NOR gate. [4]
(c) If the pMOS transistors have µ times the effective resistance of nMOS transistors, find a general expression for
the logical efforts of a κ-input NAND gate and a κ-input NOR gate. As µ increases, comment on the relative
desirability of NANDs vs. NORs and why? [2+2+1=5]
6. Suppose that the precharge transistor in the adjoining figure was chosen such that the node X is guaranteed to be
charged to Vdd . All nMOS transistors have W/L = 20. Determine how long it takes for the node voltage at X to
decrease to 0.8Vdd after the clock signal pulse goes high (with zero rise time) when the input voltages at A, B, D
are 5 V and the input voltage at C is 0 V. Assume γ = 0 V0.5 , VT 0 = 1 V, kn0 = 10 µA/V2 . [7]
7. Determine the ratio between device transconductance parameters kp and kn of the inverter show in the adjoining
figure to prevent any kind of logic error due to the charge sharing issues in the domino circuit shown between nodes
X and Y under all possible circumstances. Assume that the threshold voltages in the inverter are equal to 1 V. [6]

Figure for Question 6 Figure for Question 7

80 Marks MEL G623 Page 2 of 2

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