www. Micro Digital Ed.

com
BIHE university

MCU memory map, memory mapped IO

Electronics Department, HCMUT 1

 Topics
www. Micro Digital Ed. com
BIHE university

• STM32 Memory map

• Memory mapped IO
• CMSIS Core Library
• STM32 Embedded Software Libraries

Electronics Department, HCMUT 2

 MCU Block Diagram
www. Micro Digital Ed. com
BIHE university

Electronics Department, HCMUT 3

 Memory map
www. Micro Digital Ed. com
BIHE university

Electronics Department, HCMUT 4

 Memory mapped IO
www. Micro Digital Ed. com
BIHE university

If base address is 0xA0004000,

what is the address of Reg5?

Write a C instruction to write

0x12345678 to Reg 5.
Reg0
Reg1
Reg2
Reg3
Reg4
Reg5

Electronics Department, HCMUT 5

 CMSIS IO Registers Access
www. Micro Digital Ed. com
BIHE university

Electronics Department, HCMUT 6

 Driver Libraries
www. Micro Digital Ed. com
BIHE university

• CMSIS
• Cortex Microcontroller Software Interface Standard
• Support for creating reusable software components
for ARM Cortex-M based systems
• Low level (LL)
• Hardware Abstraction Layer (HAL)

Electronics Department, HCMUT 7

 CMSIS Library
•
www. Micro Digital Ed. com
BIHE university

Electronics Department, HCMUT 8

 CMSIS Core
www. Micro Digital Ed. com
BIHE university

• CMSIS-Core (Cortex-M): define user access to the

processor core and the device peripherals
– Hardware Abstraction Layer (HAL): interface SysTick, NVIC,
System Control Block registers, MPU registers, FPU registers,
and core access functions.
– System exception names: interface to system exceptions
– Methods to organize header files that makes it easy to learn
new Cortex-M microcontroller products and improve software
portability.
– Methods for system initialization to be used by each MCU
vendor, e.g. SystemInit() function.
– Intrinsic functions used to generate CPU instructions that are
not supported by standard C functions.
– A variable to determine the system clock frequency.
Reference: https://www.keil.com/pack/doc/CMSIS/Core/html/using_CMSIS.html
Electronics Department, HCMUT 9
 CMSIS Core files
File/Folder Content
www. Micro Digital Ed. com
BIHE university

CMSIS\Documentati
This documentation
on\Core
CMSIS-Core (Cortex-M) header files (for
CMSIS\Core\Include
example core_cm3.h, core_cmInstr.h, etc.)
Arm reference implementations of Cortex-M
Device
devices
Device\_Template_V CMSIS-Core Device Templates for extension
endor by silicon vendors

Electronics Department, HCMUT 10

 STM32 Embedded Software Offer
www. Micro Digital Ed. com
BIHE university

Electronics Department, HCMUT 11

 STM32Snippets
www. Micro Digital Ed. com
BIHE university

What is it ?
A collection of code examples, directly based on STM32 peripheral
registers, available in documentation and as softtware bundles
Targe Audience
Low level embedded system developers, typically coming from an 8 bit
background, used to assembly or C with little abstraction

Features: Limitations:
o Highly Optimized o Specific to STM32 devices, not portable directly
o Register Level Access between series
o Small code expressions o Not matching complex peripherals such as USB
o Closely follows the o Lack of abstraction means developers must
reference manual understand peripheral operation at register level
o Debugging close to o Available (today) on STM32 L0 and F0 series
register level

Electronics Department, HCMUT 12

 Standard Peripheral Libraries
www. Micro Digital Ed. com
BIHE university

What is it ?
Collection of C Libraries covering STM32 peripherals

Targe Audience
Embedded systems developers with procedural C background. All existing STM32
customer base prior to the STM32Cube launch, willing to keep same supporting
technology for future projects, and same STM32 series

Features: Limitations:
o Average optimization, fitting lots of o Specific to certain STM32 series.
situations o No common HAL API prevents
o No need for direct register application portability between series
manipulation o Middleware libraries may not be unified
o 100% coverage of all peripherals for each series
o Easier debugging of procedural code o Doesn’t support forward STM32 series
o Extensions for complex middleware starting with STM32 L0, L4 and F7
such as
o USB/TCP-IP/Graphics/Touch Sense
Electronics Department, HCMUT 13
 STM32Cube
www. Micro Digital Ed. com
BIHE university

What is it ?
o Full featured packages with drivers, USB, TCP/IP,
Graphics, File system and RTOS
o Set of common application programming interfaces,
ensuring high portability inside whole STM32 family
o Set of APIs directly based on STM32 peripheral
registers
o Set of initialization APIs functionally similar to the SPL
block peripheral initialization functions

What is it ?
o Hardware Abstraction Layer (HAL) APIs: embedded system developers with a
strong structured background. New customers looking for a fast way to evaluate
STM32 and easy portability
o Low-Layer (LL) APIs: low level embedded system developers, typically coming
from an 8-bit background, used to assembly or C with little abstraction. Stronger
focus on customers migrating from the SPL environment .

Electronics Department, HCMUT 14

 HAL
www. Micro Digital Ed. com
BIHE university

Features:
o High level and functional abstraction
o Easy port from one series to another
o 100% coverage of all peripherals
o Integrates complex middleware such as USB/TCP-IP/Graphics/Touch
Sense/RTOS
o Can work with STM32CubeMX to generate initialization code

Limitations:
o May be challenging to low level C programmers in the embedded
space.
o Higher portability creates bigger software footprints or more time spent
executing adaptation code

Electronics Department, HCMUT 15

 LL
www. Micro Digital Ed. com
BIHE university

Features:
o Highly Optimized o Peripheral block initialization APIs
✓ Initialization, de-initialization and
o Register Level Access default initialization routines SPL-Like
o Small code expressions functionally speaking
o Closely follows the reference manual ✓ More optimized than SPL, fitting lots
o Debugging close to register level of situations
✓ No need for direct register
o Can work with STM32CubeMX to generate manipulation
o Initialization code for STM32L0/F0/F3/L4 ✓ Easier debugging of procedural code

Limitations:
o Specific to STM32 devices, not portable directly between series
o Not matching complex peripherals such as USB
o Lack of abstraction for runtime means developers must understand peripheral
operation at register level
o Peripheral block initialization APIs have the same limitations as the SPLs (except
availability considerations)

Electronics Department, HCMUT 16

 Possible concurrent usage of HAL and LL
www. Micro Digital Ed. com
BIHE university

Limitation:
o LL cannot be used with HAL for the
same peripheral instance.
Impossible to run concurrent
processes on the same IP using
both APIs, but sequential use is
allowed

Example of hybrid model:

o Simpler static peripheral initialization
with HAL
o Optimized runtime peripheral
handling with LL calls

Electronics Department, HCMUT 17

 ST software packages
www. Micro Digital Ed. com
BIHE university

Electronics Department, HCMUT 18

 LL library - introduction
www. Micro Digital Ed. com
BIHE university

• Stm32yyxx_ll_ppp.h:
– Unitary functions for direct
register access
• Stm32yyxx_ll_ppp.h:
– Init functions
– Conceptual compatible with
SPL libraries

Electronics Department, HCMUT 19

 Role of some LL header file
www. Micro Digital Ed. com
BIHE university

o Most of ppp peripherals have their own pairs of stm32xxxx_ll_ppp.c and .h files

.h file Serviced peripheral

stm32xxxx_ll_bus.h APB1, APB2, IOP, AHB registers

SYSTICK registers•
Low power mode configuration (SCB register of Cortex-MCU)
stm32xxxx_ll_cortex.h
MPU API
API to access to MCU info (CPUID register)
Some of the FLASH features (accelerator, latency, power down modes)
stm32xxxx_ll_system.h DBGCMU registers
SYSCFG registers (including remap and EXTI)
Device electronic signature
stm32xxxx_ll_utils.h Timing functions
PLL configuration functions

Electronics Department, HCMUT 20

 LL functions
www. Micro Digital Ed. com
BIHE university

Electronics Department, HCMUT 21

 LL_functions
www. Micro Digital Ed. com

• Low level: Basic register read and write BIHE university

• Middle level: one-shot operation API with some processing

• High level: global configuration and initialization functions that

cover full standalone operations on related peripheral registers

Electronics Department, HCMUT 22

 Hardware abstraction layer (HAL)
www. Micro Digital Ed. com
BIHE university

• Set of APIs and to interact easily with the application upper

layers
• Cross-family portable set of APIs
• Three API programming models: polling, interrupt and DMA
• All HAL APIs implement user-callback functions
mechanism:
• Peripheral Init/DeInit HAL APIs can call user-callback functions to
perform peripheral system level Initialization/De-Initialization (clock,
GPIOs, interrupt, DMA)
• Peripherals interrupt events
• Error events.

Electronics Department, HCMUT 23

 HAL Project struture
www. Micro Digital Ed. com
BIHE university

Electronics Department, HCMUT 24

 HAL features
www. Micro Digital Ed. com
BIHE university

• High level of abstraction

• API to perform complete procedure, e.g. ADC
conversion
• Handle register access internally
• Use variable to hold the state of procedure,
buffers

Electronics Department, HCMUT 25

 Choose drivers for implementation
www. Micro Digital Ed. com
BIHE university

• Use CMSIS for the core hardware, e.g. NVIC

• Use LL for register level programming of
peripherals
• HAL can be used with care:
– Make sure you understand the mechanism under the
hood, e.g. interrupt handling, error handling, timing, etc
Opinion:
o Consider using LL libraries
o Provide the hardware abstraction at application / protocol
stack module

Electronics Department, HCMUT 26