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The document discusses three tutorials related to memory hierarchy systems and cache memory optimization. Tutorial 1 calculates average access times and costs for three cache designs with different capacities. Tutorial 2 finds the minimum hit rate needed for a cache after optimization to not increase average access time. Tutorial 3 calculates effective access times for a system with and without an additional on-chip cache.

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20 views2 pages

Tutorials-2 Embedded

The document discusses three tutorials related to memory hierarchy systems and cache memory optimization. Tutorial 1 calculates average access times and costs for three cache designs with different capacities. Tutorial 2 finds the minimum hit rate needed for a cache after optimization to not increase average access time. Tutorial 3 calculates effective access times for a system with and without an additional on-chip cache.

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shreyasmi.ec21
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UNIT 2

TUTORIAL 1: Perform capacity planning for a two level memory hierarchy system.
The first level, M1 is a cache with three capacity choices 64 Kbytes, 128 Kbytes and
256 Kbytes. The second level, M2 is a main memory with a 4 Mbyte capacity. Let C1
and C2 be the cost per byte and t1 and t2 the access times for M1 and M2
respectively. Assume C1 =20C2 and t2 =10t1. The cache hit ratios for the three
capacities are assumed to be 0.7, 0.9 and 0.98 respectively.
i) What is the average access time ta in terms of t1=20ns in the three cache designs?
ii) Express the average byte cost of the entire memory hierarchy if C2=$0.2/Kbyte.
iii) Compare the three memory designs and indicate the order of merit in terms of
average costs and average access times respectively. Choose the optimal design
based on the product of average cost & average access times.

Solution
i) The average access time ta in terms of t1=20ns in the three cache designs can be
calculated as follows:

For M1 with 64 Kbytes capacity:


Access time = t1 + (1 - hit ratio) * t2
Access time = 20ns + (1 - 0.7) * 200ns
Access time = 80ns
For M1 with 128 Kbytes capacity:
Access time = t1 + (1 - hit ratio) * t2
Access time = 20ns + (1 - 0.9) * 200ns
Access time = 38ns
For M1 with 256 Kbytes capacity:
Access time = t1 + (1 - hit ratio) * t2
Access time = 20ns + (1 - 0.98) * 200ns
Access time = 24ns
Therefore, the average access times for the three cache designs are 80ns, 38ns, and
24ns respectively.

ii) The average byte cost of the entire memory hierarchy can be calculated as follows:

Cost of M1 in 64K= C1 * (64K)


= 20C2 * (64K)= 20 ($0.2/Kbyte)*64 K= $256 / Kbyte
Cost of M1 in 128K= C1 * (128K)
= 20C2 * (128K)= $512 /Kbyte
Cost of M1 in 256K= C1 * (256K)
= 20C2 * (256K)= $1024/Kbyte

Cost of M2 = C2 * 4M = $0.2/Kbyte * 4M = $800/Kbyte


Total cost in 64K= Cost of M1 + Cost of M2 = $256 + $800= $1056/Kbyte
Total cost in 128K= Cost of M1 + Cost of M2 = $512 +$800= $1312/Kbyte
Total cost in 256K= Cost of M1 + Cost of M2 = $1024+$800= $1824/Kbyte

The average byte cost of the entire memory hierarchy is $/byte.

iii) The order of merit in terms of average costs and average access times respectively
is as follows:

M1 with 256 Kbytes capacity: Average access time = 24ns, Average cost =
M1 with 128 Kbytes capacity: Average access time = 38ns, Average cost =
M1 with 64 Kbytes capacity: Average access time = 80ns, Average cost =
Therefore, the optimal design is M1 with 256 Kbytes capacity as it has the lowest
product of average cost and average access time.

TUTORIAL 2: A cache memory that has a hit rate of 0.8 has an access
latency 10 ns and miss penalty 100 ns. An optimization is done on the
cache to reduce the miss rate. However, the optimization results in an
increase of cache access latency to 15 ns, whereas the miss penalty is not
affected. The minimum hit rate (rounded off to two decimal places) needed
after the optimization such that it should not increase the average memory
access time is _____________.
Solution:
Average Memory Access Time (AMAT):

The "absolute hit rate" is the percentage of all memory accesses that hit in
this cache level. The "relative hit rate" is the percentage of memory accesses
that failed at all previous levels but succeeded at this one.
The given data,
Cache memory hit rate Hc = 0.8 Access Latency Tc = 10 ns.
Miss penalty = 100 ns.
Optimization increases cache access latency to 15 ns. Miss penalty is not
affected.
Memory with optimization Tc = 15 ns
Average memory access time Tavg = Tc+ (1-Hc) miss penalty
Average memory access time in first case ,
Average memory access time Tavg = (10)+(1-0.8) 100= 30 ns

Cache memory hit rate = ?


Tavg = 30 ns
Average memory access time in the second case,
Tavg = (Tc) + (1-Hc) miss penalty
30 = (15) + (1-Hc) 100 ns
Hc = 85/100
x = 0.85 minimum hit rate (rounded off to two decimal places).

TUTORIAL 3:
A computer has a single cache (off-chip) with a 2 ns hit time and a 98% hit
rate. Main memory has a 40 ns access time. What is the computer’s
effectiveaccess time? If we add an on-chip cache with a 5 ns hit time and a
94% hit rate, what is the computer’s effective access time? How much of a
speedup does the on-chip cache give the computer?

Solution:
2 ns + 0.02 * 40 ns = 2.8 ns.
With the on-chip cache,
we have 5 ns + 0.06 * (2 ns + 0.02 * 40 ns) = 668 ns.
The speedup is 2.8 /668

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