STATIC AND DYNAMIC PERFORMANCE LIMITATIONS

FOR HIGH SPEED D/A CONVERTERS

 THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND
COMPUTER SCIENCE

ANALOG CIRCUITS AND SIGNAL PROCESSING

Consulting Editor: Mohammed Ismail. Ohio State University
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 STATIC AND DYNAMIC
PERFORMANCE LIMITATIONS
FOR HIGH SPEED
D/A CONVERTERS

by

Anne Van den Bosch

K. U. Leuven, Belgium

Michiel Steyaert
K. U. Leuven, Belgium

and

Willy Sansen
K.u. Leuven, Belgium

SPRINGER SCIENCE+BUSINESS MEDIA, LLC

A c.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN 978-1-4419-5434-3 ISBN 978-1-4757-6579-3 (eBook)

DOI 10.1007/978-1-4757-6579-3

Printed on acid-free paper

All Rights Reserved

© 2004 Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers, Boston in 2004
No part of this work may be reproduced, stored in a retrieval system, or transmitted
in any form or by any means, electronic, mechanical, photocopying, microfilming, recording
or otherwise, without written permission from the Publisher, with the exception
of any material supplied specifically for the purpose of being entered
and executed on a computer system, for exclusive use by the purchaser of the work.
Abstract

Although the digital world gains in importance due to the decreasing feature size of the
transistors, the analog building blocks remain indispensable. The design of the inter-
face between the two worlds has to comply with the strict requirements of both sides.
The presented research focusses on the design of current steering DIA converters in
the modem telecommunication systems of tomorrow.
An accurate description of both the static and the dynamic behaviour is of the
utmost importance when designing a current steering D/A converter with a high per-
formance. A new formula has been derived that accurately describes the INL-yield of
a D/A converter as a function of the transistor mismatch behaviour in a given technol-
ogy. The influence of systematic errors introduced by linear and quadratic gradients
has to be minimised by the use of special switching schemes. Based on these elements,
two 12 bit and one 14 bit current steering D/A converter have been implemented.
Apart from the three well known factors influencing the dynamic behaviour of
the DI A converter, a fourth element has been introduced. The frequency dependency
of the output impedance has a negative effect on high resolution, high speed current
steering DIA converters. Taking this new element into account during the design re-
sulted in the realisation of a 10 bit D/A converter with a Nyquist performance in the
entire frequency band for a clock frequency up to 1 GS/s.
To determine the optimal segmentation level of a current steering DIA converter, a
statistical analysis has been performed. It could be concluded that if the requirement
dictated by the transistor mismatch of the unit current sources is fulfilled , both the INL
and the DNL error are smaller than 112 LSB regardless of the number of bits imple-
mented in a binary way. A low segmentation level implies a low decoder complexity
and as such leads to a small power and area consumption. Based on these findings , a
fully binary 10 bit D/A converter has been realised with a small power consumption
and a good dynamic performance.

The second part of this work is focussed on transistor mismatch. An overview is

given of the most important mismatch models and on the influence of both the imme-
diate surroundings and the used transistor topology. Also the link between the static
performance of a current steering D/A converter and the extraction of the transistor
vi

mismatch parameters has been investigated. It is suggested that a current steering D/A
converter could act as a test structure for matching characterisation.
Contents

Abstract v

Contents vii

List of Symbols and Abbreviations xv

1 Introduction 1
1.1 Introduction........ . . 1
1.2 Outline of the Research Work. 2

2 The DfA Converter: Functionality and Specifications 7

2.1 Introduction......... .. .. 7
2.2 The Basic OfA Converter Function . . . . . 7
2.2.1 Analog and Digital Signals . . . . . 7
2.2.2 The OfA Converter as a Black Box. 9
2.3 The Characteristics of an Ideal OfA Converter . 10
2.3.1 Introduction . . . . . . . . . . . . . . . 10
2.3.2 The Quantisation Error .. . . . . . . . 10
2.3.3 The Sample and Hold like Amplitude Distortion 12
2.4 The Performance Specifications of a D/A Converter. 13
2.4.1 Introduction.... . .. 13
2.4.2 The Static Specifications . . . . . . . . . . . 13
2.4.2.1 Introduction... .. . . . . . . . 13
2.4.2.2 The Offset Error and the Gain Error. 14
2.4.2.3 The Differential Non-Linearity Error (DNL) 14
2.4.2.4 The Integral Non-Linearity Error (INL) . 14
2.4.2.5 Monotonicity .. 15
2.4.3 The Dynamic Specifications 17
2.4.3.1 Introduction . . . 17
2.4.3.2 The Update Rate. 18
2.4.3.3 The Settling Time 18
2.4.3.4 The Glitch Energy 18
viii CONTENTS

2.4.3.5 The Slew Rate . . . . . . . . . . 19

2.4.3.6 The Clock-Feedthrough . . . . . 20
2.4.3.7 The Signal to Noise Ratio (SNR) 20
2.4.3.8 The Signal to Noise and Distortion Ratio (SNDR) 20
2.4.3.9 The Spurious Free Dynamic Range (SFDR) . 20
2.4.3.10 The Total Harmonic Distortion (THD) . . . . 21
2.5 The D/A converter specifications as a function of the application 22
2.6 Conclusions . . . . . . . . . . . . 22

3 CMOS D/A Converter Architectures 23

3.1 Introduction . . . . . . . . . . . . 23
3.2 The Resistor D/A Converter .. . 23
3.2.1 The resistor string DIA converter. 23
3.2.2 The binary weighted resistor DIA converter 25
3.2.3 The R-2R based D/A converters 25
3.3 The Capacitor D/A Converter . . . . . 26
3.4 The Current-Steering D/A Converter. 29
3.4.1 Introduction . . . . . . . . . 29
3.4.2 The Binary Implementation . 29
3.4.3 The Unary Implementation .. 29
3.4.4 The Segmented Implementation 30
3.5 Conclusions . . . . . . . . . . . . . . . 30

4 Static Behaviour of Current Steering DIA converters 33

4.1 Introduction........... 33
4.2 Modelling of the random errors . . 33
4.2.1 Introduction........ 33
4.2.2 Lakshmikumar Approach. 34
4.2.3 Monte Carlo Approach . . 35
4.2.4 A new INLyield Formula 36
4.2.4.1 Introduction 36
4.2.4.2 Theory..... 36
4.2.5 Conclusion........ 41
4.3 Modelling of the systematic errors 42
4.3.1 Possible causes . . . . 42
4.3.2 Switching Schemes . . . . 43
4.3.2.1 Introduction .. 43
4.3.2.2 The Gradient Error Distribution . 43
4.3.2.3 The sequential, conventional and hierarchical sym-
metrical switching schemes . . . . . . . . . ... . 44
CONTENTS ix

4.3.2.4Switching Schemes for the 2-D Rowand Column

Decoding Principle . . . . . . . . . . . . . . . . . 47
4.3.2.5 Decoder Independent 2-D Centroid Switching Schemes 48
4.3.2.6 The Analytical Optimisation of a Switching Scheme 49
4.4 Conclusion .. 51

S Dynamic Behaviour of Current Steering DIA Converters S3

5.1 Introduction............................... 53
5.2 Major contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2.1 The Imperfect Synchronisation of the Control Signals of the
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2.2 The Digital Signal Feedthrough via the CCD of the Switch
Transistors . . . . . . . . . . . . . . . . . . . .. . . . 55 . . .
5.2.3 The Voltage Variation at the Drain of the Current Source Tran-
sistors . . . . . . . . . 55
5.2.4 The Output Impedance . . . . . . . . . 56
5.3 SFDR-Bandwidth limitations . . . . . . . . . . 58
5.4 SFDR-Bandwidth Optimised Implementations. 60
5.4.1 The Cascoded Current Source Transistor 61
5.4.1.1 The analysis of the zeroes of the impedance Zimp 62
5.4.1.2 The analysis of the poles of the impedance Zimp 62
5.4.1.3 A numerical example . . . . . . . . 63
5.4.1.4 Fault analysis of the presented theory 67
5.4.1.5 Conclusion . . . . . . . . . . . . . . 68
5.4.2 The Cascoded Switch Transistor . . . . . . . . 68
5.4.2.1 The analysis of the zeroes of the impedance Zimp 69
5.4.2.2 The analysis of the poles of the impedance Zimp 70
5.4.2.3 A numerical example . . . . . . . . . 70
5.4.2.4 Fault analysis of the presented theory . 71
5.4.2.5 Conclusion . . . . . . . . . . . . . . . 71
5.4.3 The Double Cascoded Current Source Transistor 72
5.4.3.1 The analysis of the zeroes of the impedance Zimp 73
5.4.3.2 The analysis of the poles of the impedance Zimp 73
5.4.3.3 A numerical example 75
5.5 Conclusion .. 76

6 A Design Methodology for High Performance CMOS Current Steering

DIA Converters 77
6.1 Introduction............................... 77
6.2 Determining the level of segmentation in a current steering D/A con-
verter . . . . . . . . . . . . . . . . . . . . . . . . .... . 77
. . . . .
x CONTENTS

6.2.1 The area approach . . . . . 77

6.2.2 The mathematical approach 78
6.2.3 Conclusion..... . . . . 84
6.3 Architectural choice of the thermometer decoder 84
6.4 Design of the synchronised switch driver. 85
6.5 Dimensioning the unit current cell . . 85
6.5.1 The current source transistor .. . 85
6.5.1.1 The area constraint .. 85
6.5.1.2 The output voltage swing 87
6.5.2 The switch and cascode transistor 87
6.6 Conclusion 88

7 Realisations 89
7.1 Introduction................... 89
7.2 High Accuracy DIA Converters. . . . . . . . . 90
7.2.1 First Design of a 12 bit D/A Converter. 90
7.2.1.1 The Floorplan . . . . . . . . 90
7.2.1.2 Design of the swatch cell . . 91
7.2.1.3 Design of the thermometer decoder . 93
7.2.1.4 The switching scheme . 94
7.2.1.5 The layout . . . . . . . . . . . . 95
7.2.1.6 Measurement results. . . . . . . 96
7.2.1.6.1 Static measurements . 96
7.2.1.6.2 Dynamic measurements 97
7.2.l.7 Conclusion....... .. . . . . 100
7.2.2 A 14-bit Intrinsic Accuracy Q2 Random Walk CMOS D/A
converter . . . . . . . . . . . . . . . . . . . . . . 102
. . . . . .
7.2.2.1 The Floorplan . . . . . . . . . . . . . . . . . . . . 102
7.2.2.2 Design of the swatch cell and the thermometer de-
coder . . . . . . . . . . 102
7.2.2.3 The switching scheme . 103
7.2.2.4 The Layout. . . . . . . 105
7.2.2.5 Measurements..... 106
7.2.2.5.1 Static measurements. 106
7.2.2.5.2 Dynamic measurements 106
7.2.2.6 Conclusion............. 108
7.3 High Speed D/A Converters . . . . . . . . . . . . . 111
7.3.1 A 800 MHz Ultra Low Glitch Energy 6-bit CMOS D/A Con-
verter . 111
7.3.1 .1 The Floorplan . . . . . . . . . . . . . . . . . 111
. . .
CONTENTS xi

7.3.1.2 Design of the swatch cell and the thermometer de-

coder . . . . . . .. . . 112
7.3.1.3 The switching scheme. 113
7.3.1.4 Layout . . . . . . .. . 113
7.3.1.5 Measurements. . . . . 113
7.3.1.5.1 Static measurements. 115
7.3.1.5.2 Dynamic measurements 115
7.3.1.6 Conclusion...... . . . . . . . 116
7.4 High Speed, High Accuracy D/A Converters. . . . . 120
7.4.1 A 1O-bit I-GS/s Nyquist Current-Steering CMOS D/A Con-
verter . 120
7.4.1.1 The Floorplan . . . . . . . . . . . . 120
7.4.1.2 Design of the swatch cell . . . . . . 123
7.4.1.3 Design of the thermometer decoder . 126
7.4.1.4 The switching scheme . 130
7.4.1.5 The layout . . . . . . . . . .. . 133
7.4.1.6 Measurement results . . . . . . . 133
7.4.1.6.1 Static measurements . 133
7.4.1.6.2 Dynamic measurements 134
7.4.1. 7 Conclusion . . . . . . . . . . . . . 137
7.4.2 A 12-bit 500-MS/s Current-Steering CMOS D/A Converter 140
7.4.2.1 The Floorplan . . . . . . . . . . . . . . . . .140 . .
7.4.2.2 Design of the swatch cell and the thermometer de-
coder . . . . . . . . . . 141
7.4.2.3 The switching scheme . 142
7.4.2.4 The layout . . . . . . . 143
7.4.2.5 Measurement results . . 144
7.4.2.5.1 Static measurements . 144
7.4.2.5.2 Dynamic measurements 144
7.4.2.6 Conclusion . . . . . . 149
7.5 Low Power High Speed DJ A Converters . . . . . . . 149
7.5.1 Introduction .. . . . . . . . . . . . . . . . . 149
7.5.2 A Low Power 10 bit fully binary D/A Converter . 150
7.5.2.1 Floorplan .. .. . . . . . 150
7.5.2.2 Design of the swatch cell 150
7.5.2.3 The switching scheme . 150
7.5.2.4 The Layout . . . . . .. . 152
7.5.2.5 Measurement Results . . 152
7.5.2.5.1 Static measurements . 152
7.5 .2.5.2 Dynamic measurements 152
xii CONTENTS

7.5.2.6 Conclusion. 156

7.6 Overview of Realised DACs 159
7.7 Comparison with literature . 159
7.7.1 The Figure of Merit . 159
7.8 Conclusion . . . . . . . . . 162

8 Transistor Mismatch: Evolution and Relevance 165

8.1 Introduction.............. 165
8.2 Model of Lakshmikumar . . . . . . . 166
8.2.1 Characterisation Methodology 166
8.2.2 Physical causes for mismatch 167
8.2.2.1 Threshold Voltage Mismatch 167
8.2.2.2 Current factor mismatch . 168
8.3 Model of Pelgrom . . . . . . . . . . . 169
8.3.1 Characterisation methodology 169
8.3.2 Mismatch model 170
8.4 Other models . . . . . . 171
8.4.1 Model of Abel . 171
8.4.2 Model of Bastos 172
8.4.3 Model of Gotarredona-Linares 174
8.4.4 Model of Griinebaum-Oehm . 176
8.4.4.1 The Spectral model 176
8.4.4.2 Different mismatch effects explained 177
8.4.5 Drennan-McAndrew.............. 178
8.4.6 Model of Croon. . . . . . . . . . . . . . . . . 179
8.5 Mismatch parameters for the 0.5 and the 0.4 p.,m CMOS technology 181
8.5.1 The 0.5 p.,m technology . . . . . . . . . . . . . . . . .181
8.5.2 The 0.4 p.,m technology. . . . . . . . . . . . . . . . 183
8.5.3 Evolution of the mismatch parameters A VT and A.s . . 186
8.6 Transistor mismatch dependency on its geometry 186
8.6.1 Introduction......... 186
8.6.2 Different Layout Structures 186
8.6.3 The hexagonal transistor . . 188
8.6.3.1 Introduction . . . 188
8.6.3.2 The Hexagonal Transistor. 189
8.6.3.2.1 The transistor structure 189
8.6.3.2.2 The transistor parameters 189
8.6.3.3 Transistor Properties of the Hexagonal Structure 191
8.6.3.3.1 The drain and source capacitance. 191
8.6.3.3.2 The matching performance 195
8.6.3.4 Conclusion.................. 198
CONTENTS xiii

8.7 Influence of the surroundings of the transistors on the mismatch be-

haviour . . . . . . . . . 198
8.7.1 Side Effects . . . . . . . . . . . . . . . . . . . . . . 198
. . . . .
8.7.2 Metal Coverage . . . . . . . . . . . . . . . . . . . . . . . . . 198
8.8 The CMOS current steering D/A Converter as a test structure for tran-
sistor mismatch parameter extraction . 199
8.8.1 Introduction.......... 199
8.8.2 The Test Structure Approach . 199
8.8.3 The D/A converter Approach. 200
8.8.3. I The D/A converter architecture as a test structure. 200
8.8.3.2 Measurement and extraction procedure of the tran-
sistor mismatch parameters 201
8.8.3.3 Measurement Results 202
8.9 Conclusion 202

Appendix 1 205

Appendix 2 207

Bibliography 211
List of Symbols and Abbreviations

Symbols

AVT , A,6 MOS transistor mismatch parameters

f3 Current factor of a MOS transistor
C gs , Cgd, etc. Device capacitances
dB decibel
f Frequency
gm Transconductance
go Transistor small-signal output conductance
L, W Transistor gate-length and gate-width
VT Threshold voltage
q Elementary Charge

Abbreviations

AC,ac Alternating Current

ADC, AID-converter Analog-to-Digital Converter
ASIC Application Specific Integrated Circuit
CMOS Complementary Metal Oxide Semiconductor
CPU Central Processing Unit
DAC, D/A-converter Digital-to-Analog Converter
DC,dc Direct Current
DNL Differential non-linearity
DSP Digital Signal Processing
ENOB Effective Number of Bits
FSOC Full scale output current
FOM Figure-of-Meri t
GBW Gain-bandwidth product
GSM Global System for Mobile communications
xvi List of Symbols and Abbreviations

HF High Frequency
IC Integrated Circuit
INL Integral non-linearity
LSB Least Significant Bit
MSB Most Significant Bit
nMOS N-channel Metal Oxide Semiconductor
pMOS P-channel Metal Oxide Semiconductor
RF Radio Frequency
SFDR Spurious Free Dynamic Range
SNDR Signal to Noise and Distortion Ratio
SIN ratio, SNR Signal-to-Noise Ratio
SR Slew Rate
THD Total Harmonic Distortion
VLSI Very Large Scale Integration
xDSL Any type of digital subscriber line
Chapter 1

Introduction

1.1 Introduction

During the last decade, the telecommunication market and especially the mobile tele-
communication systems have known an unprecedented growth. New services are con-
stantly being introduced since the evolution towards smaller technologies makes it
possible to integrate millions of transistors on a single chip. The digital designers cre-
ate new DSP (Digital Signal Processing) architectures that allow complex algorithms
to be implemented at very high computational speeds. In parallel, analog designers
have been putting an enormous effort in developing high speed, low distortion blocks
that in combination with the digital building blocks will result in the high performance
telecommunication systems of tomorrow. However, this implies that the design of the
interface circuit between the analog and digital part of the system -the D/A converter
and the AID converter- is becoming more challenging in time. Besides a highly ac-
curate circuit also a high operation speed achieved at a low power consumption are
demanded. The combination of these constraints poses a real challenge for the de-
signers of these circuits. Furthermore, additional problems -like the substrate noise
coupling from the digital to the analog part on the chip and the scaling of the power
supply voltage- add to the complexity of the design.

The presented work will focus on the design and implementation of high perfor-
mance D/A converters and especially the current steering topology which offers at the
moment the best result when realising the aforementioned constraints of speed, accu-
racy and power consumption in CMOS technologies. Since the static behaviour of a
current steering architecture strongly depends on the mismatch behaviour of the tran-
sistors used to implement the current sources, this work will also address this issue in
some more detail.
2 Introduction

1.2 Outline of the Research Work

Fig.l.l gives a schematic overview of this manuscript. First, chapter 2 will introduce
the main set of specifications that are needed to fully describe the performance of a
DIA converter. In the past, most publications only described the static behaviour of the
presented DIA converter, while the telecommunication engineers of today also need
information on the frequency domain behaviour of the circuit in order to accurately
determine its impact on the whole system they are developing. Therefore, the second
chapter of this work starts with a description of the basic functionality of an ideal DIA
converter and the limitations this imposes on its attainable performance. Then, the
different specifications that are commonly used (INL, DNL, ... ) to describe the static
performance of a D/A converter, are discussed in more detail. The remainder of this
chapter gives an overview of the dynamic specifications (SFDR, ...).
Chapter 3 gives an overview of the different topologies existing today to imple-
ment a D/A converter. The basic functionality of this circuit is to generate for each
digital input code a multiple of a certain reference quantity. Dependent on this quan-
tity (a voltage, a charge or a current), three classes of D/A converters can be identified
namely the resistor, the capacitor and the current steering architecture. In the first part
of this chapter, both the resistor and the capacitor DIA converter will be discussed. It
is the intention of the author to emphasise the existence of these architectures as useful
alternatives for the current steering architecture. For a detailed study the reader is re-
ferred to [Razavi, Johns]. The remainder of this chapter describes the current steering
topology. This topology will be analysed throughout this work.
The current steering topology is at the moment the preferred architecture for
telecommunication applications requiring a high accuracy. In the fourth chapter, the
emphasis will be put on the different factors that influence the static performance of
this topology. This performance is mainly determined by the matching behaviour
of the current source transistors. Since no two transistors behave exactly the same
due to technological variations introduced during processing, it is important to know
the impact of this phenomenon on the yield and the performance. This topic will be
discussed in the first part of this chapter. Apart from the process variations which gen-
erate random errors, the current sources in the array are also influenced by systematic
errors that are introduced by thermal, electrical and process gradients which will be
discussed in detail in the second part of this chapter.
Chapter 5 will focus on the dynamic performance of the current steering DIA con-
verter. The first part of this chapter will identify and discuss some design guidelines
that will solve the generally known problems such as the imperfect synchronisation
of the switch control signals, the digital signal feedthrough through the gate-drain ca-
pacitance of the switch transistors and the drain voltage variation of the current source
1.2 Outline of the Research Work 3

transistor. The remainder of this chapter will focus on a fourth factor with a major
impact on the frequency domain behaviour of the DIA converter, namely the dynamic
output impedance. A formula will be derived for the spurious free dynamic range as
a function of this impedance, providing the designer with the necessary information
to design a high speed Nyquist D/A converter. For high resolution circuits, this im-
plies the use of cascoded current cell structures as is discussed in the last part of this
chapter.
The next chapter covers the design flow of a current steering topology. After dis-
cussing the approach to determine the segmentation level (number of binary and unary
bits), the considerations that have to be made in choosing the thermometer decoder
and the switch driver will be discussed. The remainder of this chapter describes the
dimensioning of the transistors of the unit current cell (the switch, current source and
cascode transistor).
In chapter 7, several implemented DIA converters will be discussed ranging from a
high accuracy circuit (12 bits and 14 bits) to a high speed circuit (10 bits IGSample/s)
and to a combination of both (12 bits 500 MSamples/s). Also the design of a 10 bit
low power DIA converter for telecommunication applications will be addressed. The
last section of this chapter gives an overview of the most important static and dynamic
specifications of the realised DI A converters and of the state-of-the-art published de-
vices. In order to make a comparison possible, a figure of merit will be introduced
that is based on the resolution, the dynamic behaviour and the power consumption.
It is easy to understand that the design of high performance analog circuits such
as DIA and AID converters, reference sources, .. . requires the availability of reliable
transistor mismatch models. Designers have to be able to rely on accurate simulation
tools if they want to be successful in the realisation of a circuit with a performance
that lies closely to the limits of the given technology. However, the accuracy of such
simulation tools is determined by the underlying models. At this moment, the analog
designer has to introduce large safety margins to guarantee the required performance
of the circuit leading however to an unnecessary power consumption and an operation
speed reduction [Kinge CICC96]. In literature, several models have been presented
that describe the mismatch characteristics of the transistor by providing the designer
with the standard deviation of the mismatch in a set of electrical parameters (like
the threshold voltage VT, the current factor (3, the mobility degradation parameter (),
the bulk threshold parameter y). In the first part of chapter 8, an overview of these
models will be given starting with the basic models presented by Lakshmikumar and
Pelgrom [Laksh JSSC86, Pelgr JSSC89]. However, going to deep submicron tech-
nologies, these models have to be adapted as to explain the transistor mismatch of
short and narrow devices. The extraction of the transistor mismatch parameters for
a 0.5 and a 0.4 pm standard CMOS technology and the transistor mismatch depen-
4 Introduction

dency on the used topology (wafer, quad or hexagonal structure) and its immediate
surroundings (metal coverage, ... ) will be discussed.
For the VLSI manufacturer, it is important to be able to provide his customers with
the necessary quantitative data of the matching quality of his technology. This can be
achieved by the use of dedicated test circuits that are especially designed for this pur-
pose (low parasitics, high measurement accuracy, ... ). Furthermore, it is necessary
to follow the evolution of the matching performance of the technology over different
runs in time. This requires a test circuit that gives a good indication of the matching
technology for a low cost. However, these circuits are of no further use to the manu-
facturer or the designer and therefore an alternative structure has been sought for. A
high performance current steering D/A converter is highly dependent on the matching
quality of the technology. Furthermore, the evaluation of the DIA converter's perfor-
mance poses no problem since there exist standardised test procedures. In the last
part of chapter 8, the D/A converter's performance will be directly translated in the
transistor mismatch characteristics of the used technology.
Finally, the last chapter of this work gives a summary of the main results that have
been achieved in this work and some recommendations are formulated towards future
research.
 ....
N
85 86 87 88 89 0
::.
=
S·
• non-idealities &(1{ L : f& v} ~ ..rJ
• static specifications I~
• dynamic specifications
~
=-
Chapter 3 j D/A converter architectures dump, out
-
I?;
flO
• resistor topology
• capacitor topology
.s::,'
• c( urrent steering topology)
~I
r' ~1 I~::l
ell matrix =-
/ ~ ..,~
~
Chapter 4 j Static Behaviour of current steering D/A converters Chapter 5 j Dynamic behaviour of current steering D/A converters
• random errors : new INL-yield formula • known problems (timing, feedthrough , off-period)
• systematic errors : new switching schemes • output impedance : new formula as a function of the resolution

C') (.) [S
' I ~ ~ +-t -t { /
IJl
('II ~ C Chapter 6 A design methodology for high performance current steering D/A converters
~
IJl
Chapter 7 j Realizations
• high accuracy' circu its (12 & 14 bit)
• high speed circuits (6 bit aOOMS/s)
• high accuracy & high speed (10 bit 1GS/s & 12 bit SOOMS/s)
• low power circuits (10 bit 7.amW)

Chapter a j Transistor Mismatch : Evolution and Relevan~ t i

L L r
Figure 1.1: Outline of the presented work

til
Chapter 2

The DIA Converter: Functionality and

Specifications

2.1 Introduction

Although the digital world is gaining in importance due to the decreasing feature size
of transistors in the rapidly evolving semiconductor technology, the analog building
blocks have proven to be indispensable. The advantages of digital processing (easier
design, extensive programmability, ... ) are counteracted by the fact that people per-
ceive information in an analog form (f.i. speech). The design of the interface between
the analog and the digital system (the AID and the D/A converter) has to comply with
the stringent specifications required by modern complex digital systems. Furthermore,
additional problems -like the substrate noise coupling from the digital to the analog
parts on the chip- add to the complexity of the design.
Where a few years ago, most papers only described the static behaviour of the
DIA converter, the telecommunication engineers nowadays also need information on
the frequency domain performance of these devices. The specifications describing
both the static and the dynamic behaviour of a DIA converter will be discussed in this
chapter.

2.2 The Basic DIA Converter Function

2.2.1 Analog and Digital Signals

Fig.2.1 gives a general schematic representation of the telecommunication systems

that are used nowadays. All the signals in the our surrounding world have an analog
8 The DIA Converter: Functionality and Specifications

r Digital Signal

T
Processing
Unit

Figure 2.1: The general schematic of a telecommunication system

nature (like f.i. speech), which means that those signals have a continuous amplitude
varying in time. However, in order to perform the required signal operations mostly
digital algorithms are used since digital signal processing systems are relatively easy to
design and are highly flexible due to their programmable software. Furthermore, they
are capable of realising quite complex data manipulation algorithms and incorporate
a high computing power on a small area. Digital signals can have only two values,
namely, ahigh state ("1") and a low state ("0") and are only allowed to vary according
to a specified clock. These signals are therefore discrete in time and amplitude. To
transform an analog signal into a digital signal and vice versa, ND and D/A converters
are used.
However, since a N-bit digital signal can only have 2N values, the amount of
information at any given moment in time is limited and depends on the resolution
(N) of the D/A converter. To illustrate this principle, fig.2 .2 is given. Describing an
analog signal at a given update rate with an one bit accuracy, only allows a coarse
approximation as is indicated in fig.2.2.a. To improve the quality of the reconstructed
analog signal, the resolution and/or the update rate of the D/A converter have to be
increased (fig.2.2.b/c/d). It should be noted that a lower bound for the update rate is
imposed by the Nyquist-Shannon theorem. This theorem states that the update rate of
the D/A converter has to be larger than or equal to two times the highest frequency
component of the signal in order to avoid aliasing and thus be able to fully reconstruct
the signal. Although one can conclude from this discussion that a high accuracy D/A
with a high update rate will give the best results, these devices will increase the cost
2.2 The Basic DIA Converter Function 9

o Ca)

11
10
01
(b)
00

11
10
01
(c)
00
time
111
110
101
100
011
010 (d)
001
000 ~.L..L...L..l.....L....e......,L....L.J4-JL.....L...,"""J....J...L....L..J..-_-+
time

Figure 2.2: Influence of the resolution and the update rate on the digital representation
of an analog signal

of the overall system. Therefore, the actual requirements of the DfA converter always
depend on the application and the signals that need to be processed.

2.2.2 The DIA Converter as a Black Box

The input of the DfA converter is a N bit digital sequence that can be described by the
following binary vector:

bi E{O,I} (2.1)
10 The DIA Converter: Functionality and Specifications

where bo is the least significant bit (LSB) and bN-l is the most significant bit (MSB).
The decimal number corresponding to this binary vector is equal to :
N-l
B = I: i bi (2.2)
i=O

The D/A converter's output signal can either be a charge, a voltage or a current and
can be expressed as :
N- J
Yout(B) = I: 2i bi * Yre! = B * Yre! (2.3)
i=O

where Yre! denotes the unity (=LSB) charge, voltage or current depending on the D/A
converter's architecture.

2.3 The Characteristics of an Ideal DIA Converter

2.3.1 Introduction

The function of an ideal DIA converter is the reconstruction of an analog waveform

using sequences of digital words at the input. However, since these digital input words
have a finite length and are updated at discrete time intervals, the output of the D/A
converter has a shape similar to the one of a sample-and-hold circuit. The discrete
nature of the D/A converter's waveform reconstruction process imposes quantifiable
limitations on the accuracy with which even an ideal DIA converter can generate an
analog waveform. These limitations will be discussed in more detail in this paragraph.

2.3.2 The Quantisation Error

By representing an analog signal with a finite number of bits, an error is introduced

between the analog value and its digital representation. This error -which is called
the quantisation error- inherently limits the maximum achievable dynamic range of
the DI A converter. To better understand its impact on the dynamic behaviour of this
device a short derivation is given [Razavi, VdPlassche, Stehr]. Fig.2.3 clearly shows
that the quantisation process introduces an irreversible error since a signal with an
amplitude Yj + E: will be quantised into the level Yj. This procedure introduces a
random error that can be considered to be equivalent to white noise in the frequency
domain.
In this derivation E: denotes the quantisation error and ~ denotes the quantisation
step (fig.2.3). Furthermore, it has been assumed that E: is :
2.3 The Characteristics of an Ideal DIA Converter 11

-
>
::s
o
7

3
2

0""'"_ _ _ _ _ _ _ _ _ _ _.....
000 001 010 011 100 101 110 111 X

-/;,,/2

Figure 2.3: The quantisation error of a DIA converter

• a random variable that is uniformly distributed in the interval [- /:,. /2 , /:,. /2]

• independent of the analog signal.

In this case, the quantisation noise power can be expressed as the mean square value
of £:
Pnoise = E(£2) = -
1 1/::,/2 /'1
£2d£ = -
2 (2.4)
/:,. - /::, / 2 12
For a D/A converter with a high resolution (N :::: 5), the peak-to-peak value of a sinu-
soidal output signal can be approximated by :

(2.5)

The total signal power is then equal to :

V2 22N A 2
pIp il
Psignal = - - = - - (2.6)
8 8
The signal-to-noise ratio can be calculated using eq.(2.4) and eq.(2.6) :

(2.7)
12 The DIA Converter: Functionality and Specifications

time

g
> fundamental signal
/

3fs frequency

Figure 2.4: The amplitude reduction error of an ideal DIA converter (fs is the sam-
pling frequency)

or expressed in decibels:

SN R = 6.02N + 1.76dB (2.8)

This equation is often used to compare the performance of a given DI A converter with
that of an ideal D/A converter. From eq.(2.8) it can be concluded that the influence of
the quantisation error on the signal-to-noise ratio decreases when the resolution of the
DIA converter increases.

2.3.3 The Sample and Hold like Amplitude Distortion

During signal reconstruction, the D/A converter acts as a sample-and-hold circuit

(fig.2.4). The analog output signal remains constant during the sampling time ts. In
the time domain the output is thus represented as a series of modulated rectangular
2.4 The Performance Specifications of a DIA Converter 13

pulses, while in the frequency domain the spectrum of the output is distorted by the
sin(x)lx response (in which zeros appear at multiples of the sampling frequency). The
frequency response of the output is given by :

(2.9)

When sampling at the Nyquist rate, the input frequency fin equals half the sampling
frequency fs leading to an amplitude reduction of 21]( or 3.92 dB.
As a conclusion it can be stated that the sin(x)lx frequency response acts as a low
pass filter that modifies the amplitude of the fundamental signal. In some applications,
this amplitude distortion has to be corrected by the use of an inverse sin(x)/x filter or an
equalizer. Furthermore, the reconstruction of the sampled signal typically requires the
elimination of the image frequencies. For narrow-band signals (fin « f s) the sin(x)/x
filter can already introduce a significant suppression of these unwanted signals. Other-
wise, an explicit analog reconstruction filter is needed after the D/A converter.

2.4 The Performance Specifications of a DIA Converter

2.4.1 Introduction

In order to be able to compare different DIA converter architectures, a number of

performance measures have been introduced. Each of these measures highlights a
different aspect of the DIA converter. Their importance has to be determined ac-
cording to the D/A converter's intended use. High accuracy D/A converters that are
used for instrumentation purposes should have a low integral non-linearity, differential
non-linearity and offset error while D/A converters used for waveform reconstruction
applications (f.i. telecommunication) should have an excellent dynamic performance
(low total harmonic distortion, ... ).
In literature different definitions for these specifications can be found. In this
paragraph an overview of the most important static and dynamic measures are given
based on [Hendriks, VdPlassche, Stehr, Razavi].

2.4.2 The Static Specifications

2.4.2.1 Introduction

The static specifications described in this paragraph give an idea of the DIA converter's
distortion performance at low frequencies. It are these specifications that ultimately
14 The D/A Converter: Functionality and Specifications

'S
c.
'S
o
til
o
OJ
c:
, ,
,,
I'll

, ,
,,
,. ,
OFFSET

digital input digital input

(a) (b)

Figure 2.S: The static specifications of a DIA converter

impose the performance limit of the D/A converter. The most important static mea-
sures are the integral and differential non-linearity error.

2.4.2.2 The Offset Error and the Gain Error

The offset error is defined as the constant DC offset of the DIA converter transfer
characteristic while the gain error is defined as the deviation of the slope of the mea-
sured D/A converter in comparison with its ideal characteristic (fig.2.S.b). Since these
errors do not introduce any non-linearities, no effect is seen on the frequency domain
characteristics.

2.4.2.3 The Differential Non-Linearity Error (DNL)

The differential non-linearity error is the worst case deviation between the actual and
the ideal step size (= I LSB) between two adjacent codes. It can be described as:

DN L = max (Yout (B) - Yout(B - 1) - lLSB) (2.10)

Fig.2.S.a gives a graphical representation of the DNL error.

2.4.2.4 The Integral Non-Linearity Error (INL)

The integral non-linearity error (INL) is defined as the maximum deviation of the
measured D/A converter transfer characteristic from the ideal output curve (fig.2.S.a).
This ideal curve is a straight line that is determined by the D/A converter's measured
2.4 The Performance Specifications of a DfA Converter 15

zero and full-scale output. This implies that nor the gain error nor the offset error has
an impact on the INL value. This curve is described by :

Y I (2 N - 1) - Y (0)
. (B)
YoUI.ld = Youl (0) + ou 2N _ 1 out *B (2.11)

Using eq.(2.11), the INL can be expressed by :

IN L = max(Yout(B) - Yout,id(B)) (2.12)

Using this definition for the ideal output curve implies a compensation of the offset
and the gain errors since a zero output for Yout(O) excludes a potential offset error and
the boundary condition for the maximal output eliminates the gain error. In practice
the definition of the ideal output curve as the "best fit" through the OfA converter's
measured code transitions is frequently used.
Both INL and ONL errors are measured in terms of LSB's and can have either
positive or negative values. Although these measures give a good indication of the
static behaviour of the OfA converter, in some cases they also provide the designer
with some general information on the frequency domain behaviour of the converter.
The shape of the INL characteristic gives an indication of the distortion component
that will limit the OfA converter's dynamic performance. Fig.2.6.a shows the output
spectrum for a OfA converter where the dynamic behaviour is determined by quantisa-
tion noise. The impact of the INL characteristic is illustrated in fig.2.6.b and fig.2.6.c.
It is shown that a bow like INL characteristic gives rise to a spurious free dynamic
range (defined in the section regarding dynamic specifications) that is determined by a
second order harmonic (for a low frequency signal at a low update rate). This already
indicates the maximum achievable limit for the SFOR since for high frequency signals
andfor high update rates other factors like timing errors gain in importance and will
further deteriorate the dynamic performance. It should however be clear that two Of A
converters with the same INL error can have totally different distortion components
since in both cases the INL characteristic can be completely different.

2.4.2.5 Monotonicity

A DfA converter is monotone when its output never decreases with an increasing
digital input code. This implies that a minimum increase of zero is allowed when
the input signal of the DfA converter increases with only one LSB. It can be proven
for a binary DfA converter that it is always monotonic when the integral non-linearity
error is less than or equal to 112 LSB [VdPlassche].
16 The DIA Converter: Functionality and Specifications

12-bit sine with noise

U
III
~
a:
cu. -1
en

3 4 5 6 7 8 9 10
Normalised Frequency

INL rofile

0.9

0.8

0.7

ai'
en 0.6

:::.... 0.5

......0 0.4
III 0.3

0.2

512 1024 1536 2048 2560 3072 3584 4096

Code

12-bit sine

U
III
~
a:
cu.
en

_160 L-~--.L~--'-~-~~-~-~~---.J
o 3 4 5 6 7 8 10
Normalised Frequency

Figure 2.6: The INL characteristic related to the dynamic performance of the DIA
converter
2.4 The Performance Specifications of a DIA Converter 17

clock-feedthrough

so \
~ DNL

slew rate I

~
---
_ _ _ _ ideal response

-- - - non-ideal response

settling time

time

fundamental
s signal image signal
>
harmonics
a:
cLL
(/)
clock
feedthrough

frequency
Nyquist bandwidth

Figure 2.7: The dynamic specifications of a DIA converter

2.4.3 The Dynamic Specifications

2.4.3.1 Introduction

The influence of the dynamic non-linearities on the distortion performance of the D/A
converter can be described by using measures in both the time and the frequency
domain. Although the time domain specifications were frequently used in the past,
the frequency domain specifications gain in importance.
The main purpose of DIA converters used in telecommunication systems is the
reconstruction of waveforms from digital data. It is important that as a result of this
conversion no new signal components are created that alter the information content of
the original signal. In the remainder of this paragraph, the most important time and
frequency domain specifications will be discussed in more detail.
18 The DIA Converter: Functionality and Specifications

output voltage

0 11 0 11

E".SB

Figure 2.8: The glitch energy error

2.4.3.2 The Update Rate

The update rate is the rate at which the output is sampled. It therefore determines the
maximal output signal frequency (which equals half of the update rate according to
the Nyquist theorem).

2.4.3.3 The Settling Time

In general, the settling time of a D/A converter is defined as the time required for the
output to experience a full scale transition and to settle within a specified error band
around its final value.
However, also in the code-to-code transition response a settling time can be defined
(fig.2.7). If this settling time is dependent on the applied code, it will affect the DIA
converter's frequency domain behaviour.

2.4.3.4 The Glitch Energy

The glitch impulse gives an idea of the error generated by the earliest part of the
transient response when the D/A converter switches between two consecutive output
codes (fig.2.7). The glitch energy is defined as the area under this transient response.
This error is mainly caused by timing errors within the DIA converter and results in a
deterioration of the dynamic performance.
A qualitative description of the glitch energy for a binary D/A converter is given
2.4 The Performance Specifications of a DIA Converter 19

here under the following assumptions [VdPlassche]:

• the largest glitch impulse occurs at the MSB transition

• the glitch impulse has a square shape (worst case calculation)

• the timing error is represented by tdiJ

• the peak-to-peak amplitude of the D/A converter is given by A pIp

The glitch energy error can then be expressed as (fig.2.S):

A p1p
E glilch = tdiJ * -2- (2.13)

The energy of one LSB equals :

A p1p
ELSB = 2- +
N I
* t sample * -2- (2.14)

To have a DIA converter with a good dynamic performance, the following ratio has to
be minimised:
E glil ch tdiJ
= ---"---- (2.15)
ELSB 2- N + 1 * t sampl e
The glitch energy can be reduced by placing a "deglitcher" circuit at the output of
the DIA converter. However, since such highly accurate linear circuits are difficult
to design, it is simpler to minimise the timing error tdiJ by the use of well-placed
synchronisation blocks.

2.4.3.5 The Slew Rate

The slew rate is defined as the maximal rate at which the output of the D/A converter
can change with the varying input (fig.2.7).

dVout dVout dq I
SR=--=--*-=- (2.16)
dt dq dt C out

It should be noted that the slew rate can be different for the charging (SR+) or the
discharging (SR-) of the output capacitance depending on the architecture of the D/A
converter. If the output slewing has code dependent rise and fall times, it is also a
contributor to distortion.
20 The DfA Converter: Functionality and Specifications

2.4.3.6 The Clock-Feedthrough

Due to parasitic capacitive coupling, the effect of the switching of the clock can be
directly seen at the output of the DfA converter (fig.2.7). This clock feedthrough does
not introduce any additional noise or distortion in the Nyquist baseband zone since it
is not code dependent and manifests itself in the frequency domain as a component at
the sampling frequency. This component can be easily removed by the use of a low
pass filter at the output of the DfA converter.
Other feedthrough components that arise from coupling between the digital and
the analog part of the DfA converter usually tend to increase the overall noise floor
unless this feedthrough is directly related with the input codes.

2.4.3.7 The Signal to Noise Ratio (SNR)

The signal to noise ratio (SNR) is defined as the ratio of the power of the fundamental
signal to the integrated noise power. Although this specification is rarely quoted on
the DfA converter's data sheets, it is an important frequency domain specification. A
lower limit of this specification is dictated by the quantisation noise. The quantisation
contribution has already been calculated in paragraph 2.3.2.

SNR = 6.02N + 1.76dB (2.17)

2.4.3.8 The Signal to Noise and Distortion Ratio (SNDR)

The signal to noise and distortion ratio (SNDR) is defined as the ratio of the power of
the fundamental signal to the sum of the integrated noise power and the power in all
distortion components.

2.4.3.9 The Spurious Free Dynamic Range (SFDR)

The spurious free dynamic range (SFDR) specification is defined as the ratio between
the fundamental signal and the largest distortion component within a specified fre-
quency band (fig.2.7). This distortion component does not necessarily has to be a
harmonic of the fundamental signal nor does the frequency band has to be equal to the
DfA converter's Nyquist baseband zone.

Psignal
SFDR=-.....:..:.!':.~- (2.18)
Plargest-di st

In some applications it is sufficient to have an idea on the SFDR specification

within a certain frequency interval as any larger out-of-band spurs will be filtered out
2.4 The Performance Specifications of a D/A Converter 21

Resolution [bits]
Oversampling DACs
20 r--------------"

Nyquist rate DACs

12 '-----r--------------
I I I
I

I
I I
-----~--------------'

Audio Video Telecommunication

Bandwidth [Hz]
Figure 2.9: The different DIA converter types as a function of speed and resolution
[Wikner]

in the next stage. In any case, it is imperative that the SFDR specification is always
given together with the information concerning the measured frequency window. Fur-
thermore, it should be noted that the SFDR is not a constant for a given D/A converter
as the INL specification is. It depends on the operating conditions, the update rate,
the digital sine wave and on the measurements (differential or single ended output).
Therefore, in order to characterise the dynamic performance of a DIA converter, the
SFDR should be given as a function of the update rate (for a number of fixed full-
scale sinusoidal output signals) and as a function of the signal frequency (for different
values of the update rate).

2.4.3.10 The Total Harmonic Distortion (THD)

The total harmonic distortion is defined as the ratio of sum of the power of the har-
monic components to the power of the fundamental signal (eq.2.19). This specifica-
tion is usually expressed in decibels and gives a more complete picture of the DIA
converter's distortion performance than the SFDR.

THD = PH2+H3+H4+ ...

(2.19)
Psignal

Since in most cases the worst distortion component is harmonically related and
contains more than 80 % of the total harmonic energy, the total harmonic distortion
is rarely plotted over frequency since its value is only 1-3 dB higher than the SFDR
22 The DIA Converter: Functionality and Specifications

value. However, plotting the three most significant harmonic distortion components
as a function of the frequency can be helpful in gaining more insight in the D/A con-
verter's spectral performance.

2.5 The DIA converter specifications as a function of

the application

Based on a literature study, a schematic overview of the required specifications in

terms of resolution and bandwidth is given as a function of the application area (audio,
video or telecommunication applications) in fig.2.9. This study has been done by
[Wikner]. From this figure, it can be concluded that current steering Nyquist D/A
converters are highly suited for high speed applications.

2.6 Conclusions

In this chapter the basic functionality and the characteristics of an ideal DIA converter
have been described. To make a comparison between different DIA converters possi-
ble, a set of performance measures have been introduced that describe the static and
the dynamic behaviour of these devices.
Chapter 3

CMOS D/A Converter Architectures

3.1 Introduction

In the previous chapter, the functionality of a DIA converter has been explained to-
gether with the specifications that describe its static and dynamic behaviour. This
chapter discusses the different architectures for a D/A converter.
A DIA converter generates for each digital input code a mUltiple of a certain re-
ference quantity. Dependent on this quantity (a voltage, a charge or a current), three
classes of D/A converters can be identified namely the resistor, the capacitor and the
current steering architecture. In the first part of this chapter, both the resistor and
the capacitor DIA converter will be discussed. It is the intention of the author to
emphasise the existence of these architectures as useful alternatives for the current
steering architecture. For a detailed study the reader is referred to [Razavi, Johns].
The remainder of this chapter describes the current steering topology. Three possible
implementations together with their advantages and disadvantages will be discussed
in detail. During the remainder of this thesis, this architecture will be analysed with
regard to its static and dynamic performance.

3.2 The Resistor DIA Converter

3.2.1 The resistor string D/A converter

In this type of D/A converter, a reference voltage is divided into 2N - 1 parts by

selecting one tap of a segmented resistor string using a switching network (fig.3.1).
Although this implementation provides a simple and inherently monotonic D/A con-
version, it has some major drawbacks. For resolutions higher than eight bits, the
24 CMOS D/A Converter Architectures

VREF

B3

R
B2
">-_e_----{') VOUT
R
B1

R
BO

-=-

Figure 3.1: The resistor string architecture

occupied silicon area becomes fairly large. For a ten bit DIA converter, 1023 resistors
and 1024 switches are required. Furthermore, the delay through the switching network
poses a severe limitation on the update rate of the DIA converter.
The integral non linearity error is directly related to the matching precision of the
used resistors. Due to uncertainties during processing, the values of the resistors in
the resistor string will not be equal. The relative mismatch between two resistors is
given by:
!:::. R !:::. P !:::.L !:::. W !:::.t !:::.Rc
-=-+-----+-- (3.1)
R p L W t R

with Rc the contact resistance, L the length, W the width, t the thickness and p the
resistivity of the resistor. The width, length and value of the resistor can be freely
chosen by the designer as to minimise the mismatch. However, larger dimensions
need more silicon area and create a higher capacitance to the substrate.

The influence of this mismatch on the integral non-linearity error of the resistor
string D/A converter is given by [Razavi]:

Vref !:::. R
INL=---- (3.2)
.j4N R

which is reached at the middle of the resistor string. Since this formula is a standard
deviation, it has to be interpreted as follows. In 68 % of the cases, the non-linearity
error will be smaller than or equal to the value calculated in eq.(3.2).

For high speed, high accuracy applications, this architecture is no longer the pre-
ferred solution.
3.2 The Resistor DIA Converter 25

VREFn---~------~--------------~

SR 4R 2R R

83 82 81 BO

o 0

R
13 12 11 10

liN ">----+----0 VOUT

Figure 3.2: The binary weighted resistor DIA converter

3.2.2 The binary weighted resistor DIA converter

This type of converter is very similar to the resistor string structure. Each resistor
in the string is given a value proportional to the binary value of the bit it represents
(fig.3.2). The currents generated from each active bit are then summed to obtain the
required output. The number of resistors and switches is now reduced to one per bit,
but the range of the resistors is extremely wide for high resolution D/A converters.
Furthermore, it is important to note that the feedback resistor R is implemented on
chip. As a result, it experiences the same thermal drift as the resistor ladder and
has no significant influence on the accuracy of the DIA converter. Besides the large
resistor values for high resolution implementations, this architecture has no guaranteed
monotonicity and is susceptible to glitches.

3.2.3 The R-2R based D/A converters

The large resistor values of the binary architecture can be reduced by using series
resistors. This results in the very frequently used R-2R D/A converter (fig.3.3). Al-
though the number of resistors has doubled in comparison to the binary structure, only
a single size resistor is necessary since the 2R is realised by a series combination of
two resistors with a value of R. The major advantages of this structure are its smaller
area and higher accuracy. However, the resistors often exhibit a non linear behaviour.
Furthermore, a time delay between the processing of the different bits adds to the
generation of glitches and distortion components.
26 CMOS D/A Converter Architectures

R R R

2R

83

R
13 12 11 10

liN >-_____- - - 0 VOUT

Figure 3.3: The R-2R DIA converter

3.3 The Capacitor DIA Converter

A simple architecture for the capacitor D/A converter is given in fig.3.4. The bottom
plates of the capacitors switch from the ground to the reference voltage according to
the digital input. If all the capacitors have the same value, a thermometer decoded
input is necessary. Similar to the resistor string DIA converter, a binary structure
can be implemented by adjusting the capacitor values. An example of a 3 bit charge
redistribution D/A converter is given in fig.3.5.
One of the causes that influences the non linearity error of a capacitor D/A con-
verter is the random mismatch caused by processing inaccuracies. This mismatch can
be expressed as :
t!. C t!. W t!. L t!. tox
-=-+---- (3.3)
C W L tox
with W the width, L the length and tox the oxide thickness of the capacitors. The
designer can minimise the mismatch by carefully choosing the dimensions of the ca-
pacitor. Besides the random errors, the non linearity error of the D/A converter is also
determined by the voltage dependence of the capacitance modelled by

C = CO+COiX[ V+COiX2V2+ ... (3.4)

with iX j the jth order voltage coefficient of the capacitor, and the non-linearity of the
junction capacitance of the switches connected to the output expressed as

(3.5)
3.4 The Current-Steering DIA Converter 27

Vout

s
~

Figure 3.4: The capacitor DIA converter

4C Vout

~
<pI

B2 ~ A C2
Vref ~I.~__-L________~______~ ~2

Figure 3.5: A 3 bit charge redistribution DIA converter

where Co is the zero bias capacitance, Vj is the voltage across the junction, <P is the
built-in potential and m j has a value that is typically between 0.3 and 0.5.
In recent years, this architecture has not been frequently used for telecommunica-
tion applications. However, [Fergu CICCOO, Khano AACDOl] presented two 10 bit
DIA converters that possess a high linearity. Overcoming the problem of their non
linear behaviour and the need for implementing a special driver for the DI A converter
load, this architecture lends itself for low power applications.
28 CMOS D/A Converter Architectures

Vsupply

Figure 3.6: The binary current steering D/A converter

:-~~ ~---f\, High Resolution CMOS Current-Steering DAC l ~~ -$- -1- - - - - - - -,

I $
81 21 I 81 $$ 21

$
82 41 : ,' ..........._ _ _ _ _S_P
....E...C_S_ _ _ _......_..... 82 $$$$ 41

\i·
I I

;_:~~_:'Y = ~~h 0-+

3
~~~~
W
@
Monotonicity

Powe' L_:_:_:_:____:
I I 6666 81

,, .
,-------------------~
,'.
,.......-....:l"---t
$
80

\ .. $
81 21
\
\.
~-------------------~

Figure 3.7: The advantages/disadvantages of the unary, binary and segmented current
steering D/A converter architecture
3.4 The Current-Steering DIA Converter 29

3.4 The Current-Steering DIA Converter

3.4.1 Introduction

In the current steering architecture (fig.3.6), the reference quantity is given by a cur-
rent. Also here different implementations are possible as will be discussed in the
following paragraphs. This architecture has the advantage of combining a small sili-
con area with a high update rate. The resolution of the D/A converter is determined
by the matching behaviour of the current sources. This issue is analysed in the next
chapter.

3.4.2 The Binary Implementation

In the binary implementation, every switch switches a current to the output that is
twice as large as that of the next less significant bit. The digital input code directly
controls these switches. The advantages of this architecture are its simplicity (since
no decoding logic is necessary) and the small required silicon area. However, this
structure does not always exhibit a monotone behaviour and suffers from a large DNL
and dynamic error. At the half scale transition, 2 N - 1 unit sources are switched on/off
and 2 N - 1 - 1 other independent sources are switched off/on. Assuming a normal
distribution for the unit current sources with a standard deviation a (I), this step has a
a(ll I) determined by:

a 2(1l I) = (2 N - 1)0'2(1) (3 .6)

=} a(ll I) = J2N=1 a~J) LSB
This sigma, a(ll I), is a good approximation for the DNL error.

3.4.3 The Unary Implementation

In the unary decoded architecture every unit current source is addressed separately.
The digital input code is converted to a thermometer code that controls the switches
(table 3.1). The advantages of this architecture are its good DNL error and the small
dynamic switching errors. Furthermore, the D/A converter has a guaranteed mono-
tone behaviour since only one additional current source has to be switched to the
output for one extra LSB. The major disadvantages of the unary decoded architecture
are the complexity, the area and the power consumption of the thermometer decoder.
Performing similar calculations as in eq(3.6) for the unary architecture leads to the
following result:
a(ll J) = a(l) LSB (3 .7)
I
30 CMOS D/A Converter Architectures

Decimal Binary Thermometer Code

bl b2 b3 dl d2 d3 d4 ds d6 d7
0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0 0 1
2 0 1 0 0 0 0 0 0 1 1
3 0 1 1 0 0 0 0 1 1 1
4 1 0 0 0 0 0 1 1 1 1
5 1 0 1 0 0 1 1 1 1 1
6 1 1 0 0 1 1 1 1 1 1
7 1 1 1 1 1 1 1 1 1 1

Table 3.1: The decimal, binary and thermometer code

This formula mathematically represents the idea behind the unary decoding. The er-
ror between two consecutive codes is just the deviation on the additional unity current
source. The DNL error was defined as the maximum deviation at a single LSB tran-
sition. For an N bit converter, this means that the DNL error is determined by the
maximum when taking 2N - 1 samples from a normal distribution with the sigma
defined in eq.(3.7).

3.4.4 The Segmented Implementation

To get the best of both worlds, most current-steering DfA converters are implemented
using a segmented architecture. In this case, the DfA converter is divided into two
sub-DfA converters: the B LSBs (least significant bits) are implemented using a bi-
nary architecture while the (N-B) MSBs (most significant bits) are implemented in a
unary way. In this architecture, a balance between good static and dynamic specifi-
cations versus a reasonable decoder power, area and complexity can be found. This
is illustrated in fig .3.7. Since the segmented architecture is a mixture of the previous
two architectures, the result for the most critical transition is of the same form.

a(~ l) = -/2 8 + 1 - I a(I) LSB (3.8)

I
Note that the formula in eq.(3.8) for the segmented architecture is a general formula
that is valid for the binary (B=N-l) and the unary implementation (B=O).

3.5 Conclusions
In this chapter, an overview has been given of the different DfA converter architec-
tures. In the remainder of this work, the current steering topology has been studied.
3.5 Conclusions 31

The advantages and disadvantages of the unary, binary and segmented architecture
have been analysed as to optimise the D/A converter's performance.
Chapter 4

Static Behaviour of Current Steering

DIA converters

4.1 Introduction

As has been discussed in the previous chapter, the current steering topology is cur-
rently the preferred architecture for telecommunication applications requiring a high
update rate and/or a high accuracy. Designing such a DI A converter requires a tho-
rough understanding of both the static and the dynamic behaviour of this device.
In this chapter, the emphasis will be put on the static performance of the current
steering DI A converter. This performance is determined by the matching behaviour of
the current source transistors. Since no two transistors behave exactly the same due
to technological variations introduced during processing, it is important to know the
impact of this phenomenon on the yield and the performance of the circuit. This topic
will be discussed in the first part of this chapter. Apart from the process variations
which generate random errors, the current sources in the array are also influenced by
systematic errors that are introduced by thermal, electrical and process gradients. The
second part of this chapter discusses the errors generated by these gradients and will
go into more detail on how to solve this problem.

4.2 Modelling of the random errors

4.2.1 Introduction

Due to the mismatch of the current source transistors, the INL performance of dif-
ferent D/A converters made in the same process technology will vary randomly. It is
34 Static Behaviour of Current Steering DfA converters

therefore important to be able to predict this performance within certain boundaries.

For this purpose, the concept of the DfA converter's INL_yield will be introduced.
This yield figure is defined as the percentage of functional DfA converters with an
INL performance smaller than the specification of half a LSB (least significant bit).
In this section, several analytical expressions for the INL_yield found in open liter-
ature will be discussed and evaluated. Also a new model will be derived that is easy to
use and gives the designer an accurate indication on the required matching behaviour
of the current sources as a function of the resolution of the DfA converter. All the
models - including the new one- start from the assumption that the unit current source
errors have a Gaussian nature.

4.2.2 Lakshmikumar Approach

A first suggestion to analytically determine the yield of a DfA converter as a function

of the matching parameters of the current source transistors was made in [Laksh JSSC86]:

(4.1)

with

• N = the number of bits,

• Zi = the mean normalised output at code i,

• a }l) = the unit current relative standard deviation.

However, this formula is based on the assumption that there exists no correlation
between the outputs of a current-steering DfA converter. The INLyield can then be
obtained by multiplying the probabilities that each output has an error smaller than
half an LSB. To demonstrate that this assumption is not correct the following example
is given. The outputs corresponding with the digital input word 01100 and 01101 are
strongly correlated since they are both implemented using the same current sources.
Using eq.(4.1) to estimate the yield will impose too severe constraints in terms of
matching accuracy on the current sources leading to an oversizing of these transistors.
In [Laksh JSSC88], an adjustment of this model was presented. Here the MSB (most
significant bit) transition is considered to be the most critical one since in a binary
implementation this transition has the largest probability of generating an output error.
4.2 Modelling of the random errors 35

Furthermore, the DfA converter's outputs before and after the MSB transition are not
correlated. The yield can then be described as :

INL yield = n
2N -

i=2N- l_l
1
Qi
erf(-)
.j2
(4.2)

with

• N = the number of bits,

• Z; = the mean normalised output at code i,

• °Y) = the unit current relative standard deviation.

FigA.l shows a comparison between the Monte Carlo simulations and the formu-
las derived in this section.The yield estimation given in eq.( 4.2) is too optimistic since
the influence of only two outputs is taken into account while the errors generated by
the other outputs are being ignored.
Comparing the two approaches, one can conclude that designing a chip using the
first approach can lead to a large but nearly fault-free DfA converter while using the
second approach results in a compact but low yield circuit. The correct yield estima-
tion is situated somewhere in between these two results.

4.2.3 Monte Carlo Approach

To obtain an accurate estimation of the INLyield, the Monte Carlo simulation has
been considered to be the best alternative [Conro JSSC88]. A lot of recent publica-
tions refer to this method to do their accuracy analysis. The following procedure can
be used. Each of the (2 N - 1) current sources has a random value that has been de-
rived from a Gaussian distribution with a mean value I LSB and a standard deviation
(J (I). For every digital code the output current of the DfA converter is calculated and
compared to the ideal value. If the difference is larger than half an LSB - even for
only one digital code - the DfA converter is regarded as not functional and is rejected.
For every (J(I) this procedure is repeated a large number of times ( > 100) to obtain
reliable results. The INLyield is then given by the ratio of the number of functional
DfA converters (I N L < 1/2LSB) to the total number of try- outs. In this way the
relation between the unit current standard deviation and the INLyield is determined.
However, to obtain the results depicted in figA.l, a large amount of CPU time is nec-
essary. Running a Monte Carlo simulation for a high resolution DfA converter takes
several hours which is a major drawback.
36 Static Behaviour of Current Steering DfA converters

100

90

80

70

60
~
'tI
Gi 50
>.
I
..J
~ 40

30

20

10

0
0
sigma(J)/J

Figure 4.1: Monte Carlo simulations (0) of the IN L_yield compared to the results of
the formulas in eq.4.1 (.) and eq.4.2 (0) for a 10 bit DIA converter

4.2.4 A new INL_yield Formula

4.2.4.1 Introduction

The models presented in the previous section either lack accuracy but are fast or are
accurate but very time consuming. The model that will be derived in this section
is both accurate and fast. The INLyield calculated with this formula shows a good
agreement with the Monte Carlo simulations and can be thousands of times faster for
high resolutions (table 4.1).

4.2.4.2 Theory

The idea will be elaborated for an arbitrary number of bits N. For the simplicity of
notation the following symbols are defined:

Definition 1: X(j) is the sum of j non-correlated unity current sources

Definition 2: Y(j) is the difference between X(j) and the sum of the ideal current
sources
4.2 Modelling of the random errors 37

C*o(Y(2 '»
.
·112 LSB 1/2LSB

Figure 4.2: The shaded area determines the probability p(Y(2N) < 0.5LSB)

Every current source has a normal distribution with a mean value Imean and a standard
deviation a (I).This implies that both XG) and YG) also have a normal distribution
with the following properties eq.(4.3):

Xmean (})= j * Imean Y mean (}) = 0

a(X(}) = J(j) * a(I) a(Y(}) = a(X(}) (4.3)

The exact possibility that an INL error will occur is based on the fact that each
current source generates an error and is given by the following sum of probabilities:

P(INLerror) = (4.4)

P(IY(l)1 2: 0.5&IY(2)1 < 0.5&··· &IY(2N - 1)1 < 0.5) +

P(IY(2)1 2: 0.5&··· &IY(2 N - 1)1 < 0.5) + ... +
P(IY(2 N )1 2: 0.5)

However, this equation is not transparant and therefore not suitable for practical
use. The basic idea behind the new theory is based on the fact that if at any point
IY(})I reaches half an LSB, there exists a 50% chance that the error increases and
50% chance that it decreases again since a normal distribution with mean value zero
is used. Extending this line of thought, one can say that if an INL error occurs - when
passing through all the possible codes generated by the (2 N - 1) digital input words -
there is a 50% chance that this error still exists for the (fictive) code 2N. This idea can
be expressed as:
38 Static Behaviour of Current Steering DIA converters

100

90

80

70
......
~
L 60
'C *
4i 50 .*
":;'
I :*
..J 40 ... *
~
30 *'"
*
20 *
*
10 *.
*
0
0.5 1~ 2 25 3 35
coefficient C

Figure 4.3: INLyield as a function of the coefficient C

P(IY(2N)1 :::: 0.5) = P(3j E [l..(2 N - ~)] : IY(j)1 :::: 0.5]) (4.5)

At this point the INLyield of the D/A converter can be integrated in the calculation
since there exists an obvious relation between the yield and the possibility of an INL
error to occur:

INLyield = 1 - P(3j E [1..(2 N -1)] : IY(})I :::: 0.5]) (4.6)

Combining eq.(4.5) and eq.(4.6):

1- INLyield
P(IY(2 N )1 :::: 0.5) = 2 (4.7)

From eq.(4.7), the possibility that no INL error occurs at code 2N can be easily derived
and equals:

P(IY(2N)1 < 0.5) = 0.5 + _IN_L-=_y_i_el_d (4.8)

2

At this point, the INLyield is no longer described as a sum of probabilities (eq.(4.4))

4.2 Modelling of the random errors 39

but as the possibility that a sample from a normal distribution is smaller than half an
LSB. This requirement can be written as:

1 1/ 2LSB

-1/2LSB
p(Y(2N»dY(2N) = lCM p(Y(2N»dY(2N) = 0.5 + IN L -y ield
-CM 2
(4.9)

with p(Y(2N» the probability density function (fig.4.2). Eq.(4.9) directly gives the
following result:

(4.10)

with:

.
C = lnvJlorm( _ x,x)
(05
. + INLyield)
2

The invJlorm(-x,x) is the inverse function of the normal cumulative function in-
tegrated from -x to x. In appendix 1, a table is given determining the value of C as a
function of either the INLyield or as a function of the value of (0.5 + IN Lteld ). It

should be further noted that if the normal cumulative function integrates from minus
infinity to x the expression for C slightly alters and is given by:

C .
= lnVJlOrm(_oo,x) (075
. + INLyield)
4

Since Y(2N) has a normal distribution with a standard deviation J2N a (I) (eq.(4.3»,
the relation existing between the INL_yield of the current steering DfA converter
and the matching properties of the current source transistors can be deduced from
eq.(4.1O).

a(l)
(4.11)
I 2J2NC

Fig.4.3 shows the INL_yield of the DfA converter as a function of the coefficient C.
In fig.4.4 the INLyield of a lO-bit DfA converter calculated using the new formula
in eq.(4.11) and simulated using the Monte Carlo approach are depicted. From this
figure, it can be concluded that the formula is in good agreement with the Monte Carlo
simulations.

To gain more insight in eq.(4.11), the unit current standard deviation is plotted in
logarithmic scale versus the resolution of the DfA converter (fig.4.S). As can be seen
from this figure, the relationship is characterised by straight lines since
40 Static Behaviour of Current Steering D/A converters

*
cf2. 90
"0 *
*
..
Qi
~ *
Z 85
* *
*
*
80
** *

0.2 0.4 0.6 0.8 1.2 1.4

sigma(I)/(I) [%]

Figure 4.4: Comparison between the Monte-Carlo simulations and the new formula
for a JO-bit DIA converter

(4.12)

with
log2
A
2
B -log2 -logC

One can easily conclude from fig.4 .5 that for the design of a high accuracy current
steering CMOS D/A converter the matching parameters playa significant role. A
small deviation of the required a(I)/I can lead to severe yield degradation.
The time to create a figure like fig.4.5 using Monte Carlo simulations in MATLAB
is given in table 4.1, where the results for an INL_yield from 100% to 10% for a current
steering D/A converter with different resolutions can be found . For all the simulations
twenty values for the relative unit current standard deviation were taken. This can be
understood as follows. In a first coarse approximation, a simulation using 10 values
for a(I)/I -that span a wide range- is run. From the obtained result, the interval for the
a(I)/I that obtain a high INL_yield can be specified. In this interval another 10 points
are simulated. Creating fig.4.5 using the new formula takes only a few minutes. The
time to write the short MATLAB program is so to speak the most time consuming. It
is also worth noting that the time necessary to calculate the INL_ yield is independent
4.2 Modelling of the random errors 41

10-',.-------,-------,-------,---------,

6 8 10 12 14

number of bits

Figure 4.5: The unit current relative standard deviation as afunction of the resolution
of the DIA converter for a yield of99.7% (0), of50% (0) and of 10% (*)

resolution Monte Carlo formula

8 bit 0.13 hours seconds
10 bit 0.69 hours seconds
12 bit 5.31 hours seconds
14 bit 108.57 hours seconds

Table 4.1: Comparison between the CPU time consumption of the Monte Carlo simu-
lations and the new formula

on the resolution of the DI A converter while the time consumption of the Monte Carlo
simulations "explodes" with an increasing D/A converter's accuracy.

4.2.5 Conclusion

In this section, the impact of random errors caused by the matching behaviour of the
current source transistors on the yield of the DIA converter has been discussed. A
new formula has been derived that provides a clear insight on this issue in a fast and
42 Static Behaviour of Current Steering DfA converters

accurate way. In chapter 6, that discusses the design flow for a current steering DfA
converter, the usefulness of this formula will become clear during the dimensioning
of the current source transistors. It will allow to determine the area of the unit cur-
rent source transistor in such a way as to optimise the static performance of the D/A
converter and to minimise its silicon area consumption.

4.3 Modelling of the systematic errors

4.3.1 Possible causes

Apart from the random errors, the static performance of the D/A converter is deter-
mined by the following systematic errors:

• Although the transistor mismatch effect of the current sources has already been
taken into account during the sizing of these transistors, it can still have a ne-
gative influence on the static performance of the DIA converter due to the "edge
effect" [Wong ICMTS95] which states that the mismatch behaviour of a tran-
sistor is dependent upon its surroundings. To avoid this error, the current source
array has to be expanded by inserting dummy rows and columns as to provide
identical surroundings for all the active current source transistors.

• The voltage drop along the ground line will slightly change the output current
of the different current source transistors placed on the same row. This leads to
an integral non linearity error that is given by [Miki JSSC86] :

(4.13)

where gm is the derivative of the full scale current to the current source bias
voltage, R is the total resistance of the ground line and f is a factor depending on
the used switching scheme. If all the current sources are switched sequentially
from the left to the right, the value for f equals 9. This error can be reduced by
either using sufficiently wide power supply lines (reducing the resistance R) or
by using a special switching scheme (increasing the factor f).

• If the resolution of the DfA converter increases by a single bit, the number of
current sources in the current source array doubles. The area occupied by a
single unity current source also doubles because of the random matching con-
straint. This leads to a four-times area increase for the current source array for
each additional bit. For DIA converters with a resolution of 10 bit and higher,
4.3 Modelling of the systematic errors 43

the dimensions of the current source array become so large that process- and
temperature gradients have to be considered. The non-linearity errors intro-
duced by these gradients can be (partially) compensated by the introduction of a
special switching scheme. How this is implemented is discussed in more detail
in the next section.

4.3.2 Switching Schemes

4.3.2.1 Introduction

If the error contributions of the current sources are totally random and uncorrelated,
the INLyield of the D/A converter dictates the minimal requirement for the matching
precision of the current sources as is indicated in the previous paragraph. The random
error can then be kept within the specified boundaries (l N L < 0.5LS B) by adjusting
the active area. This implies that in order to guarantee a good static performance, the
systematic errors introduced by linear and/or symmetrical gradients have to be com-
pensated in order to keep the random errors dominant. This is done by using optimised
switching schemes for the current sources. Several switching schemes have been pre-
sented in literature [Miki JSSC86, Nakam JSSC91, Marqu ISSCC98, VdPla JSSC99,
VdBos ISSCC01]. These switching schemes will be discussed in more detail in the
next paragraphs. First, a short introduction on the basic principles of gradients will be
given.

4.3.2.2 The Gradient Error Distribution

It is generally assumed that the error distribution introduced by the gradients can be
modelled by a superposition of both a linear and a quadratic component [Cong TCASII].
The linear gradient error can be expressed as :

8t(X , y) = at * cosiJ * x + at * siniJ * y (4.14)

with iJ E [0, 360°] is the angle of the gradient, at represents the slope of the gradient
and (x,y) determines the position of the current source transistor. This type of gradient
can be caused by f.i. a variation of the oxide thickness over the wafer or by the voltage
drop along the ground line of the current source transistors [Miki JSSC86].
The quadratic gradient error can be expressed as :

with bo , as being technological parameters and (x,y) the position ofthe current sources.
44 Static Behaviour of Current Steering DIA converters

83,82,81,80)
= (0,1,1,0) -1 column decoder
I
1
I
1 0 0

I- 1
...
(1)
"C I- 1
0
(J
(1)
"C I- 0
3:
...0 I- 0
I- 0

Figure 4.6: The row and column decoding principle; every cell of the matrix contains
some decoding logic, a synchronisation block, a switch and the current source

This expression has been derived under the assumption that the symmetrical gra-
dient is identical for both the x and the y dimension and that the current source array
is located in the center of the die [Cong TCASII]. Examples of symmetrical gradients
are f.i. the gradients introduced by temperature and by die stress [Basto TSM97].
Since the actual error distribution is a superposition of both the linear and the
symmetrical gradient error, it can be expressed as :

e(X, y) = el(X, y) + es(X, y) (4.15)

4.3.2.3 The sequential, conventional and hierarchical symmetrical switching

schemes

The switching schemes that will be discussed in the next two subsections are deter-
mined by the implementation of the thermometer decoder that transforms the digital
input word in a decimal value. FigA.6 shows the schematic of a row and a column
4.3 Modelling of the systematic errors 45

iii
(J
.;: c;
Q) 0
E:O::
E~
I E

I
> .-
1/1':::
'C .!!l
c;'C
III ...
'C 2
CII ...
'C CII
f!
E
Cl

11 12 13 14 15678910111213141516 sequential scheme

15131197 5 13 11 12 ! 4 1 6 810121416 conventional symmetrical

scheme

1410 6 [2Ti] 5 9 131511 7 [314] 8 1216 hierarchical symmetrica l

scheme (type A)

15 11 7 [3IiJ 5 9 13 14 10 6 [214] 8 12 16 hierarchical symmetrical

scheme (type B)

Figure 4.7: The sequential, the conventional symmetrical and the hierarchical sym-
metrical switching scheme

decoder [Miki JSSC86]. The working principle is based on comparing the generated
row signals of two adjacent rows as follows:

• If both signals are high, the entire row of current sources is turned on .

• If both signals have different values, only the current sources that have a high
column signal are turned on.

The above described principle can be implemented by using a simple digital logic
block, leading to a high speed decoder circuit with a low power consumption. Three
different switching schemes have been presented in [Miki JSSC86, Nakam JSSC91]
using this decoder logic: the sequential, the conventional symmetrical and the hierar-
chical symmetrical scheme. A schematic representation of these switching sequences
is given in fig.4.7.

In the sequential switching scheme, the current sources in a given row are turned
on sequentially from the left to the right. The effect of this scheme on the integral non-
linearity error is given in fig.4.8 and fig.4.9. As can be clearly seen from these figures,
46 Static Behaviour of Current Steering DIA converters

Switching Sequence Graded Error Symmetrical Error

E 52 E 52
sequential "8 * 5-1 16 * 5-2
E E 52
conventional symmetrical 2" "8 * 5-2
E
hierarchical symmetrical(A) f*(1+5~1) 2"
E
hierarchical symmetrical(B) 2" E

Table 4.2: The INL errors of the three types of switching schemes [Nakam JSSC91 J S
denotes the number of current sources in a row of the current source array and E de-
notes the peak-to-peak error in both the graded and the symmetrical error distribution

the sequential switching sequence causes large linearity errors due to the accumulation
of both graded and symmetrical errors.
In the conventional symmetrical switching scheme, the current sources are turned
on symmetrically around the center of the row. By using this scheme, the graded
errors are cancelled at every two increments of the digital input (fig.4.8) but the errors
generated by a symmetrical gradient will accumulate as is indicated in fig.4.9.
In the hierarchical symmetrical switching scheme, the current sources are turned
on around the first and the third quarter of the current source row. Two different
schemes are possible, depending on which error is cancelled first. Using switching
scheme A, the symmetrical error generated by current source I is cancelled by current
source 2 while the graded error caused by the current source pair (1,2) is cancelled by
the current source pair (3,4). In switching scheme B, the errors caused by the linear
gradient are cancelled out at current source level while the symmetrical errors are can-
celled at the current source pair level. Comparing the linearity error of both switching
schemes leads to the following result. In type A, the integral non-linearity error is ap-
proximately the same for both the graded and the symmetrical error distribution while
in type B, the integral non-linearity error caused by the symmetrical error distribution
is twice as large as the one caused by the graded error distribution (fig.4.8 and fig.4.9).
Table 4.2 gives an overview of the non-linearity errors of the three types of
switching sequences where S denotes the number of current sources in a row of the
current source array and E denotes the peak-to-peak error in both the graded and the
symmetrical error distribution.
As a conclusion, it can be stated that if a I-dimensional row and column decoder
is used, it is best to implement the hierarchical symmetrical switching scheme type A
since this scheme avoids the accumulation of linear and symmetrical errors resulting
in a small integral non-linearity error.
4.3 Modelling of the systematic errors 47

linear gradient

-0.1

-0.15
,
....
0....
....
-0.2
•,,
Q) -0.25 ,, , •• sequential
,
---l
Z
-0.3 , " . ' conv.symm .

, ..... hier. typeA

-?' hier. typeS
-0.35

-0.4
- ,
"
"
"
,"
,"
,I

....
"

-0.45 ' .,.'

-'" '4tt
''',
", # ' "
-0.5
0 2 4 6 8 10 12 14 16
input code

Figure 4.8: The INL error caused by a linear gradient for the sequential, the conven-
tional symmetrical and the hierarchical symmetrical (type A and type B) switching
schemes (E=O.4)

4.3.2.4 Switching Schemes for the 2-D Rowand Column Decoding Principle

In the previous paragraph, the errors generated by the systematic gradients are only
minimised in one dimension, namely the x-dimension. It is possible to adjust the
decoder as to implement a hierarchical scheme in both the x and the y-direction. Al-
though this implementation improves the overall linearity of the OJ A converter, it is
still not optimal.
In [Marqu ISSCC98] a switching scheme has been presented that preserves the
simple row and column decoder but further reduces the INL error. The presented
OJA converter has a 6-2-4 segmented architecture where the 6 most significant bits
are implemented using a row and column decoder. Instead of using only one current
source, the current is generated by four current sources that are placed symmetrically
around the center of the array. Each current source is controlled by a separate decoder.
This implies that instead of using only one decoder, four decoders have been placed on
the chip. The OJA converter is actually built up out of four sub OJ A converter blocks.
By implementing the conventional symmetrical switching scheme in both the x and
y direction, the linear errors have been completely cancelled out due to the spatial
48 Static Behaviour of Current Steering DfA converters

symmetrical gradient
:.: r - - - . - - - - . - - ,,-",--=,,c...,, '.,- ,, -" ,, 11;-,:,-,.=
,- , , -, , -" -:-i , , -",-, , -" . ' "-,-,,-
, ,-",-,, ' . - - - , - - - - - - - ,

0.4 .,•••.•'" #"\

. # ,
# . '~
0.3 # ~ ,... ~ -~,

....
e....
Q)
0.2 " ,.
..
#
~",
" . " "
' / ~~:

....J
0.1 ,,:,"- . .
Z

#
/
#. , .. " sequential
-0.1 #.
".' cony. symm.
#. + hier. typeA
-0.2 ",..# ' -?' hier. typeS

,,'"
-0.3 L--_ _-'---_----'-'*-_
" _--'-_ _---'--_ _--L_ _----'_ _ _L - - _ - - '
o 2 4 6 8 10 12 14 16
input code

Figure 4,9: The INL error caused by a symmetrical gradient for the sequential,
the conventional symmetrical and the hierarchical symmetrical (type A and type B)
switching schemes (£=0.4)

symmetry while the symmetrical errors have been reduced significantly.

4.3.2.5 Decoder Independent 2-D Centroid Switching Schemes

In most DfA converters implemented using a row and column decoder, the switches
and the current source transistors are part of the same matrix. However, to minimise
the coupling between the 'digital' switches and the 'analog' current sources and at the
same time increase the flexibility of the switching schemes, two separate matrices for
the current source and the switch transistors are used. In this way, the decoder does
no longer determine the complexity of the switching scheme. This complexity is now
dictated by the occupied silicon area for the interconnections (which can be done on
top of the current source transistors), the used technology (especially the number of
metal layers) and the creativity of the layout engineer.
Most current steering DfA converters have a segmented architecture implying that
the unary current source in most cases equals a number of times the unit current source
(= LSB current). It is therefore possible to divide this unary current source into a
number of "sub"-current sources. For the 12 bit implementation [VdBos CICC98],
4.3 Modelling of the systematic errors 49

16 sub- current sources have been used that were switched on simultaneously around
the center of each quadrant (double centroid switching scheme). In the 12 bit D/A
converter described in [VdBos ISSCCOl], the current source array was divided in 16
blocks and the sub-current sources were placed symmetrically around the center of
each block leading to an INL error smaller than 0.3 LSB. This switching scheme is
better known as the triple centroid switching scheme. To indicate the possibilities
of defining alternative switching schemes, the example of a 14 bit D/A converter is
given in figA.I0. This figure shows a comparison between the switching scheme
presented by [Miki JSSC86] and the Q2 Random Walk switching scheme presented by
[VdPla JSSC99] for a 14 bit D/A converter. To obtain such a high resolution without
the use of any tuning or trimming, the systematic errors have to be made as small as
possible. In this case, information regarding the gradients had been extracted from
an earlier test chip. A Q2 random walk switching scheme has been implemented.
The resulting INL error for this switching scheme is about ten times smaller than for
the classical switching scheme presented by Miki , which resulted in the first CMOS
D/A converter with an intrinsic accuracy of 14 bit. More details on the here discussed
switching schemes can be found in chapter 7.

4.3.2.6 The Analytical Optimisation of a Switching Scheme

Up until now, deriving the optimal switching sequence has been done in a heuristic
manner [Miki JSSC86, Nakam JSSC91, Marqu ISSCC98]. However, trying to solve
this optimisation problem analytically can have several advantages. The problem of
determining the switching scheme on sight is converted in solving a set of analytical
equations that describe the gradients. A first advantage of this approach is obvious.
This method allows to find a solution for every type of gradient by simply modifying
and/or adding an extra equation. Another advantage is that solving this optimisation
problem, a (near) optimal switching sequence will be found that is in most cases better
than the heuristically derived one. For the case of the Q2 random walk switching
scheme of the 14 bit D/A converter [VdPla JSSC99] which has been determined using
an optimisation algorithm which was heuristically constrained, it has been shown in
[Cong TCASII] that this switching scheme is an optimal solution for the minimisation
of the quadratic gradient errors but not for the minimisation of the linear graded errors.
In the remainder of this paragraph, the mathematical ideas behind the optimisation
problem will be highlighted.

In order to find the optimal switching sequence, a lower bound for the INL error of
the D/A converter has to be determined. This is done by taking the following elements
into account :
50 Static Behaviour of Current Steering DIA converters

0 2 Classical Switching Scheme

0.5

iii'
~
....... 0
..J
Z
0-0.5
ct
C

-1

_1 .5L..----........----"'---------'--------J
o 4095 8191 12287 16383
DAC Input Code

(a) Simulation of the INL for the Q2 classical switching scheme

0 2 Random Walk

0.5

iii'
CJ)
..J
.......
..J
~
~-0.5
C

-1

4095 8191 12287 16383

DAC Input Code

(b) Simulation of the INL for the Q 2 Random Walk switching scheme

Figure 4.10: A comparison between the switching scheme presented by

[Miki JSSC86] and the Q2 Random Walk switching scheme [VdPla JSSC99]
4.4 Conclusion 51

• The INL error of a DIA converter is by definition equal to :

(4.16)

where IN Lm is the minimal value and IN L M is the maximal value of the INL
characteristic of the DI A converter.

M * 100 =
• If the percentual errors of the different current sources are given [1Ideal
F;, i = 1 ... 2N - 1], one can state that the difference between the upper and the
lower limit for the INL characteristic has to be larger than the maximum current
source error.
(4.17)

• The INL error of the D/A converter will be minimal if IN Lm and IN LM are
located symmetrically around zero.

INL = INL m = INLM (4.18)

Combining these three elements results in an absolute lower bound on the INL error:

I NL Fmax (4.19)
LB = -2-

Once the lower bound of the INL error is given, the (near) optimal switching se-
quence can be determined by using an INL bounded algorithm. Since it is not the
intention of the author to go deeper into the computing algorithms for solving the
optimisation problem, the reader is referred to [Cong TCASII] for more information.
It should be noted that some gradient information has to be available to tackle the
switching scheme optimisation problem. This information can be extracted from a
test chip but this method significantly increases the design time of the DIA converter
circuit [VdPla JSSC99]. When this is not allowed, the heuristically derived schemes
are at the moment still the best alternative. If extra silicon area and power consumption
are not a problem, calibration circuits can be implemented that counteract the influence
of the gradients (and even of the random mismatch errors) [Bugej JSSCCOO].

4.4 Conclusion

A new INLyield formula has been derived that in an accurate way describes the in-
fluence of the mismatch behaviour of the current sources on the yield of the DI A
converter. In the second part of this chapter, the impact of the systematic errors on
the static performance of a current steering DI A converter has been discussed. Im-
plementing special switching schemes leads to a minimisation of these errors in such
52 Static Behaviour of Current Steering DfA converters

a way that the random errors become dominant. This is important since the derived
yield formula will remain valid and can be used for determining the dimensions of the
current source transistor.
Chapter 5

Dynamic Behaviour of Current

Steering DIA Converters

5.1 Introduction

Where in the previous chapter, the static behaviour of the current steering D/A con-
verter has been discussed, this chapter will focus on the dynamic performance of these
architectures.
Recent papers [Marqu ISSCC98, Bavel CICC98, VdBos CICC98] reveal the pro-
blem that high speed Nyquist D/A converters are difficult to design. Analysis of the
frequency domain performance of these architectures reveals that second and third
order harmonic distortions limit the spurious free output signal bandwidth. This is
caused by a combination of different factors that each have to be solved. The first
part of this chapter will identify these performance degrading factors and some design
guidelines will be proposed that solve the problems such as imperfect synchronisation
of the switch control signals, the digital signal feedthrough through the gate-drain
capacitance of the switch transistors and the drain voltage variation of the current
source transistor.
The importance of the output impedance of the DIA converter will be discussed in
the remainder of this chapter. A formula will be derived for the spurious free dynamic
range as a function of the output impedance that allows the designer to calculate the
minimal impedance that is required to obtain a certain frequency performance. For
high resolution D/A converters, this implies that the use of cascoded structures be-
comes mandatory. These architectures will be discussed in detail in the final section
of this chapter.
54 Dynamic Behaviour of Current Steering DIA Converters

~
~
rL ctl3 ,,<
"

- - - -L -__________L -_______ V~

control signals [VI output voltage M

ctl1
(a)
----/'",,----
ctl2
3
2
1

ctl1
3
(b) 2

ctl2

ctl3

X
3
(c) 2
1
ctl2
ctl110w
o

Figure 5.1: (a) impeifect synchronisation of the switch control signals, (b) capacitive
feedthrough, (c) drain voltage variation of the current source

5.2 Major contributors

It has been generally accepted that the dynamic performance of a current steering DIA
converter is mainly determined by either timing errors, by capacitive feedthrough from
the digital control signals to the output node or by the voltage stability of the drain
node of the current source transistors (fig.S.1). Different solutions for these problems
can be found in open literature at the design level. However, in this paragraph a fourth
element will be introduced that significantly degrades the dynamic performance of the
DIA converter, namely the frequency dependency of its output impedance. These four
factors will now be discussed in more detail based on the circuit schematics of a basic
current cell block (fig.S.2.a).
5.2 Major contributors 55

5.2.1 The Imperfect Synchronisation of the Control Signals of the

Switches

If the control signals of both switches (Mswa and M swb) are not exactly matched in
time, a glitch error will be directly visible at the output of the D/ A converter (fig.S.I .a).
This problem can be solved by placing a synchronisation block immediately in front
of the switch transistors. In this way, any delay introduced by the digital decoding
logic is cancelled out and the timing error is minimised. However, one should keep
in mind that at the layout level, the implementation of this circuit has no use unless
identical connections between the synchronising circuit and the switching transistors
are drawn.

5.2.2 The Digital Signal Feedthrough via the CGD of the Switch
Transistors

The gate-drain capacitances of the switch transistors M swa and M swb form a feedthrough
path that allows the digital control signals to have a direct impact on the output of the
D/A converter (fig.S.1.b). The glitch energy error that is generated in this way can be
significantly lowered by the use of a reduced voltage swing at the input of the switches
or it can be minimised by placing a cascode transistor on top of the switch transistors
[Marqu ISSCC98] . Since the introduction of these cascode transistors (that also have
to be switched on/off) does not solve the problem entirely and leads to a higher area
consumption and a distortion of the fully symmetrical operating principle of the ba-
sic current cell, recent D/A converter designs opt for the first solution since in some
designs the implementation of a reduced voltage swing can be done by the same syn-
chronisation circuit used to solve the problem described in the previous section (S .2.1).

5.2.3 The Voltage Variation at the Drain of the Current Source

Transistors

If the crossing point of the switch control signals is situated at exactly the VDDivss
value, the following problem will occur. A time interval exists in which both switch
transistors are simultaneously in the off-state. Since the current source transistor Mcs
is still delivering current, the capacitance Co at its drain node will discharge. At
the moment one of the switches starts conducting, an extra amount of current will
flow through these transistors as to restore the DC voltage at that node. This will
result in a glitch error at the output of the D/ A converter leading to a deterioration
of the dynamic performance (fig.5.l.c). This problem can be solved by the use of a
special switch driver circuit [Kohno CICC9S]. However, also for this building block
56 Dynamic Behaviour of Current Steering DIA Converters

Zimp [ohm]
1

out 9 msw r Osw roes

I 21t rOes Co

1 9msw
21tCo

rosw
I

frequency [Hz]

Figure 5.2: (a) The basic current cell block (capacitance Co is the parasitic capaci-
tance), (b) The impedance seen in the drain of the switch transistor versus frequency

a trend exists towards an integration with the synchronisation circuit [Bavel CICC98,
VdBos CICC98].

5.2.4 The Output Impedance

Since the first three problems causing a degradation of the dynamic performance of a
current steering DIA converter can be solved by the use of one well designed and care-
fully layouted synchronised switch driver, the update rate of these devices is mainly
determined by the design of the digital decoder. Therefore mixed-signal designers
are pushing their designs to higher resolutions. Higher resolutions however do not
only complicate the design of the decoder, it also introduces a fourth important fac-
tor that influences the dynamic performance of the D/A converter, namely the output
impedance.
As is generally known, the output resistance Rimp (fig.5.2) of each current cell has
to be made large so that its influence on the INL (integral non-linearity) specification
of the DIA converter is negligible. The relation between this output resistance and the
achievable INL specification is given by [Razavi]:

f uni t Rloai N 2
fNL=----- (5.1)
4Rimp

with Rload the load resistor, funi! the LSB current and N the total number of unit
current sources. In most cases, the cascode configuration of the switch and the cur-
rent source transistors achieves the INL specification. However, this is only true
5.2 Major contributors 57

over a limited frequency bandwidth as can be concluded from the following calcu-
lation. Fig.S.2.a shows the schematic of the unit current cell of a current steering DI A
converter where the parasitic capacitance Co is indicated. The impedance Zimp (the
impedance seen from the output node into the drain of the switch transistor M swb) can
be calculated (fig.S.2.b) and equals:

Zimp ( 1 + jWColgmsw)
= rosw(l + gmsw(rocsIICo» = rosw(l + gmswrOcs). (5.2)
1 + }wCorocs

This formula indicates that the impedance has a pole and a zero at the following fre-
quencies:

1 gmsw
pole = - - - - and zero = - - (5.3)
2nCOrOes 2n Co

The possibility to shift this pole and zero to a higher frequency is determined by
the flexibility in adjusting the following four parameters: the output resistance of
the current source transistor rOes and the switch transistor ro sw , the transconductance
of the switch gmsw and the capacitance Co. According to eq.(S.3) the pole can be
shifted towards a higher frequency by minimising the output resistance rOes of the
current source transistor. However, the value of this resistance can not be freely ad-
justed since the gate-length L of this transistor is dictated by matching considerations
[Pelgr JSSC89] and the current JDS is determined by the full scale output signal. Since
the current through the switches equals the current through the current source transis-
tors and the gate-length L of the switch transistor is chosen to be minimal for speed
reasons, nothing can be gained by the output resistance rosw of these transistors. Also
the transconductance gmsw is largely determined since the gate overdrive voltage of
the switches is the result of an optimisation process between the area occupied by the
current sources and the useful utilisation of the limited power supply range of the DIA
converter [VdBos ISDDMI98].
As can be concluded from the previous paragraph, the transistor parameters can
be hardly adjusted to improve the negative impact generated by the pole of the output
impedance. A whole different story applies to the capacitance Co. Considering that
for one extra bit of accuracy, not only the active area increases by a factor of four but
also the area occupied by the decoding logic and the interconnections scales up, it is
easy to understand that the total area needed for high resolution D/A converters (> 10
bit) becomes in the order of magnitude of several square millimeters. To reduce the
dimensions of the current source matrix (which is beneficial for distance matching)
and to minimise the coupling between the digital and the sensitive analog part of the
chip, all decoding logic (including the switching transistors) and their interconnections
58 Dynamic Behaviour of Current Steering D/A Converters

are placed outside the current source array. Although this reduces the area occupied
by the current source matrix considerably, it is not enough to ignore the influence of
for example the parabolic gradients. To minimise the systematic errors introduced
by these gradients special switching schemes have been devised as described in the
previous chapter. These schemes introduce in almost all cases extra routing wires and
thus an extra interconnect capacitance Co which is independent of the current source
and switch transistor dimensions and is totally determined by the layout. The value
for this interconnect capacitance can be several orders of magnitude larger than the
intrinsic value of Co.

5.3 SFDR-Bandwidth limitations

At this point, the frequency dependency of the output impedance has been discussed
qualitatively but the question remains if this impedance has a significant effect on
the dynamic performance of the DI A converter. In this paragraph, the value for the
required minimal output impedance for a unit current cell will be calculated as a func-
tion of the resolution of the DIA converter. It will then become clear that for high
resolutions and designs with a large interconnect capacitance Co the non-linearity in-
troduced by the output impedance severely limits the output signal bandwidth.
For a sin(wt) output signal, the number of switches T that conduct current at a
time t equals:

1 + Sin(wt»)
T(t) = S ( 2 (5.4)

with S the total number of current sources.

The total output impedance of the DIA converter is determined by the load impedance
ZL in parallel with T(t) parallel impedances Zimp:

Sf (l + sin(wt»
::::} Vout(t) = - - - - - - - - - - (5.5)
2ft + Yi mp S(1 + sin(wt»

with I the current through one switch transistor and Yimp = l/Zimp and YL = l/ZL.
A Taylor series expansion of the output voltage allows to determine the influence of
Yimp on the dynamic performance of the D/A converter.

On the condition that SYimp « ft, the ratio Q of the fundamental signal to the
second order harmonic is given by equation (5.6).
5.3 SFDR-Bandwidth limitations 59

10 12 14 18
resolution of the DAC

Figure 5.3: The required output impedance as afunction of the resolution of the DIA
converter and for a load impedance of 25 ohm

4YL
Q = -------'-
+ 2SYimp (5.6)
SYimp

Similar calculations can be performed to determine the influence of higher order har-
monics on the SFDR of the DIA converter.
For the completeness of the presented work, the detailed calculations are given in
Appendix 2. This Appendix will also show that the third order distortion component
caused by the dynamic impedance effect is very small.
From formula ( 5.6), the value for the required Zimp for a given resolution can be
easily determined and equals:

(5.7)

Eq.(5.7) is plotted in fig.5.3 for a D/A converter with a resolution between 8 and
16 bits and for a load resistor of 25 ohm. For a resolution of 10 bits the Zimp has to
have a value of about 6.4 MQ which is still relatively easy to implement. However,
for a 12 bit current steering D/A converter with a load resistor of 250., the value for
the required Zimp has to be at least 100 MQ in the Nyquist frequency range. This is
no longer a straightforward design specification since for high speed, high accuracy
circuits the effect of the interconnect capacitance on the output impedance can no
60 Dynamic Behaviour of Current Steering DIA Converters

longer be neglected. From eq.(5.3), it can be derived that the total capacitance at the
drain of the current source has to be smaller than the value given in eq.(5.8) otherwise
the non-linearity introduced by the output impedance of the D/A converter poses a
hard constraint on its dynamic performance.

C < rOswgmsw
°- 2n IN Zimp ,req
(5.8)

with IN the Nyquist frequency.

Eq.(5 .7) can be rewritten in function of the SFDR.

4Z
SFDR ~ HD2 = 201og(Q) = 201og(~) (5.9)
SZL

The number of current sources S approximately equals 2N (with N the number of

bits) for high resolution D/A converters. Eq.(5.9) can then be rewritten as :

Zimp
SFDR 201og(-) + 201og4 - 201og(2 )
N

ZL
Zimp
SFDR 201og(-) - 6.02 (N - 2) (5.10)
ZL

From this equation, it can be concluded that doubling the load resistance of the
D/A converter can lead to a SFDR decrease of 6dB. Increasing the resolution of the
DI A converter for a constant z~:p ratio, also deteriorates the dynamic performance.

5.4 SFDR-Bandwidth Optimised Implementations

Since the values of the pole and zero in the current cell output impedance are practi-
cally solely determined by the interconnect capacitance Co, an optimised layout can
lead to a considerable improvement. However, this will only result in a few extra
MHz SFDR for high resolution DIA converters. Therefore a solution has to be found
at the design level that consists of changing the frequency dependency of the output
impedance Zimp by placing for example an extra cascode transistor either on top of
the switching transistors or on top of the current source transistor. This will not only
change the frequency behaviour of Zimp but also increase its DC value.
 5.4 SFDR-Bandwidth Optimised Implementations 61

.
G. w
Daw +---:- _i !e_.~.

9msw Vg.uw rosw

Deas= S SW

RLOAD Geas

out
----, 0 ct = Sc;os
9mca. Vg~c.. 'aus
C, ~ VI'"
~ Gc •
I
I

M.w : 9mca Vises 'Oe. Co

scs I

(b) small signal model

i tes t = i rOsw - 9 msw V ssw i rOcas =Vssw - Vscas

roc• s

i tes t = i rOca. + i c , - 9 me.s Vse• s i rOsw ros,", =vtes! - ~sw

(a) cascaded current source i ZOes = i rOeas - g meas V.eas i c , =sC, V ssw
Z Ocs =rOes /I C o
config urati on i zOe. Z oe. = V seas

(c) set of equations

Figure 5.4: The cascoded current source configuration (a) the circuit schematic (b)
the small signal model and (c) the set of equations

5.4.1 The Cascoded Current Source Transistor

A symmetrical solution consists of placing a cascode transistor on top of the current

source transistor (fig.S.4.a). Only one additional transistor is necessary in comparison
with the basic current cell. In order to be able to accurately describe the frequency
behaviour of the impedance Zimp , its algebraic expression has been calculated using
the small signal model (fig.S.4.b). Solving the set of equations (fig.S.4.c) leads to the
following result:

num(Zimp) = gOeasgoes + gOswgoeas + gOswgmeas + gOswgOes + gOeasgmsw + gmsw

gmeas + gmswgoes + S(gOeas Co + gOeasCI + gmeasCI + gOesC , + goswCO + gmswCO)
+s2CoC,
(5.11)

denom(Zimp) = gOsw(gOeasgOes + s(gOeasCO + gOeasC, + gmeasC, + gOes Cd

+s2CoC,)
(5.12)
62 Dynamic Behaviour of Current Steering DIA Converters

Both the numerator and the denominator will now be separately discussed in some
more detail.

5.4.1.1 The analysis of the zeroes of the impedance Zimp

Since the transconductance gm of a transistor is in general about 10 to 20 times larger

than the output conductance of the same transistor and since for mismatch reasons the
value of the conductance gOes is small (because of the large value for the gate-length
L), the numerator of Zimp can be simplified to:

T = num(Zimp) = gmswgmeas + s(gmeasCI + gmswCO) + s2CoC,

= (sC, + gmsw)(sCO + gmeas) (5.13)
From eq.(5.13), it can be concluded that the impedance Zimp has 2 zeroes, namely:

gmsw gmeas
and = 2rr Co
(5.14)
Z, = 2rrC, Z2

5.4.1.2 The analysis of the poles of the impedance Zimp

For the denominator, two different cases have to be studied as will become clear from
the analysis of the simplified expression:

D = denom(Zimp) = gOsw(gOeasgOes + S(gOeas Co + gmeasC,) + s2 COC,) (5.15)

This equation can not be easily factored.

In the first case, it is assumed that the value of the product COgOeas is much larger
than the value of C,gmeas' The denominator can then be written as:

D = gOsw(gOeasgOes + s(gOeasCO + gOesC,) + s2 COC,)

= gosw(sC, + gOeas)(sCO + gOes) (5.16)
It can be concluded that the impedance Zimp has 2 poles located at the following
frequencies:

1
P'a=---- and P2a = - - - - (5.17)
2rrC,rocas 2rrCorOes

In the second case (COgO eas « C,gmeas), the denominator can be factored in the
following manner:

D = gOsw(gOeasgOes + S( gOeas gOes Co + gmcasC,) + s 2 CoC,)

gmeas
5.4 SFDR-Bandwidth Optimised Implementations 63

gOsw gOeas gOes

= (sC,gmeas rOeas rOes + 1)(sCo + gmeas) (S.18)
gmeas
Notice that one of the poles of the impedance Zimp will now coincide with one if its
zeroes and as a consequence, a frequency behaviour similar to the one of the current
source transistor without the cascode transistor is seen.

gmeas
P'b = - - - - - - - and P2b = 27TCo (S.19)
27T C, g measrOeasrOes
The case where COgOeas ~ C,ggmeas does not present itself in reality because
for high resolution current steering D/A converters either Co or C, incorporates the
interconnection capacitance making that term the dominant one.

5.4.1.3 A numerical example

A numerical example will now be given to illustrate the theory. In this example the
impedance Zimp will be calculated for a 12 bit current steering D/A converter with a
full scale current of 20 rnA that is designed in a O.SMm technology. In a first step, the
transistor parameters will determined.

The dimensions of the current source transistor are determined by the used tech-
nology mismatch parameters and the full scale current.

All 1.9%Mm
AVT 13mVMm
MC ox -5 A
2 8.S * 10 V2
(Vcs - VT) es 1V
Ies SMA
The values of the gate-length and gate-width can now be calculated and equal Wes =
2.3Mm and Les = 37 Mm . The output conductance of the current source transistor
equals gOes = 8.S * 10- 8 S
The current flowing through the cascode and the switch transistor is equal to the
current flowing through the current source transistor and as a consequence also the
values for the gate overdrive voltage, the dimensions, the transconductance and the
output conductance of these transistors can be determined.

(Vcs - VT )eas 0.24 V

Weas 0.8Mm
L eas 0.7 Mm
gmeas 42MS
gOeas 1.6MS
64 Dynamic Behaviour of Current Steering DIA Converters

Zimp [Ohm]

330 M 1 - - - - - " .

100 M ,
-----,- (a)
current source configuration
-Qmsw/Co without cascode transistor
500k
, /
- - - - - - - - - - ... - - - - - -- - " r ' - - - - -
Co= 1pF

13.3 k 9M freq [Hz]

Zimp [Ohm]

8.5 G
/
11.2 MHz I
, (b)
100M --1'-
current source confilluration
17.2 M - - - --:- - - - - - --' \-----,... with cascode transistor
,
Co= 1pF
-Qmsw /C,
500 k
: • I /
-'t---
C, = 6.6fF
,
- - - - _,_ - - - - - - L - - - - _ 1- - - - - -

11.3 k 6.8 M 46.2 M 1.4 G freq [Hz]

Zimp [Ohm]

8.5G 1-------...
(c)
current source confilluration
___
,L __ _ with cascode transistor
100 M
,
I

Co= 6fF
,
500 k - - -- - -,- - - - - - - - - - - - ' r - - - - - C,= 1pF
I
I

529 9M freq [Hz]

Figure 5.5: Bode diagrams for the numerical example in section 5.4.1.3
5.4 SFDR-Bandwidth Optimised Implementations 65

(VGS - Vr)sw 0.2 V

Wsw 0.8p.,m
Lsw = 0.5p.,m
gmsw = 55p.,S
gosw 2p.,S

The mimimum values (without layout parasitics) of the parasitic capacitances Co

and Clare given by :

Cl 2 * CS- sw + CD - cas ~ 6.6 f F

Co CS-cas + CD-cs ~ 6 f F

Now, the Bode diagram will be calculated for the unit current cell without any
additional cascode transistors. The value of the interconnect capacitance Co is chosen
to be IpF. The impedance Zimp is then given by:

(5.20)

The values of the poles and zeroes are :

P = 13.3 kHz
z - 9MHz

The required value for the impedance Zimp is 100MQ to obtain a good dynamic per-
formance for the 12 bit D/A converter. This impedance is reached for a signal band-
width frequency of about 45 kHz. The Bode diagram is given in fig.5 .5.a.
The second case that will be discussed is the case where the interconnection be-
tween the switches and the current sources is done at the source node of the cascode
transistors. The value of the capacitance Co is chosen to be 1pF. The impedance Zimp
can then be calculated and equals :

2.5 * 10- 9 + 5.9 * 10- 17 * s + 6.6 * 10- 27 * s2

(5.21)
Zimp = 2.7 * 10- 19 + 3.8 * 10-24 * s + 1.3 * 10- 32 * s2
The exact values for the poles and the zeroes can be derived from this expression:

PIa 46.2 MHz

P2a = 11.3 kH z
ZI 6.8MHz
Z2 1.4GHz
66 Dynamic Behaviour of Current Steering DIA Converters

The required impedance of 100MQ is reached for a signal bandwidth of 1.2 MHz.
This is a more than 25 times improvement compared to the case where the current
source transistor is implemented without the casco de transistor. The Bode diagram is
given in fig.5.5.b.
The third case describes the situation where the interconnection between the cur-
rent source array and the switches is made at the drain node of the cascode transistor.
The value of the capacitance C] is chosen to be IpE The impedance Zimp is then
given by:

2.5 * 10-9 + 4.4 * 10- 17 * S + 6 * 10- 27 * s2

(5.22)
Zimp = 2.7 * 10- 19 + 8.7 * 10-23 * s + 1.2 * 10- 32 * s2

The exact values of the poles and zeroes are :

Plb = 529Hz
P2b = 1.2 GHz
z] 9MHz
Z2 = 1.2 GHz

From these numbers it can be concluded that P2 and Z2 coincide. The Bode diagram
for this case is given in fig.5.5.c. The required impedance of 100MQ is reached for a
signal bandwidth of only 45 kHz. This result is similar to the one of the current source
transistor without the cascode transistor. The zero is located at the frequency given
by gmsw /2n C 1, which is exactly the same frequency as the zero of the current source
configuration without the cascode transistor gmsw / 2nCo since both capacitances are
in this case determined by the interconnections. As is generally known, the product
of this frequency and the drain-source resistance of the switch transistor equals the
product of the required impedance and its corresponding frequency for a 20 dB slope
in the Bode diagram. As a consequence, both configurations have the same signal
frequency bandwidth.
It can be concluded from this example that placing an extra cascode transistor on
top of the current source is only useful if the interconnection between the switches
and the current source array is done at the source node of the cascode transistor. Fur-
thermore, it is important to note that this is only an example. During the design phase
of the 12 bit D/A converter, the values for the poles and zeroes (= the values of the
transistor parameters) together with the value of the interconnect capacitance Co have
to be optimised to obtain a maximum frequency bandwidth.
5.4 SFDR-Bandwidth Optimised Implementations 67

5.4.1.4 Fault analysis of the presented theory

The solutions of the numerical example are exact since no terms in the numerator or
the denominator of Zimp have been eliminated during the calculation. If the values for
the poles and the zeroes are calculated using the derived simplified analytic formula
of eq.(5.14) and eq.(5.17), the following results are found:

PIa = 38.6MHz and P2a = 13.5 kHz

Zl = 6.7 MHz and Z2 = 1.4GHz

There exists almost no difference between the values from the numerical example and
the theoretical equation for the frequency of the zeroes but for the frequency of the
poles this is not entirely true. This can be understood as follows .
The transfer function has the following form:

a + bs + cs 2 = 0

It is easy to derive that the sum of the two solutions of this equation equals b/c while
the product equals alc. If the exact formula of the denominator of Zimp is compared
to the simplified one, it becomes clear that for both equations the coefficients a and c
remain the same and only coefficient b is different.

This means that the product of the solutions of the exact equation and of the sim-
plified one are equal. If we now assume that one pole is dominant over the other one,
it can be stated that the pole with the highest frequency equals b/c. This directly im-
plies that the dominant pole has a frequency equal to alb. If the coefficient b of the
simplified expression is x times smaller than the coefficient b of the exact expression,
the calculated dominant pole will be a factor of x larger than the real dominant pole.
In this case,

gOeas Co + gOes C I
Preal ,dom = P est ,dom * ---------------
gOeasCO + gOeasCl + gmcasCl + gOesCl (5.23)
Preal ,dom = Pest ,dom * P eorrl
which for the numerical example leads to a correction factor P eorrl that equals 0.85 .
The real non-dominant pole has a value of Preal ,nondom = P es t ,nondom * l/Peorrl =
68 Dynamic Behaviour of Current Steering DIA Converters

Pest ,nondom * 1.18 since the product of the two poles has to remain constant as was
mentioned earlier.
Another important implication of this correction factor Peorr! is that the impedance
levels of Zimp shift! The middle level of Zimp is in this case no longer equal to
*
gmeasrOeasrOsw but to gmeasrOeasrOsw Peorr I. It is important to take this into account
during the design of the D/A converter.
In the second case (gOcasCO « gmeasCI), the exact and the simplified expressions
for the denominator of Zimp are given by

gOcasgOcsCO 2
D est = gOsw(gOeasgOes + s( + gmeasCd + s CoCd
gmeas
The correction factor is determined in the same way as in the previous paragraph and
equals

COgOcas gOes
gmeas
+ gmcas C1
Pcorr2 = (5.24)
gOcasCO + gOeasCI + gmeasCI + gOcsCI
which has a value of about Pcorr2 ~ 1(0.98) for the numerical example. In this case
the estimated values of the pole and zero (p Ib = 517Hz and Z2b = 8.8M Hz) fre-
quencies are practically the same as the numerical calculated ones.

5.4.1.5 Conclusion

To solve the problem of the output impedance, the cascoded current source is a good
option. However, it is important to note that this implementation only provides a
good solution if the cascode transistor is part of the switch array and not of the current
source array. Analysing the Bode plots leads to the conclusion that the best results will
be obtained by using a minimised interconnect capacitance Co and a small parasitic
capacitance C I.

5.4.2 The Cascoded Switch Transistor

The second solution that will be discussed is the use of a cascode transistor on top of
the switch transistors (fig.5.6.a). This architecture is already frequently used because
it reduces the glitch energy error caused by the digital feedthrough through the gate-
drain capacitance of the switches [Marqu ISSCC98] . In fig.5.6.a/b, the schematic
representation of the unit current cell is given together with the small signal model of
5.4 SFDR-Bandwidth Optimised Implementations 69

i test =i rOcas - 9 mcas V scas i rOsw rosw = V seas - V ssw

i test =irO.w +i C1 -9 msw Vssw i rOca. roca. =V te .. - Vsc ••

(a) cascoded switch transistor iZOcs =i rOsw - 9 m$W V ssw i C1 = s C 1 V scas

configuration izOcs Z Des = Vssw Z Dc. =rocs 1/ Co
(c) set of equations

Figure 5.6: The cascoded switch transistor configuration (a) the circuit schematic (b)
the small signal model and (c) the set of equations

the circuit. This model is similar to the one of the cascoded current source transistor
(fig.5.4) that has been discussed in the previous section. The impedance Zimp is given
by:

num(Zimp) = gOswgocs + gOswgOcas + gOcasgmsw + gOcasgocs + gOswgmcas+

gmswgmcas + gmcasgocs + s (gosw Co + gosw C [ + gmsw C [ + gocs C [ +
gOcasCO + gmcasCO) + S2CoC[
(5.25)

denom(Zimp) = gOcas(gOswgOcs + s(goswCO + gosw C [ + gmsw C [ + gocsC[)

+ s2CoC[)
(5.26)
Also for this case, the numerator and the denominator are discussed separately.

5.4.2.1 The analysis of the zeroes of the impedance Zi mp

The numerator of the impedance Zimp can be factored in the same way as for the
cascoded current source implementation. This leads to the following result:
70 Dynamic Behaviour of Current Steering DIA Converters

Zimp [Ohm]

8.5 G
I 1 MHz
100 M - -
I
I--
/'
I cascoded switch transistor
11 M - --- -:-
I

- - - - - -')-----,.. configuration

Co= 1pF
C1 =6fF
625 k - - - -
I
- 1- - - - - - - L - - - - _1- - - - - - -r - - -
I I I
I I
I

11.6 k 9M 56M 1.1 G freq [Hz]

Figure 5.7: Bode diagrams for the numerical example in section 5.4.2.3

T = (SCI + gmcas)(sCO + gmsw) (5.27)

The values of the zeroes is then given by :

gmcas gmsw
and (5.28)
ZI = 2nCl Z2 = 2nCo

5.4.2.2 The analysis of the poles of the impedance Zimp

Since the switch transistors are never incorporated in the current source array because
of decoupling reasons, there is actually only one case that has to be considered, namely
the case where goswCO » gmswCl (the interconnection is made at the drain node of
the current source and thus is part of the capacitance Co). The denominator can be
factored:

(5.29)

and as a consequence the poles are given by :

1 1
PI = - - - - and P2= - - - - (5.30)
2nClrosw 2nCorocs

5.4.2.3 A numerical example

In order to make a comparison between the different implementations, the same

values for the transistor parameters are chosen as in section 5.4.1.3. The value of the
5.4 SFDR-Bandwidth Optimised Implementations 71

interconnect capacitance Co is chosen to be I pF. The impedance Zimp is then given

by:
2.S * 10-9 + 4.6 * 10- 17 * s + 6.6 * 10- 27 * s2
Zimp = -----::-::-------::-::-------::-:------::- (5.31)
2.7 * 10- 20 + 3.8 * 10-24 * s + 10- 32 * s2
The values of the poles and zeroes are :

PI 56MHz
P2 = 11.6kHz
Zl l.1GHz
Z2 = 9MHz

The Bode diagram is given in fig.5.7. From this figure it can be concluded that the
non-linearity introduced by the output impedance limits the output signal bandwidth
to a value of approximately 1 MHz which is a significant improvement compared to
the topology without the cascode transistor.

5.4.2.4 Fault analysis of the presented theory

The values calculated using eq.(S.28) and eq.(S.30) are:

PI 48.2MHz
P2 = 13.5kHz
Zl 1 GHz
Z2 8.8MHz

The correction factor Pcorr3 is derived in a similar way as for the cascoded current
source topology and equals:

Pcorr3 = - - - - - - ' 'gOcsCI + goswCO

------=---,-------
-- 0.86 (5.32)
gOcs CI + goswCO + gOswCI + gmswCI
The value for goswCO equals 2* 10- 18 and the value for gmswCI is about a factor of five
smaller and equals 3.6 * 10- 19 . If the difference between these two values becomes
larger, the correction factor will approach one. On the other hand, if the difference
decreases, the value of the correction factor becomes important and has to be taken
into account!

5.4.2.5 Conclusion

Cascoding the switch transistors will be an effective solution for the problem of the
dynamic output impedance. However it requires the implementation of two extra tran-
sistors for each current source which leads to a considerable increase of the occupied
72 Dynamic Behaviour of Current Steering DIA Converters

G.
D.w
~
<i) 9m... .... ',..
DcIfIII2 :5. w

out
.02
<1)9"""'....... ' ''''''' e)
Dcu l-Sgll

." <:) 9_,._, rlka• , e,1

D~ = S(;A'"

<f 9.... . .... '- f e,

S ..
-
(b) small signal model

irOsw r OSW = Vtest - Xsw

i test = 9 msw
ir1):!iW - V ssw
i rOcasl rOcas1 =V Ocas2 - XCils1
i test;;;; i l"Oeas2 + i C2 - 9 meaS2 V sc..Is2
i rOca.2 rOcas2 = Vssw
i l'Oc:as2 - 9 meillS2 Vseas2 =i tOeu1 + i Cl - 9 m~s1 VseaS1
- Vscas2

i rOes =irOc:nl - 9 mC-.!IS1 v:sen1

ic, =sC, V t;e••2
(a) double cascoded cu rrent
source configuration j ZOcs Z Ocs. =V scas1 ie2 =SC 2 V SSw

(c) set of equations

Figure 5.8: The double cascoded current source configuration (a) the circuit schematic
(b) the small signal model and (c) the set of equations

silicon area. Furthermore, the on- and off-switching of the cascode transistors disturbs
the fully symmetrical operation principle of the D/A core, leading to a deteriorated dif-
ferential behaviour.

5.4.3 The Double Cascoded Current Source Transistor

In this section, the effect of placing a double cascoded current source configuration
is investigated (fig.5.8). Throughout the calculations, it has been assumed that the
interconnection between the current source and the switch/latch array is located at
the drain of the current source transistor (large Co). The output impedance has been
calculated using the small signal equivalent depicted in fig.5.8.b. This leads to the
5.4 SFDR-Bandwidth Optimised Implementations 73

following result:

num(Zimp) + (gosw + gmsw)(gOcaslgOcas2 + gOcas[gmcas2+

= gOeaslgOeas2g0cs
gOeas[gocs + gmcasl gOcas2 + gmcasl gmcas2 + gmcas I gocs + gOeas2g0cs) + SCI (gOcasl

gOcas2 + gOeaslgmcas2 + gOcaslgOes + (gosw + gmsw)(gOeas2 + gmeas2 + gOes» + sCo(

gOcaslgOcas2 + (gosw + gmsw)(gOcasl + gmcasl + gOeas2)) + SC2(gOeaslgOcas2 + gOeasl

gmcas2 + gOeaslgOcs + gmcaslgOcas2 + gmeaslgmcas2 + gmcas I gocs + gOcas2g0cs)+

s2COCI (gOeasl + gmsw + gosw) + s2 COC2 (gOeasl + gmeasl + gOeas2) + s2CI C2

(gOcas2 + gmcas2 + gOes) + s3 CoC I C2
(5.33)

denom(Zimp) + SCI (gOcasl gOeas2 + gOeaslgmcas2 + gOcasl

= gOsw(gOcas I gOcas2g0cs
gOes) + sCO(gOeaslgOeas2) + SC2(gOcaslgOcas2 + gOcaslgmeas2 + gOeaslgOcs + gmcasl

gOeas2 + gmcaslgmcas2 + gmcaslgOcs + gOeas2g0cs) + s2 COC2 (gOcasl + gmcasl

+gOcas2) + s2COCI (gOeasd + s2CI C2(gOcas2 + gmcas2 + gOcs) + s3 COCI C2)

(5.34)

5.4.3.1 The analysis of the zeroes of the impedance Zimp

Eq.(5.33) can be drastically simplified by taking into account the fact that the transcon-
ductance of a transistor is about a factor of 20 larger than its conductance. The numer-
ator of Zimp can then be factorised in the following manner:

(5.35)

The zeroes are given by:

gmcas2 gmcasl
ZI = 2;rCo Z3 = 2;rCI
(5.36)

5.4.3.2 The analysis of the poles of the impedance Zimp

Eq.(5.34) can be simplified in the same manner as the numerator of Zimp. Taking into
consideration the large value of the capacitance Co, this results in:

denom(Zimp) = gOeaslgOcas2g0cs + sCOgOcaslgOeas2 + sC2gmeaslgmeas2

(5.37)
+s2COC2gmeasl + s3 COCI C2
Depending on the value of COgOeas I gOcas2 and C2gmcas I gmeas2, two cases are possible.
74 Dynamic Behaviour of Current Steering DfA Converters

In the first case, C2gmcaslgmcas2 » COgOcaslgOcas2. Eq.(S.37) further simplifies

to:
denom(Zimp) = gOcas l gOcas2g0cs + sC2gmcaslgmcas2 + s2COC2gmcasl + s3CoC, C2
(S .38)

For frequencies smaller than g mcas' /2rr C 1, the third order term in this equation can
be neglected. This assumption is valid since C, has a small value (tF) and thus the
pole g mcas 1 / C, is located in the GigaHertz range.

(S.39)

The solutions of this quadratic equation are given by:

= - - (1
P 2 3 gmcas2 ± ~1)
yl-X (S.40)
, 4rrCo

Since the value of x is much smaller than one, the Taylor series expansion of the square
root can be used, which directly gives us the value of the two poles.

P2 = gmcas2 (1 + (1 _ ~» ~ gmcas2
4rrCo 2 2rrCo

P3 = gmcas 2 (1 _ (1 _ ~» ~ gOcasl gOcas2g0cs

(S.41)
4rrCo 2 2rrC2gmcaslgmcas2

Remember that the value of the first pole was given by:
gmcas'
(S.42)
PI = 2rrC,

In the second case, C2gmcas I gmcas 2 « COgo cas I gOcas2. Eq.(S.37) further simplifies
to:
denom(Zimp) = gOcaslgOcas2g0cs + sCOgOcaslgOeas2 + s2COC2gmcasl + s3CoC, C2
(S.43)

The same assumption can be made as in the first case (relating to the third order term)
resulting in the same high frequency pole.

(S.44)

The solutions of this equation are given by:

X = -----------
4C2gmcas I gOes
(S.4S)
COgOcas 1gOcas2

Using the Taylor series expansion results in the following three poles
gmeasl gOes
(S.46)
PI = 2rrCI P2 = 2rrCO
5.4 SFDR-Bandwidth Optimised Implementations 75

Zimp[Ohm]

287G \-------,....
,
100M ,
----- 1
--
, current source configuration
I -gmsw/~ with double cascode fransistor
SOOk - - - - - - - - - -
:
~
/'
- - - - - - - - 'r'----
Co = 1pF
C1 =6fF
C2 = 6.6fF
2.4 k 1.4G freq [Hz]

Figure 5.9: Bode diagramsfor the numerical example in section 5.4.3.3

5.4.3.3 A numerical example

This example is a continuation of the example given in the previous sections (sec-
tions 5.4.1.3 and 5.4.2.3). For reasons of clarity, the values for the different parasitic
capacitances are repeated.

Co = 6fF
CI = 6fF
C2 = 6.6fF

The value for the transconductance and the output conductance of the second cascode
transistor are chosen identical to the ones of the first cascode. The value of the inter-
connect capacitance is chosen to be I pF (Co=1 pF) . Substituting the numerical values
in eq.(5.33) and eq.(5.34) gives the following result for the impedance Zimp:

4.4 * 10- 25 + 3.1 * 10- 29 * s + 6.1 * 10- 37 * s2 + 3.3 * 10-47 * s3

Zimp = l.l * 10-13 + 2.6 * 10- 21 * S + 4.5 * 10- 31 * s2 + 1.7 * 10- 41 * s3
(5.47)
The exact values of the poles and zeroes are:

PI 2263 Hz
P2 6.7 MHz
P3 2.9GHz
z\ 6.7 MHz
Z2 = 1.4GHz
Z3 2.9GHz

Poles 2 and 3 coincide with zeroes I and 3. A first order frequency behaviour is seen.
The Bode diagram is given in fig.5.9. From this figure, it can be concluded that the
76 Dynamic Behaviour of Current Steering DIA Converters

non-linearity introduced by the output impedance limits the output signal bandwidth
to a value of approximately 7 MHz which is a significant improvement compared to
the topology with only one cascode transistor. The values of the poles and zeroes are
equal to the ones calculated using the theoretical formulas.
If this result is compared to the Bode diagram presented in fig.5 .5.b, it can be
seen that the double cascoded configuration performs better than the cascoded one if
the middle plateau has an impedance level that is lower than the required impedance.
Otherwise, the two configurations would result in the same signal frequency band-
width. In order to have 3 pole-zero pairs, the value of COgOcas !gOcas2 has to be larger
than the value of C2gmcas!gmcas2. This means that the interconnection capacitance
has to be a factor of gmcaslgOcaslgmcas2g0cas2(~ 600) larger than the capacitance C2
seen at the sources of the switch transistors. For a parasitic capacitance C2 of a few
femtoFarad, the capacitance Co has to have a value of at least a few picoFarad. This
is almost never the case.
It should also be noted that for deep sub micron technologies (0.25J),m and below),
the implementation of a double cascode on top of the current source transistor is lim-
ited by the low power supply voltage. In this case alternative solutions have to be
found to improve the negative impact of the frequency dependent output impedance
of the DIA converter.

5.5 Conclusion
In this chapter, the SFDR-bandwidth limitations of high resolution D/A converters
have been analysed. A main fundamental limitation is the dynamic output impedance
of the circuit. The impact of this output impedance on the SFDR has been calculated.
Based on this analysis the requirements for the value of the output impedance of each
unit current branch has been derived. The frequency domain behaviour of the circuit's
output impedance has been analysed for different current cell topologies and the effect
on the SFDR has been illustrated with practical examples.
Chapter 6

A Design Methodology for High

Performance CMOS Current Steering
DIA Converters

6.1 Introduction

While in chapter 4 and 5, the emphasis has been put on modelling the static and the
dynamic behaviour of the current steering OfA converter architecture, this chapter will
cover the design flow for these circuits. In the first section of this chapter, the problem
of determining the level of segmentation is addressed. In the remainder of the text, it
has been assumed that a segmentation level of 0% matches a fully binary implementa-
tion and a segmentation level of 100 % represents a fully unary architecture. Both an
area based as a mathematically based approach to determine the segmentation degree
are discussed. In the following two sections, the choice of the thermometer decoder
and the switch driver are addressed. The remaining sections of this chapter describe in
detail the dimensioning of all the transistors in the unit current cell (the switch, current
source and cascode transistors).

6.2 Determining the level of segmentation in a current

steering DIA converter

6.2.1 The area approach

This approach is based on the silicon area consumption of the current steering OfA
converter [Lin JSSC98]. The method targets a minimal chip area that still guarantees
78 A Design Methodology for High Performance CMOS Current Steering D/A
Converters

the required static resolution and has an optimal frequency domain performance. It
consists of the following design flow.

• Determine the area necessary to achieve the INL specification.

As has been already mentioned in chapter 3, the INL specification of a current
steering D/A converter is independent on its architecture and is as such indepen-
dent of the segmentation level.

• Determine the area necessary to achieve the DNL specification.

Unlike the INL specification, the DNL error is dependent on the segmentation
level of the D/A converter architecture. If the minimum analog area for a fully
unary implementation equals Aunif, then the analog area of a fully binary archi-
tecture equals 2N * Aunit based on the DNL performance only.

• Determine the area necessary to implement the thermometer decoder.

It is evident that this area increases with the segmentation level of the DIA con-
verter. The value of the digital area relative to the analog area is dependent on
the circuit implementation and the used technology.

In fig.6.1, the impact of the different area constraints is depicted for a 10 bit imple-
mentation. The thick line indicates the area that is required to obtain a maximum
DNL error of 0.5 LSB and a maximum INL error of 1 LSB. For an implementation
with a minimum chip area, different segmentation levels (the flat part of the curve) are
possible as shown in the figure. However, shifting the segmentation level to a higher
value has a positive effect on the glitch and thus on the dynamic performance of the
DIA converter. As a consequence, the optimal point is situated on the right hand side
of the flat part of the curve. Although this method provides the designer with a tool
to determine the optimal segmentation degree, it is based on an inaccurate starting
point [Lin JSSC98]. In order to determine the area for implementing a certain INL
and DNL specification, several Monte Carlo simulations have been performed. The
expected value for both the INL and DNL error are then calculated by taking the root
mean square (RMS) of the simulation results for every input code instead of first de-
termining the INLIDNL error for every simulation and then extracting the expected
values. As a consequence, the relative position of the minimum required analog area
for the INL and DNL specification differ from the one presented in fig.6 .1.

6.2.2 The mathematical approach

This approach is based on the fact that for a current steering D/A converter with dif-
ferential switches (the current source is always turned on), a decoupling between the
resolution and the update rate specification is possible. The resolution of the D/A
6.2 Determining the level of segmentation in a current steering DIA converter 79

-
A total for DNL=O.5LSB, INL=1 LSB
I
28
A INL =O.5LSB
optimal
point ~
:J 26
tr A INL=1LSB
(1)
'-
"C
24
(1) A INL=2LSB
N
m
E
'-
o
s:::::

o segmentation level [0/0] 100

binary unary

Figure 6.1: Normalised required area versus the percentage of segmentation for a 10
bit DIA converter [Lin JSSC98]

converter is determined by the mismatch behaviour of the current sources while the
update rate is dictated by the switch transistors. In a first step, the dependency of the
DNL error on the segmentation level is analysed. A first analysis that can be made
to get insight in the expected inaccuracy at a certain transition is to determine which
transition will be responsible for the maximum of the DNL profile. For the unary im-
plementation, each transition has an equal probability of determining the DNL error.
However, for the binary implementation, the probabilities for each of the transitions
to determine the DNL error is different and has been simulated leading to the results
depicted in fig.6.2 for a 10 bit implementation. This figure clearly indicates that in
only 49% of the cases the MSB transition will determine the DNL error, while one
intuitively would focus on this transition.
At this point, amathematical derivation of the DNL error for the unary, the binary
and the segmented architecture is given. The calculation is based on the fact that
the more current sources switch at the same moment, the larger the variation on the
transition (un = sqrt(n) * u) will be. For a fully unary implementation, there are
2N - 1 transitions where each transition is modelled as a normal distribution with
U = Uunity. For a fully binary implementation, we only have N different transitions
each modelled as a normal distribution with Ui = sqrt(i - 1) * Uunity where i is
80 A Design Methodology for High Performance CMOS Current Steering D/A
Converters

the bit number. To determine the DNL error, a sample has to be taken from each
distribution. For the unary implementation, this results in a set of 2 N - 1 values while
for the binary implementation this results in a set of N values. The DNL error is then
determined by the maximum value of this set of samples. Based on basic statistical
operations, theorems and functions, the DNL error versus the segmentation level can
be calculated.
To derive a closed formula for the expected DNL error for the fully unary archi-
tecture [Borre PhD], we start from the assumption that each current source can be
modelled by a normal gaussian distribution with a mean value equal to 1 LSB and
a standard deviation CJ. For a N-bit resolution D/A converter, the 2N - 1 different
current sources are assumed to be uncorrelated. The definition of the DNL error can
be translated in the following experiment.
Experiment: Take 2N - 1 samples from a normal distribution with standard devi-
ation CJ and mean 1 LSB. The largest sample in absolute value determines the DNL
error.
The question that has to be solved is to find the number of CJ where the expected
value of the DNL error will be located. This can be solved by using the following
statistical theorem:
Theorem: If P is the possibility that an event happens, the average number-of-
experiments that has to be done to make the event happen is liP.
We define T as the possibility that a sample from the normal distribution is larger
than Z.CJ with z the number of sigma determining the DNL limit. Note that this z is
the parameter to be determined in this analysis. Based on the theorem, we know that
l/T experiments are required to have one sample that is larger than Z.CJ. Actually the
number of experiments is known and given by: 2N - 1.

1 N
- = 2 -1 (6.1)
T
This equation can be rewritten as:

1 jLSB +za
T = -N-- = I - p(f...I)df...! (6.2)
2 - 1 LSB-za

Based on statistical tables or on the inverse cumulative density function, the value of
z can be determined. Multiplying this value of z with CJ gives the expected value for
the DNL error.
1
DNLexp = ZCJ = invJlorm(-x ,x)(l - 2N _ 1) (6.3)

For a D/A converter with a 10 bit resolution, the expected DNL error equals approxi-
mately 3.3CJ.
6.2 Determining the level of segmentation in a current steering DIA converter 81

DNL determining transition

0.9

0.8

0.7

0.6
~
:c 0.4904
il 05
o
Q.
0.4

0.3

0.2

0.1
0.0011 0.0197
0.0002 0.0053
oL---~----~--~~----~~----
1 2 3 4 5 6 7 8 9 10
bit transition

Figure 6.2: Histogram of the probability that the DNL error is caused by transition i
as afunction of the transition for a 10 bit DIA converter

For the fully binary architecture the expected value for the DNL error is given by:

DN L exp ~ J2N=1 a (6.4)

Fig.6.3 shows the expected DNL values as a function of the resolution for a binary
and a unary architecture. The DNL values are expressed as a function of the unity
current source accuracy aLInit y . This figure gives the results of both the Monte Carlo
simulations (lines) as of the derived formulas in eq.(6.3) and eq.(6.4) (discrete points).
As can be seen from this figure, a good agreement exists between the formulas and
the simulations. Further analysis of this figure reveals that the expected DNL error
for a unary implementation is only a few times the unity standard deviation, while for
the binary implementation the expected DNL error strongly increases with the total
number of bits. This is the reason why designers traditionally do not choose a binary
implementation. However, based on the INL-yield considerations, one knows that
the unity sigma decreases with an increasing number of bits since a higher resolution
inherently requires a better accuracy. Therefore, fig .6.4 shows the expected DNL
value expressed in LSB. From this figure, it can be concluded that the expected DNL
performance for a binary architecture is relatively independent of the number of bits
and is always better than the required 112 LSB accuracy. The expected DNL error of
a unary implementation is even lower and improves with increasing resolution.
82 A Design Methodology for High Performance CMOS Current Steering D/A
Converters

BINARY and UNARY DNL

1401r===ri=~~~--'---~---'----'-~
- Monte-Carlo
- Monte-Carlo
120 0 formula
• formula
100

'iO
E 80
til
~
~ 60
c
40

20

4 6 8 10 12 14 16
number of bits

Figure 6.3: The expected value of the DNL error expressed in sigma as a function of
the resolution of the DAC for a fully binary and a fully unary architecture

UNARY and BINARY

0.25.----,.-----,-----,---..,---.,-------,---,

0.2

Binary
ai'0.15
en
:::.
...I
z
c 0.1

0.05

OL--~--~--~-~--~--~-~
2 4 6 8 10 12 14 16
number of bits

Figure 6.4: The expected value of the DNL error expressed in LSB as afunction of the
resolution of the DAC for a fully binary and a fully unary architecture
6.2 Determining the level of segmentation in a current steering DIA converter 83

Finally, also the yield for this DNL specification has been simulated. The results
are presented in fig.6.S. Fig.6.S .a shows the expected value for the DNL error for a 10
bit DIA converter (expressed as a function of the unit current source standard deviation
aunity ) and the 99.7% yield limit as a function of the segmentation level (1=fully
unary; lO=fully binary). It shows the strong DNL error increase when shifting towards
more binary bits. Based on the INL yield versus accuracy relationship (section 4.2.4),
fig.6.S .b has been calculated. It shows both the expected value of the DNL error and its
3a limit, expressed in LSB, as a function of the segmentation. It indicates that the 112
LSB DNL specification is inherently achieved even for a fully binary implementation.
To complete this analysis, it can be concluded that if the unit current source of the
D/A chip has been designed to achieve the INL yield specification, the DNL specifi-
cation will automatically be achieved within the same yield requirement even in the
extreme case of a fully binary topology.
84 A Design Methodology for High Performance CMOS Current Steering D/A
Converters

6.2.3 Conclusion

From the mathematical point of view, the binary implementation seems to be the most
advantageous one, especially since it also has a low power consumption. However, the
dynamic performance of the D/A converter is heavily dependent on the segmentation
level. The smallest glitches at the output and thus the best performance is achieved
for the fully unary architecture. Therefore, a certain degree of segmentation is called
for. For each bit that is added at the binary sub-D/A converter, the distortion due to
the non ideal switching errors will increase by a factor of two. It can be concluded
that in fact the level of segmentation is determined by the dynamic limitations. The
optimal segmentation point has to be found through simulations where a trade-off has
to be made between the area and power consumption and the SFDR specification.

6.3 Architectural choice of the thermometer decoder

In time, different architectures to implement the thermometer decoder have been pre-
sented. In this section, a short overview is given of the three most important ones.

• the row and column decoder

The thermometer decoder consists of both a row decoder and a column de-
coder [Nakam JSSC91, Miki JSSC86]. The combination of the control signals
of these two decoders determines if the current source is switched to the output
or not (as has been explained in section 4.3.2.3). Although this decoder allows
a simple implementation with a low power consumption, it inherently lacks the
flexibility to realise optimal switching schemes.

• the VHDL decoder

In order to implement any given switching scheme, the current sources are
placed in a different array from the switches and their drivers [VdBos CICC98].
For high resolution DIA converters, the row and column decoder can then be in-
tegrated in one block using a VHDL implementation. Although the update rate
of the circuit is determined by the performance of the available standard cell
library, the major advantage is the high level of automation that can be obtained
using this approach [VdPla JSSC99].

• the custom made decoder

For high speed DIA converter architectures, a custom made thermometer de-
coder is used. This decoder allows an optimal exploitation of the symmetry by
a detailed analysis of the required logic expressions. This results in a number
of custom made "standard cells" that can be optimised towards a high update
6.4 Design of the synchronised switch driver 85

rate. Furthermore, this approach gives the designer the opportunity to check
the timing constraints on every point within the decoder leading to an improved
dynamic behaviour of the DfA converter. An example of this type of decoder is
given in chapter 7. The major drawback of this method is the increased design
effort that is involved.

6.4 Design of the synchronised switch driver

To overcome the dynamic problems described in section 5.2, a synchronised driver

has to be placed immediately in front of the switches. Depending on the update rate
of the DfA converter different implementations can be used. Some of these drivers
will be discussed in more detail in chapter 7, where several realisations with different
resolutions and different update rates will be presented.

6.S Dimensioning the unit current cell

In this section, the design constraints will be discussed that determine the dimensions
of the current source, the switch and the cascode transistor.

6.5.1 The current source transistor

6.5.1.1 The area constraint

The dimensions of the current source transistor are dependent on the full scale output
current of the DIA converter and the technology in which the chip will be imple-
mented. According to the mismatch equations [Pelgr JSSC89, Laksh JSSC86], the
gate area of the current source is determined by :

WL (6.5)

The values for the mismatch parameters All and A VT are provided by the foundry.
The relative unit current standard deviation is dependent on the resolution and the
desired yield of the D/A converter (cfr. section 4.2.4) and can be easily calculated
using eq.( 4.11). As an example, the unit current source area is plotted versus the
yield of the D/A converter with a 8 bit, 10 bit and 12 bit resolution (fig.6.6) for a
gate overdrive voltage of 1V and for an implementation in a standard CMOS O.3SfA,m
86 A Design Methodology for High Performance CMOS Current Steering D/A
Converters

70

N
E
2. 60
III
CII
~
III
50

40

30

20

10

0
80 82 84 86 88 90 92 94 96 98 100

yield [%]

Figure 6.6: The unit current source area as afunction of the number offunctional DIA
converters for a 8 bit, a 10 bit and a 12 bit resolution

technology. This figure clearly indicates that the unit current source area under-
goes a large increase for yields above 95 %. Eq.(6.5) clearly indicates that the unit
current source area is dependent on the used technology through the technological
mismatch parameters A tl and A v T. The A VT parameter scales linearly down with
technology [Laksh JSSC86] while the Atl parameter remains approximately the same
[Laksh JSSC86, Bult ESSCIRCOO]. For a certain yield and a given resolution of the
DIA converter, it can then be stated that the unit current source area is proportional
to the (VG;~~d ratio. Since the supply voltage also scales down with technology
and a certain output swing is required for the D/A converter, the gate overdrive volt-
age Vcs - VT will also scale down in approximately the same way as the mismatch
parameter AVT does. It can be concluded that the required area of the unit current
source remains about the same. In fig.6.7, the unit current source area as a function of
the used technology is given. From this figure, it can be clearly seen that going to a
smaller technology with a scaled supply voltage will give no area advantages. When
the supply voltage doesn't scale down, the improved matching behaviour of the tran-
sistors can have a beneficial effect. However, for future deep submicron technologies
like the 0.12 ftm, 0.10 ftm and the 0.07 ftm technology the supply voltage scales down
and no decrease of the area of the current source array can be realised in comparison
to 0.18 ftm or 0.25 ftm current-steering D/A converter designs.
6.5 Dimensioning the unit current cell 87

6r-------r-------r-------r-------r-------r-----~35

.-.------------
4

15

OL-__L-__L-__L-__L-__L-__L-__L-__L-__L-__L-__L-~10
o 0.1 0.2 0 .3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.2
gate-length [urn]

Figure 6.7: The unit current source area as a function of the used technology (min.
gate-length) for a lO-bit DIA converter

6.5.1.2 The output voltage swing

A second constraint is given by the value of the full scale current IF S of the DfA
converter (or the wanted output voltage swing over a given resistor).

W 2IFS
(6.6)
L

Combining eq.(6.5) and eq.(6.6) results in a value for the gate-length and the gate-
width of the current source transistor.
The value for the gate overdrive voltage is determined as a trade-off between the
area of the current source transistor (large VGS - Vr) and the limit imposed by the
fact that all the transistors (switch, cascode and current source) have to operate in the
saturation region (low VGS - Vr) for a given supply voltage.

6.5.2 The switch and cascode transistor

While the dimensions of the current source transistors are determined by mismatch
considerations, the dimensions of the switch and cascode transistors are mainly deter-
88 A Design Methodology for High Performance CMOS Current Steering D/A
Converters

mined by the update rate specification. For this reason, the gate-length of the switch
transistor is chosen to be minimal. Since the current through the switch transistor
equals the current through the current sources, the gate-width can be easily calculated.
The main objective in dimensioning the switch transistors is in keeping both the gate-
length and the gate-width as small as possible. In this way the parasitic capacitance
at the output node is reduced which is beneficial for the settling time of the OfA con-
verter. Furthermore, the gate-drain capacitance is minimised which in its turn reduces
the digital feedthrough of the switch control signals to the output and as such has a
positive impact on the dynamic behaviour of the OfA converter.
The dimensions of the cascode transistor are determined by the fact that the same
current flows through both the current sources and the switches and by the dynamic
performance constraint discussed in chapter 5. The gate-length of the cascode tran-
sistor is in most cases larger than the minimal value since the output resistance of the
cascode transistor is directly proportional to this transistor parameter. In this way, a
large output impedance (seen in the drain of the switch transistors) can be realised in
order to overcome the dynamic limitations. The main objective in dimensioning the
cascode transistor is finding a trade-off between the required output impedance and a
small parasitic drain capacitance.

6.6 Conclusion
In this chapter, the design of the different sub-blocks of a current steering OfA con-
verter has been discussed ( the thermometer decoder, the switch driver and the unit
current cell). Furthermore, a mathematical approach has been derived to determine
the level of segmentation for a high resolution OfA converter. From this calculation,
it can be concluded that this level is not determined by the static performance but is
mainly determined by the dynamic performance of the driver.
Chapter 7

Realisations

7.1 Introduction

In this chapter, the design methodology discussed in chapter 6 has been put into use
through the implementation of six CMOS current steering D/A converters. These
realisations can be divided into four classes.
In the first section of this chapter, the emphasis is put on attaining a highly accu-
rate D/A converter. The design and measurement results of a 12 bit and 14 bit D/A
converter will be discussed. However, these devices have a poor frequency domain be-
haviour. In the second section of this chapter, a high speed circuit has been designed.
For this purpose, a low resolution (6 bit) DI A converter has been chosen as to keep the
complexity of the design (thermometer decoder, ... ) within boundaries. In the third
section, a combination of a high resolution and a high update rate has been realised in
a 10 bit 1 GS/s and a 12 bit 500 MS/s current steering DI A converter. Measurements of
both chips show a frequency domain behaviour that is better than all recently published
D/A converters [Lin JSSC98, Vital AACDOl, Bugej JSSC99, Khano AACDOl]. The
fourth section describes the design of a 10 bit low power DI A converter for telecom-
munication applications. This is the first chip (to the author's knowledge) that com-
bines a good dynamic performance and a low power consumption.

In the fifth section, an overview is given of the most important static and dynamic
specifications of the six presented realisations. In order to make a comparison possi-
ble, an objective figure of merit has been introduced in the last section of this chapter.
The expression for this figure of merit is based on the resolution, the dynamic be-
haviour, the area and the power consumption of the DIA converters under comparison.
This figure is then compared to other published DI A converter designs.
90 Realisations

Dumm y
8MSBD- Pipelined 8 bit
thermometer decoder
Pipe- --0 4 LSB
lines

Switch and Latch array

t ---0 Out +
---OOut-

Routing switching Scheme

Centroid Current Source array

Figure 7.1: The jioorplan of the 12 bit DIA converter

7.2 High Accuracy DIA Converters

7.2.1 First Design of a 12 bit D/A Converter

7.2.1.1 The Floorplan

The first D/A converter design that is discussed in detail is a 12 bit segmented current
steering D/A converter. Fig.7.1 gives a schematic representation of the realised chip.
As has become clear in chapter 6, the DNL error does not determine the number of
binary implemented bits but the dynamic performance is the limiting factor. From
simulations, the segmentation level was determined. As a result, the DIA converter
has been divided into two sub-DACs, where the four LSBs were implemented in the
binary and the 8 MSB's were implemented in the unary part. The output of the current
sources drives a son double terminated load. Due to the complexity of the decoding
logic, the conventional row and column decoder could no longer be used to generate
the thermometer code and was replaced by a pipelined full custom decoder synthesised
in a standard O.S pm CMOS logic. This D/A converter was designed to have a O.S V
single ended output swing implying a 20 rnA full scale drain current specification.
7.2 High Accuracy D/A Converters 91

Avr 12 mV pm
A,B 1.9 %f1m
a(l)/ I 0.25 %
(Ves - Vr) cs 1.4 V
IFS 20mA
segmentation 8-4

(W / L)cs l.5f1m/35.5f1m
(W/LLw 0.8f1m/lf1m
technology 0.5f1m

Table 7.1: The unit current cell specifications for the 12 bit DAC

7.2.1.2 Design of the swatch cell

Fig. 7.2 shows the swatch cell consisting of the unit current cell and the latch (syn-
chronised switch driver). To determine the dimensions of the transistors Me s ,Mswa
and Mswb of the unit current cell, the design procedure described in chapter 6 has
been followed. For an INL related yield specification of 99.7 % within a 0.5 LSB INL
error, the dimensions of the unit current source transistor have been calculated using
the following parameters:

A,B 1.9%f1m
Avr 12mVf1m
(Ves - Vrks 1.4 V
1FS 20mA

From these parameters, the following two constraints can be derived.

W
WL = 53 f1m 2 and - = 0.042
L
The resulting gate-width of the current source transistor equals 1.5 f1m and the
gate-length equals 35.5 f1m .

The dimensions of the switch transistors have been chosen to be as small as possi-
ble while taking the current constraint into consideration.

W
(Ves - Vr)sw = 0.3 V and L = 0.8
92 Realisations

~------------------------\ ~--------------------

- ---- , ---, 1 ~----,

, , Mswa
- - -,-'-
, ,
- - - - - - - - -- _ _MSWb
____ 1
1

, 1

, 1
1
1 1
, 1

,,
,
1 1
1
1 1
1
, ____________________ J

LATCH UNIT CURRENT CELL

Figure 7.2: The latch and the current cell

For a minimal value of the gate-width (W=0.8 Mm) of the switch transistors, the
gate-length equals I Mm. As a consequence, the switch transistor has a small parasitic
drain capacitance which has a beneficial effect on the settling time behaviour of the
DIA converter. An overview of the unit current cell dimensions is given in table 7.1.
The synchronisation of the input signals of the current switch transistors is guar-
anteed by placing a latch in front of the current switches, as indicated in fig.7 .2. Apart
from synchronising all signals, this latch also reduces the output current variation
due to the drain voltage variation of the current sources. In case of conventional
switch drivers, both switching transistors will be switched off simultaneously for a
short period. This results in a discharge of the capacitance on the drain node of the
current source transistor, which deteriorates the dynamic performance of the D/A con-
verter. In literature, several driving schemes are documented to solve this problem, all
of them requiring additional circuitry [Nakam JSSC91, Kohno CICC95, Wu JSSC95,
Basti JSSC91]. In this circuit, the intrinsic delay between the complementary outputs
is used to lower the crossing point. The value of this point can be further adjusted
(if necessary) by changing the Vss voltage of the latch as is indicated in fig.7.3. The
crossing point for a Vss voltage of 0 V, 0.2 V and 0.4 V is given on this figure. In
this case, a higher Vss leads to a lower crossing point due to the inverters that are
placed between the latch and the switch transistors. Since these inverters switch be-
7.2 High Accuracy D/A Converters 93

...... 3

~ 25
(I) . - - VSS=O .4V
en - - VSS=O.2V
.s 2
--
-...... vss=ov
0
> 1.5
::l
Co
::l 1

-
0
.r::
(J 0.5
co
:
0
1.40E-08 1.44E-08 1.48E-08 1.52E-08 1.56E-08

time [sec]

Figure 7.3: The output voltage of the latch for different values (0 V, 0.2 V, 0.4 V) of the
Vss voltage

tween VG N D-dig and the power supply VDD - di g, the control signals at the input of
the switches have an amplitude of VDD - di g - VGND - di g' In fig.7.3, VGND-di g equals
o V. To minimise the feedthrough through the CGD , the value of VG N D-di g can be
adjusted to reduce the voltage swing. Furthermore, the inverters act as a buffer to
minimise the clock feedthrough to the output of the D/A converter. Proper sizing of
the latch has resulted in a high voltage crossing point at the input of the switches in
order to prevent a simultaneous off-state of the switches.

7.2.1.3 Design of the thermometer decoder

In the classical row-column decoder, a complete row of cells has to be turned on

before switching to the following row, which results in an accumulation of system-
atic and graded errors [Basto CICC96, Lin JSSC98, Nakam JSSC91, Miki JSSC86].
Since the number of output lines of the thermometer decoder increases with an increas-
ing number of bits, the complexity of the decoding logic increases drastically resulting
in a large input capacitance that has to be buffered. A VHDL implementation based
on lookup tables was developed using a standard cell library. The unary thermome-
ter decoder was synthesised from this VHDL code using Synopsys. The placement
and routing was done with the Cell Ensemble 3 tool within the Cadence Framework
[V dPla JSSC99]. To complete the thermometer decoder, a dummy decoder has been
94 Realisations

[, ' 't ----------------- --------- E

I/)
o
a.
I--
I-- t J ( 2
2 II II 2 2 II
3 3 3 II 3

3 ~ 3 13 U 3
II 2 2 II II 2 2 II

II 12 2 II II 12 2 II
13 II 3 3 ~ 3

•
13 I ~

2~ ~~
~ 3
II 2 2

Figure 7.4: The double centroid switching scheme

made for the 4 LSBs as to prevent any latency problems that could otherwise occur
between the unary and the binary part of the DIA converter. The maximum achiev-
able update rate of the DI Aconverter is limited by the performance of the available
standard cell library. Only 2 or 3 gates can be cascaded in a 5 nsec time frame which
limits the update rate to 200 MS/s. A higher speed could be obtained if a faster digital
cell library had been available.

7.2.1.4 The switching scheme

If the resolution of the DI Aconverter increases by a single bit, the number of current
sources in the current source array doubles. The area occupied by a single unit cur-
rent source also doubles because of the random matching constraint. This leads to a
four-times area increase for the current source array for each additional bit. For D/A
converters with a resolution of 10 bits and higher, the dimensions of the current source
array become so large that process-, temperature- and electrical gradients have to be
7.2 High Accuracy DfA Converters 95

considered. The non-linearity errors introduced by these gradients can be (partially)

compensated by the introduction of a special switching scheme as has been explained
in section 4.3.
Since in this design, the four LSBs are implemented in a binary way, the value of
the unary current source equals sixteen times the LSB current. This current source
is divided into sixteen LSB current sources that are placed symmetrically around the
center of each quadrant and are switched to the output at the same time as is indicated
in fig.7.4. This switching scheme compensates for the errors introduced by linear and
symmetrical gradients both in the horizontal or vertical direction. Furthermore, the
accumulated error is minimised since the current sources in the four quadrants are
simultaneously switched to the output.
To implement this switching scheme, the three available metal layers of the 0.5 J-tm
technology have been used. The first metal connects the ground line of the current
source transistors in the matrix. The second and the third metal have been used to
implement the unary current source. Four vertical lines each connect four current
sources in a selected column, while the horizontal line connects the four vertical lines
connecting hereby the 16 unit current source transistors of a unary current source. As
a consequence, the current source matrix has been completely covered with a fully
symmetrical metal interconnection pattern that was identical for each current source
transistor. In this way, a degradation of the mismatch behaviour caused by an asym-
metrical metal coverage of these transistors has been avoided [Tuinh ICMTS97].

7.2.1.5 The layout

To obtain the 12 bit accuracy, several measures have been taken at layout level. The
coupling between the analog and the digital part of the chip has been minimised by :

• using a separate array for the swatches and the current sources. This has the
additional advantage of lowering the influence of the distance matching effect
[Pelgr JSSC89] ,

• using different power supply lines for the analog and the digital block of the
DI A converter,

• placing a guard ring around the sensitive analog current source array as to avoid
any digital coupling through the substrate.

To reduce the voltage drop in the ground lines of the current source transistors,
sufficiently wide supply lines have been used that are drawn on top of these transistors.
96 Realisations

Figure 7.5: The chip photograph a/the 12 bit DIA converter

To avoid any coupling from the clock and/or any other digital switching line to
the output, acomb-like layout scheme has been used that is depicted in fig.7.6. From
this figure, it can be seen that the swatch cells are placed together in groups of two
that share the same clock line but have different lines to the output. In this way, a
decoupling of the output from the clock has been realised.
The chip has been processed in a double poly standard 0.5 /Lm CMOS technology
with 3 metal layers. The chip photograph of the 12 bit D/A converter is shown in
fig.7 .5. The decoding logic, the swatch array and the current source array can be
clearly distinguished on this photograph. Between these two arrays, a considerable
amount of area was used for routing the complex switching scheme. Since an accuracy
of 12 bit was the main goal of this first design, a minimisation of the area was not
targeted. However, the routing area can be completely eliminated by integrating the
routing in the digital decoder. In this wayan area reduction of 25 % can be achieved.

7.2.1.6 Measurement results

7.2.1.6.1 Static measurements The 12 bit D/A converter has been measured at a
2.7 V power supply for both the analog and the digital part of the chip. All measure-
7.2 High Accuracy DIA Converters 97

THERMOMETER DECODER
J
--- -.-------------- --- ----- ---:
-
____ 9 ______

lr;:I - I'
=

UJ
r---- LATCH

UJ
z I!
~}J w
z
L LATCH

I ~
z
:l :l :l

I~
""g
il ""g
~

,"'",J
~ I[
" 0
"
I
~ ~

f- ~ SWITCH SWITCH r==

'-
Il c,
,
L,- '- ,
-------- -------------------- ------- ---e--_ OUTPUT
'-r

------------ ----------- ---.---- - - - - - - - =... - - - - - - .. OUTPUT

J-'-

I CURRENT SOURCE ARRAY

I

Figure 7.6: A simplified scheme of the layout of the 12 bit DIA converter (the grey area
represents the substrate straps)

ments have been performed on a single-ended output for a full scale output current
of 20 rnA. To shield the DIA converter from any external noise coupling, the circuit
has been mounted on a ceramic substrate that was encapsulated in a copper-beryllium
case. Fig.7.7.a and fig.7.7.b show the measured integral non-linearity and differen-
tial non-linearity profile of the 12-bit DIA converter. The INL error is approximately
0.5 LSB, implying a monotone behaviour of the DI A converter. The DNL error equals
0.7 LSB.

7.2.1.6.2 Dynamic measurements In this paragraph, the measured dynamic be-

haviour of the D/A converter is discussed in detail. In fig.7.8.a the measured spurious
free dynamic range (SFDR) of the DIA converter as a function of the input frequency
is given for an update rate of 200 MHz. The SFDR remains above 70 dB up to an in-
put frequency of 250 kHz. For larger frequencies the SFDR starts dropping and for a
2 MHz input signal its value equals 59 dB. On the same figure, the results of the model
of the dynamic impedance are shown. As has been explained in chapter 5, the SFDR
is limited due to the frequency dependency of the output impedance. The difference
between the measurements and the model at low frequencies is mainly determined by
the mismatch errors of the current sources. In fig.7 .8.b, the frequency of the input sig-
98 Realisations

-0.6

-0.8

_1L---~~--~----~----~----~----~--~----~
o 512 1024 1536 2048 2560 3072 3584 4096

DAC Input Code

(a) The measured INL of the 12 bit D/A converter

0.8

0.6

0.4

Iii'
C/) 0.2
.:.
oJ
Z 0
0
(.)
<I: -0.2
0
-0.4

-0.6

-0.8

-1
0 512 1024 1536 2048 2560 3072 3584 4096
DAC Input Code

(b) The measured DNL of the 12 bit D/A converter

Figure 7.7: The static performance of the 12 bit DIA converter

7.2 High Accuracy DIA Converters 99

85
-A- measu rements
80 --+- model dynamic impedance
75
.-.. 70
en
"0
........ 65
0::
C 60
LL
C/)
55
50
45
40
0.01 0.1 1 10 100
frequency [MHz]

(a) The SFDR versus the input frequency at an update rate of 200 MS/s

75

70

65

ai' 60
~
a:
c
u..
(/) 55

50 input frequency = 500 kHz

45

40
0 50 100 150 200 250 300
update rate (MS/s]

(b) The SFDR versus the update rate for a sinusoidal input signal fre-
quency of 500 kHz

Figure 7.8: The dynamic performance of the 12 bit D/A converter

100 Realisations

ai'
~
-20
E
2
'0Q)
0-
CJ)
-40
'S
.e
:;J
0
Q)
>
-60
~
Gi
a:
"tI
2!
:;J
III -80
01
Q)
:;:

-100
0 0.5 1 1.5 2 2.5
Frequency [MHz]

Figure 7.9: The measured relative output spectrum @ approx.500kHz signalfrequency

and @ 200MHz update rate

nal is kept constant at a value of 500 kHz while the update rate of the OfA converter is
swept from 10 MHz to 300 MHz. The SFOR varies around the 70 dB level for update
rates up to 200 MHz.
Fig.7.9 shows a typical output spectrum of the OfA converter for a 500 kHz full
scale sinusoidal input signal clocked at a frequency of 200 MHz. The SFOR is domi-
nated by the second order harmonic distortion component which lies 69 dB below the
signal level. The worst case power consumption has been measured at a 200 MSfs
update rate of the OfA converter and equals 140 mW.

7.2.1.7 Conclusion

The followed design procedure to determine the dimensions of the unit current cell
has been verified by the static measurement results. The dynamic performance of
this OfA converter is far from optimal what can be contributed to several causes. For
example, the control signals of the switches don't have a reduced swing as to lower
the capacitive feedthrough to the output of the OfA converter. Furthermore, no cas-
code transistors have been implemented to counteract the effect of the varying output
impedance. However, the main goal of processing this chip was to investigate the
static behaviour of high resolution current steering OfA converters. In the third sec-
tion of this chapter, a second 12 bit OfA converter with a state-of-the-art dynamic
performance will be discussed. The measurement results of this chip are summarised
7.2 High Accuracy DIA Converters 101

resolution 12 bit
update rate 200 MS/s

INL error 0.5 LSB

DNL error 0.7 LSB
SFDR (lMHz@200MS/s) 65 dB
SFDR (500kHz@300MS/s) 50 dB
power consumption 140mW
active area 14mm 2
process 0.5 J.lm

Table 7.2: Summary o/the 12 bit DAC peiformance

• Switch/Latch Array.
255 ..... 6 .....
Binary
I- Unary current source I- current src
_---.J~-=
-.:::
---- --__ , , , ,array , , , , ,
array
"'"""'11 1
Current Source Array
1 1 1 I" 1 1

Figure 7.10: The jloorplan o/the 14 bit DIA converter [VdPla ISSC99]

in table 7.2.
102 Realisations

AVT 12 mV /vLm
A,8 1.9 %/vLm
(J(I)/ I 0.125 %
(VGS - VT)cs IV
hs 20 rnA
segmentation 8-6

(W / L)cs 1.1/vLm/104/vLm
(W / L)sw 12.8/vLm / 1/vLm
technology 0.5/vLm

Table 7.3: The unit current cell specifications for the I4 bit DAC

7.2.2 A 14-bit Intrinsic Accuracy Q2 Random Walk CMOS D/A

converter

7.2.2.1 The Floorplan

The block diagram of the 14 bit segmented D/A converter architecture is depicted in
fig.7.1O. The 8 MSB's (referred to as b6-b13 in fig.7.10) are decoded from binary
to thermometer code in the thermometer decoder, which steers the unary weighted
current source array. The 6 LSB's (referred to as bO-b5 in fig.7 .10) are delayed by the
latency equalizer block in order to have an equal delay with the MSB's. Similar to
the 12 bit design all digital coding (thermometer decoder and latency equalizer block)
has been grouped at the top of the chip. The latches and the current switches M2a and
M2b are grouped in the switch/latch array in the middle of the chip. Finally, all current
sources (binary weighted as well as unary weighted) can be found on the bottom of
the chip in the current source array. A new switching scheme capable of obtaining a
14 bit intrinsic static linearity has been implemented and will be discussed in section
7.2.2.3 [VdPla JSSC99].

7.2.2.2 Design of the swatch cell and the thermometer decoder

Based on eq.(4.11), a relative unit current source standard deviation of 0.125 % is re-
quired to obtain a yield of 99.7 %. The 14 bit D/A converter has been implemented in
a standard 0.5 /vLm CMOS process and has a full scale current of 20 rnA. The dimen-
sions of the current source transistor can be determined from the following equations
7.2 High Accuracy DIA Converters 103

w (7.1)
=
L 96

From eq.(7.1) the gate-length and the gate-width of the current source transistor
(Wand L) have been calculated:

W = 1.1 fLm L = 104fLm (7.2)

An overview of the current cell dimensions is given in table 7.3.

The circuit of the latch driver used in this design was identical to the one of the first
12 bit design and as such an optimal gain in terms of IP reuse could be realised. The
reader is referred to section 7.2.1.2. Since the current switches of the binary current
sources are smaller, dummy switches have been added. So all latches, binary and
unary, have the same load and delay.
Since the dummy LSB decoder has been expanded from four to six bits, the ther-
mometer decoder for the unary block of the 14 bit D/A converter has been designed
according to the same principles as was the case for the 12 bit design.

7.2.2.3 The switching scheme

Even more so than for the 12 bit DIA converter, the errors introduced by process,
electrical and thermal gradients can degrade the static performance of the 14 bit D/A
converter. It is therefore essential to keep these errors under control. First hand infor-
mation on the gradients was available from a test chip that had already been processed.
From measurements, the values for the different unary current sources could be esti-
mated. This data has been used to extract the optimal switching scheme. In this way,
the different error contributions have been randomised as to minimise any error accu-
mulation in both the horizontal and the vertical direction.
The switching scheme has been given the name Random Walk Quad Quadrant
(Q2) switching scheme since four units placed in every quadrant of the current source
array are needed to implement one unary current source and the current sources are
switched on in a kind of random walk order over the array when the input code is
increased. In fig.7 .11, this scheme has been visualised. The regions indicated with the
symbols A through P have been optimised as to compensate for the quadratic errors
while the subregions 0 through 15 have been optimised towards the minimisation of
the remaining linear errors. In practice this means that for the first unary current
source subregion 0 in region A will be activated, for the second unary current source
subregion 0 in region B, ... , for the 255th unary current source subregion 15 in region
O. For more details, the reader is referred to [VdPla JSSC99].
 =
til
o
:.=
~ <:\.l
~
,~
~
~ ::;
.~
]
.~
222 190 126 62 209 177 113 49 213 181 117 53 217 185 121 57 ~ '"
158 30 254 94 145 17 241 81 149 21 245 85 153 25 249 89
78 238 14 142 225 1 129 229 133 73 233 9 137
~
65 69 5
!::
..
46 110 174 206 33 97 161 193 37 101 165 197 41 105 169 201 ~
;::
0 B F J .' , 12 10 6 2
211
147
179
19
115
243
51
83
220
156
188
28
124 60
252 92
215
151
183
23
119
247
55
87
219
155
187
27
123
251
59
91 ~
.. .. ..
N
.; 8 1 14 4 67 227 3 131 76 236 12 140 71 231 7 135 75 235 11 139
·'t*:
C)l
0 M H ... , .;
5 15 0 9
35
218
99
186
163
122
195
58
44
216
108
184
172 204
120 56
39
208
103
176
167
112
199
48
43
221
107
189
171
125
203
61 ~
<:\.l
" ,,3 7 11 13 154 26 250 90 152 24 248 88 144 16 240 80 157 29 253 93 '&
K I A N 74 234 10 138 72 232 8 136 64 224 0 128 77 237 13 141
<:\.l
'-'
42 106 170 202 40 104 168 200 32 96 160 192 45 109 173 205 ~
:::
G
-

C P E 214
150
182
22
118
246
54
86
210
146
178
18
114 50
242 82
223
159
191
31
127
255
63
95
212
148
180
20
116
244
52
84
~
'"
70 230 6 134 66 226 2 130 79 239 15 143 68 228 4 132 .~
38 102 166 198 34 98 162 194 47 111 175 207 36 100 164 196 ]
~
......
......
r-
~
::l
eo
lI:
g
.....
7.2 High Accuracy D/A Converters 105

Figure 7.12: The chip photograph of the 14 bit current steering CMOS DIA converter

7.2.2.4 The Layout

To obtain a 14 bit intrinsic accuracy, the layout of the chip has been optimised. Some
important issues are given:

• At layout level the D/A converter is subdivided into three functional blocks as
to minimise any coupling that could otherwise occur between the digital and
the analog part of the chip. The blocks are placed in the following way : the
thermometer decoder at the top, the swatch array in the middle and the current
source matrix at the bottom of the chip.

• Two separate power supplies have been used that are decoupled on chip by a
2.5 nF capacitance.

• Under the power supply lines and inside the swatch cells a decoupling capac-
itance of 750 pF is inserted. The swatch array (and the current source array)
have been automatically generated by the Mondriaan tool [VdPla CICC98].
106 Realisations

• The output signal has been shielded from the influence of other busses by using
a similar comb structure as was discussed for the 12 bit design.

• The analog and the digital part of the chip have separate clock drivers. A binary
tree has been used to distribute the analog clock over the chip as to minimise the
clock skew between the different latches in the swatch array.

• To minimise the error introduced by edge effects, three dummy rows and four
dummy columns have been added at each side of the current source matrix.

• A single current source transistor has a current that is equivalent to 4 LSB. Since
its width to length ratio is extremely small, its layout has been folded three times
to obtain an acceptable aspect ratio for the current source cell and current source
array.

The chip has been processed in a single-poly, triple-metal 0.5 Ilm CMOS process.
The chip photograph is shown in fig.7 .12. The total chip area (bonding pads included)
is only 13.1 mm 2 .

7.2.2.5 Measurements

7.2.2.5.1 Static measurements The measured INL and DNL performance of the
14 bit D/A converter are shown in fig.7.13.a and fig.7.13.b. From this figure it can be
concluded that the INL error is smaller than 0.3 LSB and the DNL error is smaller
than 0.2 LSB, which proves the 14 bit intrinsic accuracy of the circuit and this without
the use of any tuning or trimming.

7.2.2.5.2 Dynamic measurements The dynamic measurements were performed

with an HP 3585 spectrum analyser having a frequency range of 40 MHz, and having
a guaranteed dynamic range of 80 dB, with a typical value of 84 dB . All measurements
have been performed with a single power supply of 2.7 V.
First, the SFDR of the DIA converter is given as a function of the input signal
frequency for a fixed update rate of 150 MS/s. As can be seen from fig.7.14.a, a
SFDR higher than 80 dB can be obtained for a sinusoidal input signal up to 800 kHz
and higher than 70 dB for signals up to about 2 MHz. The SFDR as a function of the
update rate is given in fig .7.14.b for a full scale sinusoidal input signal of 500 kHz.
The SFDR remains well above 80 dB for update rates up to 150 MS/s. Fig.7.15 .a
and fig.7.15.b show the output spectra for the 14 bit D/A converter at an update rate
of 150 MS/s for an input signal of 500 kHz and 5 MHz. In the first case, the SFDR
equals 84 dB (no measurable spurs occurred) while in the second case the SFDR is
dominated by both the second and the third harmonic and equals 61 dB.
7.2 High Accuracy D/A Converters 107

0.8

0.6

0.4

iii' 0.2
en
:::!.
..J
3':
(.)
~ -0.2

-0.4

-0.6

-0.8

_1L-__ ~ ____ ~ ____- L_ _ _ _J -_ _ _ _~ _ _ _ _L -_ _

~ ____~

o 2048 4096 6144 8192 10240 12288 14336 16384

DAC Input Code

(a) The measured INL performance of the 14 bit D/A converter

0.8

0.6

0.4

iii' 0.2
~
..J
Z
C
(.)
~ -0.2

-0.4

-0.6

-0.8

_1 L-__ ~ ____- L_ __ _- L_ __ _ ~ _ __ _L -_ _~ ____ ~ ____ ~

o 2048 4096 6144 8192 10240 12288 14336 16384

DAC Input Code

(b) The measured DNL performance of the 14 bit DIA converter

Figure 7.13: The static performance of the 14 bit DIA converter

108 Realisations

resolution 14 bit
update rate 150 MS/s
INL error 0.3 LSB
DNL error 0.2 LSB
SFDR (2MHz@150MS/s) 70 dB
SFDR (500kHz@200MS/s) 70 dB
power consumption 300mW
active area 13.1 mm 2
process 0.5 f.Lm

Table 7.4: Summary of the 14 bit DAC performance

The measured power consumption is 70 mW at a 500 kHz output signal and

300 mW at a 15 MHz output signal.

7.2.2.6 Conclusion

As was the case for the 12 bit design, the main goal of realising this chip was to in-
vestigate the static behaviour of high resolution current steering D/A converters. This
chip is unique in the sense that it was the first design (to the author's knowledge) that
achieved the presented 14 bit specifications without the use of any tuning, trimming or
calibration circuits in CMOS technology [Bugej JSSC99]. This chip proves the possi-
bility of designing D/A converters with a resolution of 14 bit based on the mismatch
behaviour of the current sources. However, it has to be noted that the layout plays
a significant role in achieving such a state-of-the-art performance. The measurement
results are summarised in table 7.4.
7.2 High Accuracy DfA Converters 109

80

75

iii'70
~
II:
~
Ul65

60

55

Input frequency [Hz]

(a) The SFDR as a function of the input signal frequency @ )50MS/s

update rate

85,---.----.---.----.---.----.---.----.---.---~

80

75

iii' 70
~
II:
~ input frequency = 500 kHz
Ul 65

60

55

50L---~---L--~----L- __~__- L_ _~_ __ _L-__~__~

o 20 40 60 80 100 120 140 160 180 200
Update rate [Ms/s)

(b) The SFDR as a function of the update rate (input signal of 500 kHz
atO dBFS)

Figure 7.14: The dynamic performance of the 14 bit DfA converter

110 Realisations

Or---~--.-----~r-----~------~------~

-10 J g::150MHZ
. .
U
m
,,-20 ........ .. . .. .... ........... .. . $FDR::84dB
. .
........
>- ...... A::.0.dBFS ..
~-30
c
~-40 ..... HBW .::3Q0.Hz .
~
'b-50
CI)
a.
en -60
...
CI)

o== -70
Q.
-80

-90~----~------~------~------~----~
o 2 3 4 5
Frequency [MHz]

(a) Output spectrum at a 150 MS/s update rate (500kHz signal, 0 dBFS )

Or---~--~---------r--------,-------~

• ..... 1$::J5Q MHz ..

.....-10
(J
m
~-20
........ SFDH ::61 dB.
>- . A::.O.dBFS .
~-30
c
~-40 ....... HBW=3kHz ....

~
'b-50
CI)
a.
en -60

-90~------~--------~--------~------~
o 10 20 30 40
Frequency [MHz]

(b) Output spectrum at a 150 MS/s update rate (5 MHz signal, 0 dBFS)

Figure 7.15: Some output spectra

7.3 High Speed DfA Converters 111

Clock
7 DATA IN

Synchronization

~ 4 MSB ~ ~ 2 LSB
4 Bit thermometer Dummy
decoding logic

t t ---DOut+
Switch and Synchronizing
Dri ve r arra y
---DOut -

Centroid Current Source array

Figure 7.16: Floorplan of the 6 bit DIA converter

7.3 High Speed D/A Converters

7.3.1 A 800 MHz Ultra Low Glitch Energy 6-bit CMOS D/A Con-
verter

7.3.1.1 The Floorplan

Fig.7.16 shows the floorplan of the realised 6 bit DfA converter. This chip has a
segmented architecture, where the 2 LSB's have been implemented in a binary way
while the 4 MSB's have been implemented in a unary way. Since the decoding logic
of a 6 bit DfA converter is relatively simple, the thermometer code is generated by a
row and column decoder which has the extra advantage of allowing us to target higher
update rates. The synchronisation of the control signals of the selection logic and the
use of a deglitch driver circuit placed immediately before the switches has led to a
very low glitch energy specification.
112 Realisations

AVT 12 mVfLm
All 1.9 %fLm
a(I)j I 2%
(VGS - VT)cs 0.8V
hs 20 rnA
segmentation 4-2
(W j L)cs 6fLmjO.7 fLm

(W j L)sw 6fLmjO.7 fLm

technology 0.5fLm

Table 7.5: The unit current cell specifications for the 6 bit DAC

7.3.1.2 Design of the swatch cell and the thermometer decoder

The relation between the gate-width Wand the gate-length L of the current source
transistor and the process technology, the full scale current of the DIA converter and
the VGS of the current source is given by:

a 0
L
2
= -
y
+ -(VGS
y
- VT)
2

W2 = ay + oy (7.3)
(VGS - VT)4 (VGS - VT)2

a = 4AtT 0= A~ hOTAL
2(a;I)2 2(a;ll)2 y = 2N-l K P

where a (I) j I is the relative unit current source standard deviation, A VT and All are
mismatch related technology constants and N is the number of bits.
For this design, the gate overdrive voltage of the current source transistors has
been chosen to be 0.8 V. The dimensions of the current source transistor have been
calculated for an implementation in a standard 0.5 fLm technology with a full scale
current of 20 rnA and an INL yield of 99.7 %. The gate-width equals 6 fLm and the
gate-length equals 0.7 fLm. An overview of the unit current cell dimensions is given
in table 7.5.
A very low glitch energy has been obtained by synchronising and adjusting the
input signals of the switching transistors of the D/A converter. Fig.7.17 shows the
circuit of the flipflop together with the driver. The master-slave flipflop has been
designed to minimise the clock feedthrough and to maximise the achievable speed.
The core of this flipflop is based on the combination of two dynamic single transistor
clocked latches (DSTC-2-p/DSTC-I-n [Yuan VLSI96]). However that combination
7.3 High Speed DIA Converters 113

suffers from races under certain conditions (high clock and changing input signals).
Therefore the clock transistor of the master latch has been replaced by the clocked
pass-transistors MIa and Mlb. Additional level restores have been placed to optimise
the speed. After the master-slave flip flop a driver circuit has been placed that de-
termines the crossing point of the switch input signals [Basto CICC96]. The digital
feedthrough through the CCD capacitance of the switches is minimised by reducing
the voltage swing at the input of the switch transistors. This has been realised by
taking an appropriate value for the VSS voltage of the driver.

7.3.1.3 The switching scheme

Since in this case the current source array is relatively small, no complicated switching
scheme has been implemented. The current of a unary current source equals 4 times
the LSB current. Four separate current sources have been placed around the center of
the array. A representation of the switching scheme is given in fig .7.18. The boxes
indicated with a 'B' represent the current sources used to implement the binary bits
and the box indicated with a 'M' represents a transistor that is not used as a current
source but that is configured as a MOS diode which acts as a biasing reference for the
current source array.

7.3.1.4 Layout

The chip photograph of the 6 bit O/A converter is shown in fig.7.19. The different
building blocks in the layout are the row and column decoder, the switching cells
(consisting of the selection logic, the flipflop and the switches) and the current source
array. The decoding logic of the 01A converter has been implemented using two
identical row and column decoders, placed symmetrically around the current source
array. This has been done to minimise the propagation delay of the control signals
generated by these decoders. Several measures have been taken to avoid coupling
from the digital part of the chip identical to the ones used in the previous designs.

7.3.1.5 Measurements

In this paragraph, the measurement set-up will be discussed in some more detail.
To generate the digital input signals at update rates (clock rates) up to 1 GS/s, a
HP 80000 datagenerator has been used. The static measurements have been per-
formed using a HP 3457 A multimeter. The dynamic measurements have been per-
formed using a HP 3585B and/or Tektronix 2755P spectrum analyser and a Tektronix
TOS 680B oscilloscope. The O/A converter itself is mounted on a ceramic substrate
 ....
....
.,.

VDD Master Latch Slave Latch DegUtch Driver

IN

Figure 7.17: The synchronising flipflop and the deglitch driver

ell
~
~
....
g'
ell
7.3 High Speed DIA Converters 115

13 15 14 12 11 M

5 7 8 11

13 5 4 2 3 12

15 7 2 1 3 8 14

14 8 3 1 1 2 15

12 3 2 4 5 13

11 8 7 5

B 11 12 14 15 13

Figure 7.18: The centroid switching scheme(B=binary, M=current reference)

in order to shield the chip from external noise coupling. This substrate is encapsu-
lated in a copper-beryllium case where all power supplies have been locally decoupled
(fig. 7.20).

7.3.1.5.1 Static measurements The 6 bit D/A converter has been measured at a
single 3 V power supply. All measurements have been performed on a single ended
output with a load resistor of 2SQ. Fig.7.21.a and fig.7.21.b show the measured INL
and DNL characteristic of the 6 bit D/A converter. From these figures, it can be
concluded that the INL error is smaller than O.lS LSB and the DNL error is smaller
than 0.13 LSB which guarantees the 6 bit intrinsic accuracy of the presented D/A
converter.

7.3.1.5.2 Dynamic measurements The full scale settling time of the D/A con-
verter is depicted in fig.7.22. The D/A converter settles within O.S LSB in a time
frame of 4.S ns. The rise time (10 %-90 %) of the D/A converter equals 1.2 ns and
the fall time (90 %-10 %) equals 2.S ns. Fig. 7.23 shows the worst case glitch energy
which has been measured at the transition from input code 3 to code 4. The measured
value for the glitch energy, including both the coupling and the code transition, equals
only 0.2 pVs. This result has been obtained due to the synchronisation of all signals
and a careful layout.
Fig.7.24.a shows the measured SFDR of the 6 bit D/A converter as a function of
116 Realisations

Figure 7.19: The chip photograph o/the 6 bit DAC

the input frequency for a 800 MS/s update rate. The SFDR remains well above the
36 dB line for input frequencies up to 15 MHz. For frequencies higher than 15 MHz,
the SFDR rapidly decreases. Fig.7.24.b shows the measured SFDR as a function of
the update rate for a full scale sinusoidal input signal of 1 MHz. The SFDR is higher
than 36 dB up to an update rate of 800 MS/s. For an update rate of 900 MS/s, a
SFDR of about 35 dB has been measured. Fig.7.25 shows the output spectrum of
the D/A converter for a full scale 12.5 MHz sinusoidal input clocked at a frequency of
800 MS/s. The overall signal to noise ratio is dominated by the second order harmonic
distortion component which is 38 dB below the signal level. The maximum measured
power consumption is only 86 mW.

7.3.1.6 Conclusion

The main focus for this DIA converter was to probe the design space for the limits in
terms of update rate. For this reason a low resolution DIA converter has been chosen as
7.3 High Speed D/A Converters 117

Figure 7.20: The measurement set-up

resolution 6 bit
update rate 800 MS/s
INL error 0.15 LSB
DNLerror 0.13 LSB
SFDR (20MHz@800MS/s) > 30dB
SFDR (lMHz@800MS/s) > 36dB

power consumption 86mW

active area 1.4 mm 2
process 0.5 fLm

Table 7.6: Summary of the 6 bit DAC peiformance

to simplify the thermometer decoder design. This design demonstrates the possibility
of achieving update rates in the order of hundreds of MHz. The next step will be to
combine both a high resolution with a high update rate. The measurement results are
summarised in table 7.6.
118 Realisations

0.8

0.6

0.4

iii'
I/) 0.2
=.
g 0
o
~-0.2

-0.4

-0.6

-0.8

8 16 24 32 40 48 56 64
DAC Input Code

(a) The measured INL performance of the 6 bit O/A converter

0.8

0.6

0.4

iii'
I/) 0.2
=.
..J
z
C
o
CI: -0.2
C

-0.4

-0.6

_1L---~----~----~----~----~----~--~----~
o 8 16 24 32 40 48 56 64
DAC Input Code

(b) The measured ONL performance of the 6 bit 01 A converter

Figure 7.21: The static performance of the 6 bit DIA converter

7.3 High Speed DfA Converters 119

005

- 005

~ -01
<>
E-O15
"0
> - 02
:;
.2- -025
:I
0
'0 -0.3

...
~
~ -0.35

:e -OA

-0.45

-0.5 ~--L....--!
-0.55
-200 - 100 0 100 200 300 400 500 600 700
Tlme[ns)

~ -0.1
.,
; -015
005

-0.05
r--
"0
> - 02
:;
.2--025
:I
0
'0 -0.3

...
~
~ - 0 ,35

:e -04

-045 I
-05 -"\.- J
-055
- 100 - 80 -00 -40 -20 0 20 40 60 80 100
Tlme[ns)

0 .05

l
0

-0.05

.
~ -0,1

E -015
!
"0
> -0.2
:;
.2- -0.25
0"
-g -0.3

....~
:e
-0.35

-0."

-0.45

-0.5 f\.-..---- .......... -~-

-O~oo 420 440 460 460 500 520 540 560 580 600
Tlme[ns]

Figure 7.22: The settling behaviour of the 6 bit Df A converter

120 Realisations

O,---,---,----r---,----,---.----.---.---.----.

-0.01

-
III
~-0.02

-
'0
>
::J
.9--0.03
::J
o
eijl-0.04
'tI

ca
III
::E
-0.05

-0.06 L -_ _"""'---_ _- ' -_ _----'-_ _- - - '_ _ _ _- ' -_ _--L-_ _---'--_ _---'._ _ _ _' - - _
-100 -80 -60 -40 -20 0 20 40 60 80 100
Time[ns]

Figure 7.23: The measured worst case glitch

7.4 High Speed, High Accuracy DIA Converters

7.4.1 A 10-bit I-GS/s Nyquist Current-Steering CMOS D/A Con-

verter

7.4.1.1 The Floorplan

Fig.7.26 shows the ftoorplan of a high speed 10 bit D/A converter. The chip consists
of a 5 bit binary and a 5 bit unary sub-DAC. For the five most significant bits, the
input bit streams are converted to a 32 bit thermometer decoded output. For the 5
bit binary LSB processing, the outputs are logically the same as the inputs. Here, a
dummy decoder has been added to minimise latency problems between the signals
generated by the MSB decoder and the binary LSB bits. Due to the 1 GHz high speed
specification, the decoder has been designed manually at transistor level taking the
layout parasitic capacitances of both the active elements and the interconnections into
consideration [VdBos JSSCOl].
7.4 High Speed, High Accuracy D/A Converters 121

35

30

25
iii'
:!Z
a: 20
Q
IL
I/)
15 "pdat~ rate = ~OO MSis

10

oL-------------~~--~J_ ________ ~ __ ~ __ ~ __ ~

10° 10' 10'

input frequency [MHz]

(a) The SFDR versus the input frequency for an update rate of
800 MS/s

50~--~--~--~----r---~--~--~----r---.----.

45

~ 40
III
:!Z
a:
Q
IL
en 35 input frequency ~ 1. MHz

30

25L---~--~----L- __- L_ _~_ _ _ _~_ _- L_ _~L-__~__~

o 100 200 300 400 500 600 700 800 900 1000
update rate [MS/sj

(b) The SFDR versus the update rate for a full scale sinusoidal input
frequency of I MHz

Figure 7.24: The dynamic performance of the 6 bit DfA converter

122 Realisations

Or------,-------,-------.------,-------.-----~

-10
iii'
~
E
2 -20
'0
C1I
Q,
I/J

-
'5

o
Q,
-30
:::J

"f! -40
:::J
I/)
g!
::E
-50

10 20 30 40 50 60
Frequency [MHz]

Figure 7.25: The measured output spectrumJor aJull scale 12.5 MHz sinusoidal input
signal @800 MSls

85 86 87 8 8 89

I I I I I
thermometer
decoder

[ clock [- switchi ng matri x

"-
'"'"' -
'"m -
...
Q)
"tl
0
0
Q)
"tl
-
><
.~

( II

E
Cl
N
r- c:::

-
iii -
>- .l:
o -
E 0
<II E .~
:::J
"tl (/)

(a) (b)

Figure 7.26: The jloorplan oj the realised 10 bit segmented DIA converter
7.4 High Speed, High Accuracy D/A Converters 123

Zimp [ohm)

- - -\1
RL RL --- f(CO) RL RL

out gm'~R:;~s L -_ _ _ _ _ __ _
out

~M. fobt
I [Hz)
Zimp[ohm)
gmsgmcasrOcasrOsrOcs \/f(CO)

\/ f(Ct)
gmsrOcasrOs ~

Rreq .------------------\ 1
fobt I [Hz)

(a) The frequency behaviour of the output impedance for a current cell with and without a
cascode transistor

Zimp [ohm]
gms =71 mS
,24 G 1-__---.. gmcas = 83 mS

rDcas =627 kOhm

rDs =337 kOh
15M rDcas = 1.8 MOh

6,SM 1,2 GHz

Cl =0,5 fF
CO=O,I pF
337 k

884k 132M 508 M 22,6 G f [Hz]

(b) The output impedance as a function of the frequency for the 10 bit
Df A converter

Figure 7.27: The output impedance of the 10 bit DIA converter design

7.4.1.2 Design of the swatch cell

To achieve a 99.7% INL yield specification, the specification for the unity current
source matching is 0.5%. Based on this value and the size versus matching rela-
tion [Pelgr JSSC89] for MOS transistors, the dimensions of the current source tran-
sistor have been calculated. For the presented design, the dimensions of the unit cur-
rent source transistor are given by a 2 {Lm gate-width and an 8 {Lm gate-length. An
overview of the dimensions of the unit current cell is given in table 7.7.
Beyond the bandwidth of the frequency dependent Zimp , a severe linearity degra-
dation is caused in the current to voltage conversion. Based on a detailed linearity
124 Realisations

Avr 8.9 mVfJ,m

AtJ 1.9 %fJ,m
a(l)/ I O.S %
(Ves - Vr)cs IV
IFs 20 rnA
segmentation S-S

(W / L)cs 2fJ,m/8fJ,m
(W / Lbs IfJ,m/0.7 fJ,m
(W /L)sw 0.SfJ,m/0.3SfJ,m
technology 0.3SfJ,m

Table 7.7: The unit current cell specifications for the JO bit DAC

LATCH CURRENT CELL

VDD
RL RL

out

clock
....L
inp

GND

Figure 7.28: The switch driver and the current cell

analysis, the realised circuit has been optimised to achieve an improved linearity be-
haviour up to the Nyquist frequency of SOO MHz. A graphical representation of this
impedance bandwidth effect is given in fig.7 .27 .a. It shows a non-cascoded and a
cascoded current cell with a qualitative bode diagram of their output impedance be-
haviour. The diagrams also indicate the required impedance value to achieve the lin-
earity specification. For a 10 bit DfA converter (SFDR of 60 dB) and a load resistor of
2SQ, this impedance level is 6.5 MQ. This high frequency output impedance design
specification is one of the critical elements in achieving the improved high frequency
linearity behaviour. The Bode diagram for this design is given in fig.7.27.b. Notice
that the value of the capacitance CO is a factor of ten smaller than the CO of the 12
bit implementation discussed in the numerical examples of chapter 4. This can be
explained by the fact that for a 12 bit DfA converter, the area of the current source
matrix is 16 times larger compared to the 10 bit implementation. As a consequence,
7.4 High Speed, High Accuracy D/A Converters 125

(b) ________~.---~-.~-------

outn
(a) QuIp

elk elk
~ ~
innJ"! I"L inp
outn
L---+-I>O--D QuIp

(c)

inn inp

Figure 7.29: Design of the riseIJall time based giga-latch

the interconnection capacitance increases significantly.

Apart from the constraint dictated by the output impedance, also the other three
effects discussed in section 5.2 (timing and feedthrough of the switch control signals
and the drain voltage fluctuation of the current source transistor) have been taken
into account in order to achieve a state-of-the-art performance. The design of the
synchronised driver circuit will now be discussed in some more detail (fig.7.28).
In [Kohno CICC95, Marqu ISSCC98, VdBos CICC98] relatively simple but ef-
fective driver circuits have been used. In those circuits, the intrinsic delay between the
two complementary outputs is used to lower the crossing point of the control signals
of the switch transistors. In the nMOS implementations, an inverter is placed after the
outputs of the driver to invert the crossing point of the differential driving voltages to a
high value. However, for very high speeds, this driver can no longer be used. The com-
bination of the intrinsic delay and the feedthrough of the steep control signals through
the gate-drain capacitance of the switches, limits the operation frequency to a few
100 MHz. The problem of the too large required time period can be solved by using
another type of driver that sets the crossing point of the control signals by using differ-
ent rise and fall times for the driver's differential output [Chin JSSC94, Wu JSSC95].
To design a high speed rise/fall time based circuit, the delay based circuit in
fig.7.29(a) has been modified. An extra pMOS input circuit (input transistor + clock)
can be placed in parallel with each of the cross-coupled pMOS transistors situated at
the top of the circuit, to obtain instantaneous charging of the output nodes with falling
126 Realisations

[ line 3 = (a and b) or c or d or 3

a b c d a b c d e

line 3 line 3

(a) (b)

Figure 7.30: Graphic representation of the logic equation for line three (L represents
a logic function, in this case a simple ORfunction)

inputs. In this way, the intrinsic delay is removed from the circuits operation as charg-
ing and discharging starts at the same moment. To deal with a low power supply and
to keep a single phase clock, the cascaded nMOS and pMOS clock transistors have
been replaced by nMOS pass-transistors in the input path. This intermediate circuit is
shown in fig.7.29(b). The combination of the Mnl Mp scaled pMOS transistors and of
the pMOS positive feedback loop, results in a rise time that is much faster than the fall
time of the driver circuit. In this way, a high crossing point of the differential outputs is
directly available at the output of the latch. Notice that also a lower crossing point can
be realised by scaling the gate-width of the pMOS and/or nMOS transistors respec-
tively down and up. The driver topology can thus be used for both nMOS and pMOS
implementations of the D/A converter. The additional feedback by the small inverters
(fig.7.29(c)) suppresses the clock feedthrough by the pass-transistors and stabilises the
synchronised inputs. The circuit is fully functional for clock speeds exceeding 1 GHz.
Since the analog part has been optimised towards a high speed, the same has to be
done for the digital part of the 10 bit D/A converter.

7.4.1.3 Design of the thermometer decoder

Designing a thermometer decoder using standard cell libraries, has the disadvantage
that the achievable operation speed is limited by the timing constraints of the used
cells. To achieve an increased update rate, the decoder has been manually designed
7.4 High Speed, High Accuracy DIA Converters 127

and has been layouted at transistor level.

Before going into detail on the derivation of the functional building blocks of the
thermometer decoder, a general view on the architecture of this decoder is given by
using as an example the logic equation of line three. This line has to be active if the
digital input code of the DIA converter is larger than or equal to three.

line3 = (a&b) v c V d v e (7.4)

where a equals the LSB, b equals the LSB+ I, c equals the LSB+2, ...
A possible graphic representation is given in fig .7.30.a. Since the digital decoder
will be implemented using CMOS circuits, fig.7.30.b shows the implementation for
an equal load using NOR and NAND blocks. The large number of inverters results
in a decoder with a large area and power consumption. These inverters can and have
been eliminated from the decoder based on the following theorem:

Xv Y = X&Y
X&Y = X v Y (7.5)

Placing an inverter after a NAND block is identical to placing an inverter at the

input of a NOR block. Since both the NAND and NOR function are present in this
design, almost all inverters can be eliminated. In fig.7 .3I.a, this is shown in more
detail. Shifting the inverter to the input of the last NANDINOR block, results in two
inverters placed immediately after each other and as a consequence these inverters can
be dropped. The same holds for the inverters of the first NANDINOR block. In this
way only the input bits have to be inverted which results in only 5 inverters for the full
thermometer decoder (fig.7.3I.b). Furthermore, placing these inverters at the input
has the additional advantage that these circuits can also act as a buffer that regenerates
the input signal. Also note that bit e has been given the same load as bit a and bit bas
to avoid any timing errors that could otherwise occur.
The remainder of this paragraph will discuss into more detail the way the logic
building blocks were chosen and how the final architecture of the thermometer decoder
looks like.

In a first step, the equations that the thermometer decoder has to realise are written
down (table 7.8).

From these equations, one can clearly see that bit e can be separated from the rest
of the equations by implementing the last logical level of the thermometer decoder as
a block that has both a NAND and a NOR function. Since the target of this design is a
simple and compact decoder, it has been investigated if the NANDINOR block could
128 Realisations

line 3 IIne3
(a) (b)

Figure 7.31: Graphic representation of the logic equation for line three

l=avbvcvdve 17 = a V b v c V d&e
2=bvcvdve 18 = b v c V d&e
3 = (a&b) V c V d V e 19= (a&b)vcvd&e
4=cvdve 20 = c V d&e
5 = «a v b)&c) v d v e 21 = «a v b)&c) v d&e
6 = (b&c) v d v e 22 = (b&c) v d&e
7 = (a&b&c) v d Ve 23 = (a&b&c) v d&e
8=dve 24 = d&e
9 = «a v b v c)&d) Ve 25 = «a v b v c)&d)&e
lO = «b v c)&d) Ve 26 = «bv c)&d)&e
11 = «a&b v c)&d) Ve 27 = «a&b v c)&d)&e
12 = (c&d) Ve 28 = (c&d)&e
l3 = «a v b)&(c&d)) v e 29 = «a v b)&(c&d))&e
14 = (b&c&d) ve 30 = (b&c&d)&e
15 = (a&b&c&d) Ve 31 = (a&b&c&d)&e
16 = e

Table 7.8: Logic equations for a 5 bit thermometer decoder

7.4 High Speed, High Accuracy DIA Converters 129

1 = a&b v c&d&e 17 = a&b v c&d v e

2 = b&c v c&d&e 18 = b&c v c&d v e

3 = a v b v c&d&e 19 = a v b v c&d v e
4 = (c&d)&e 20 = (c&d) Ve

5 = (a&b&c) v d&e 21 = (a&b&c) v d v e

6 = bvcvd&e 22 = bvcvd Ve

7 = (a v b)&(b v c) v d&e 23 = (a v b)&(b v C) v d v e

8=d&e 24 =d v e
9 = (a&b) v (b&C)&d&e 25 = (a&b) v (b&C)&d v e

10 = b&c&d&e 26 = b&c&d Ve

11 = (a v b)&d v c v d&e 27 = (a v b)&d v c v d v e

12 = (c v d)&e 28 = (c v d) Ve

13 = a&b&c v d&e 29 = a&b&c&d v e

14 = b v c&d&e 30 = bvc&d Ve

15 = a v b&c v d&e 31 = a v b&c v d v e

16 = e

Table 7.9: Re-written logic equations for a 5 bit thermometer decoder

be re-used at another level of the logic. This is the case for the first level as will be
discussed in the next paragraph. The equations have been re-written as to prove the
concept and to determine the logic functions that are necessary to make the connection
between the first and the last logic level in the decoder. The result is given in table 7.9.
Since at this point, it is already known that the last level is implemented using a
block with both a NAND and NOR function, bit e is not taken into account so that
only the first 15 equations in table 7.9 have to be considered. From these equations
8 blocks can be extracted that can fully realise the thermometer logic. In table 7.10,
these blocks are given together with the number of times they occur.
From the equations in table 7.9, it becomes clear that the first logic level of the
thermometer decoder can be built up using a combination of both the NAND and
NOR function. However, the fan-out and fan-in of each block has to be optimised
in order to achieve the hard gig a-sample timing constraint. In this case, the load of
each bit is determined by the load for bit c which requires three NANDINOR blocks
130 Realisations

logic block occurrence

avb 4
a&b 4
-
bvc 3
b&c 3
cvd 4
c&d 4
c 1
d 8

Table 7.10: First level logic

(combinations (b,c),(c,c),(c,d». Based on table 7.10, it can be concluded that each

NANDINOR block has to have a load of 4 NANDNOR blocks. Dummy blocks have
been added for combinations where this is not the case, f.e. for b v c. The intermediate
level can be realised using a four input NANDNOR block. At this level also dummy
cells have been used to create identical loads for all the logic combinations. In fig.7.32
a graphical representation of the decoder is given to illustrate its final architecture.
During the layout phase, an additional first order extraction and estimation of the
parasitic load by the interconnects, has been performed at the critical points, which are
the inter-logic level connections. This has resulted in a scaling of some sub-circuits
and in additional drivers to deal with the increased capacitive load (at some points,
the interconnect capacitance became as important as the parasitics of the active el-
ements). It can be concluded, that the entire decoder is constructed based on only
three functional levels. The layout of these blocks has been optimised towards area
and symmetry in order to achieve a very high operation speed at a moderate power
consumption.
For the binary part of the 10 bit converter, a dummy decoder has been inserted
that is built up in the same manner as the thermometer decoder but that consists out of
dummy cells that pass the value of the binary input bit directly to the latches. Using
this method avoids any timing problems that could otherwise occur between the unary
and the binary part of the chip.

7.4.1.4 The switching scheme

In this design, the current source of the unary array is divided into 4 current sources
each delivering 8 times the LSB current. In every quadrant, a current source is placed
based on a centroid scheme [Nakam JSSC91). Since 31 current sources have to be
7.4 High Speed, High Accuracy D/A Converters 131

a b c d e
1

111111
~~~ ~ ~ ~n~~~~~~
J JJ1 111
/1 d/J dU//\ dU/1 1\
~~~~~~~~~~~~

~y
aVb a& b 1&e aVe 1&e -
a Ve
-

\1 \ 1 1 /
00000000 0000
0000000 dummy 0000 Gi
>
~

0000 'tI
c:
0

0000
u
Q)
Ul

T r
15 combinations 15timese 15 timese

~~~~~~~~ NAND

~~~~~~~~ NOR

~~~~~~~
~~~~~~~

I
30 combinations 1 combination

THERMOMETER DECODER
! 1
Figure 7.32: Final architecture of the 5 bit thermometer decoder

placed in each quadrant, a 6x6 array is used. The five remaining places per quadrant
are occupied by the binary bits and the bias transistor Mo, which is also placed over the
four quadrants to compensate for systematic errors. Four dummy rows and columns
have been added as to avoid edge effects. A graphical representation of the double
centroid structure of the current source array is given in fig.7.33. The shaded area
represents the dummy cells. It is clear that the use of dummy current sources is at the
cost of a considerable area increase. Simple mathematics show a 77% area increase
when using a 16x16 array instead of an 12x12 implementation.
132 Realisations

• t , • I • , I I ,
I
- ... _t- __ .., ___ •I ___ , __ ...• ___ ..I __
~
, __ . .'
.~
"
. __ .... _ . . . ___ .I _ _ ..... __ • __ _

Mo BO BO BO BO Mo
---:-- --,---
16 14 14 16
8 4 2 6 6 2 4 8
.
5 1 3 7 7 3 1 5
13 15 15 13
-
3 B2 B1 B1 B4
B2 B1 B1 B4
13 15 15 13
......-
5 1 3 7 7 3 1 5
-:. "

8 4 2 6 6 2 48
16 14 14 16
Mo BO BO BO BO Mo
, ,
.... -:- - - , - -- i -- -f'- --;- .. --,--" T" --i""" - .... ,_ ..... -- -r"" -.- .... + .... -:---
: : :: :::: :: ::

Figure 7.33: The double centroid switching scheme

Figure 7.34: The chip photograph of the high speed 10 bit DIA converter
7.4 High Speed, High Accuracy DfA Converters 133

7.4.1.5 The layout

• The coupling between the digital and the analog part of the chip has been min-
imised. This is not only done by using different power supply lines but also
by placing guard rings around the analog and the digital part of the chip and
by using a separate array for the switches together with their drivers. Another
advantage of these separate arrays is that the layout area of a unity cell in the
current source array can be minimised. In this way the distances between the
transistors are reduced resulting in improved matching properties.

• To reduce the voltage drop in the ground line of the current source transistors,
wide supply lines are used. These are drawn on top of the transistors together
with the interconnections needed to implement the switching scheme. In this
way, a very compact current source array can be realised. Special care has been
taken to realise a symmetrical interconnection array in order not to degrade the
matching performance.

• To avoid any edge effects, the current source array has been expanded with a
number of additional rows and columns.

• A multiple number of bonding pads is used at the output of the D/A converter
as to lower the inductance of the wire bonding and as a result to minimise any
ringing effects that could otherwise occur.

• Wherever possible, all interconnections have been made identical. In this way,
no timing and/or load differences have been introduced.

Throughout the whole design, layout parasitics have been taken into account. They
have been manually extracted at each critical node and iterated in the electrical
simulations. Symmetry was not only introduced for the interconnections between
any of the digital logic blocks, but in the whole layout (for e.g. the interconnection
between the switch driver and the switch transistors). Dummy switch transistors are
used to match the load of the latch for the binary bits. Another solution would be to
scale the binary latches, proportional to the load. But as it is extremely difficult to
scale the parasitics of the interconnections in the same way, the dummy load topology
has been chosen. Much attention has been paid at the final layout of the chip, resulting
in a very compact chip. The presented 10 bit D/A converter has an active area of only
0.35 mm 2 . Fig.7 .34 shows achip photograph of the realised design.

7.4.1.6 Measurement results

7.4.1.6.1 Static measurements All measurements have been performed on a sin-

gle ended 50Q double terminated output. The analog voltage supply is 3 V , while the
134 Realisations

digital part of the chip operates at only 1.9 V. Unless otherwise stated, the full scale
output current is 16mA in all measurements. Fig.7.35.a shows the measured INL pro-
file versus the input code and fig.7.35.b shows the measured DNL profile of the 10 bit
CMOS D/A converter. The INL error is smaller than 0.2 LSB while the DNL error
equals 0.14 LSB which proves the intrinsic 10 bit accuracy. Both the INL and the
DNL error specification have been measured for several values of the bias current of
the DIA converter.
[n fig.7.36, it is shown that the INL error stays smaller than 0.5 LSB for bias
currents as low as 1 rnA (=full scale current) and as large as 27 rnA. It also shows that
the performance improves with increasing current. This is evident since the relative
current accuracy improves with increasing VGS - VT. For full scale currents larger
than 4 rnA, the INL error is even smaller than 0.25 LSB.

7.4.1.6.2 Dynamic measurements The single tone output spectrum has been mea-
sured for several values of the signal frequency and of the update rate up to 1 GS/s.
For all the measurements, a SFDR better than 61 dB has been measured in the interval
from DC to the Nyquist frequency. An overview of the measured dynamic results for
a 100 MS/s and a 1 GS/s clock are given in fig.7.37. On the horizontal axis, the rela-
tive output frequency is plotted. This relative output frequency is defined as the ratio
between the single tones fundamental frequency and the clock frequency. According
to the Nyquist theorem the maximum x-axis value is 0.5. In this way, e.g. the 0.1
value on the x axis corresponds to respectively a 10 MHz (for a 100 MS/s clock) and
a 100 MHz (for a 1 GS/s) output signal.
Fig.7.38.a and fig.7.38.b show some typical measured output spectra for the chip
operating at a 1 GS/s clock rate for a 100MHz and for a near Nyquist full scale sinu-
soidal input signal frequency.
The SFDR has also been measured as a function of the bias current. Fig.7.39
shows the measurement results for a 1 GS/s clock speed and a 100 MHz output signal.
For all full scale currents between 2 and 20 rnA, the measured SFDR was better than
60 dB. For full scale currents larger than 16 rnA , the measured SFDR is even better
than 70 dB.
High speed DIA converters used in wide band transmitter applications require a
wide dynamic range since they have to deal with multiple channels. In this case, a
multi-tone SFDR plot can give extra information on the performance capability of
the D/A converter. Most multi-tone testing consists of generating a series of equally
spaced tones having equal amplitude at a specified update rate depending on the ap-
plication. Due to the inherent D/A converters non-linearity, various spurs wiII appear
in the spectral plot caused by intermodulation products. In fig.7.40, a dual tone SFDR
measurement is shown. Two 8 rnA sinusoidal signals around 105 MHz with a 5 MHz
7.4 High Speed, High Accuracy D/A Converters 135

0.8

0.6

0.4

iii'
(/) 0.2
:::::!.
..J
3!;
()
~-0.2

-0.4

-0.6

-0.8

-1~--~----~----~----~----~--~~--~----~
o 128 256 384 512 640 768 896 1024
DAC Input Code

(a) The measured INL performance of the to bit DI A converter

0.8

0.6

iii'
(/)
:::::!.
..J
Z
C
()

~
-0.4

-0.6

-0.8

_1L---~-- __ ~ ____- L_ _ _ _ ~ ____ ~ ____ ~ __ ~ _ _ _ _-J

o 128 256 384 512 640 768 896 1024

DAC Input Code

(b) The measured DNL performance of the 10 bit DIA converter

Figure 7.35: The static performance of the 10 bit DI A converter

136 Realisations

0 . 6r----,-----,---~--~---~--

iii'
'"
=.0.4
II:
o
II:
II:
WO.3
..J

::: :
Z
o
oi:S 0.2
..J INL
i!:
DNL
0.1

~L---~--~--~--~--~~-~
10 15 20 25 30
full scale current [mAl

(a) The measured INL and DNL versus the full-scale

current

IFS=26.66mA IFS=26.66mA
0.2r--_---,--~-~~-_-__,

--O.20~---:2:::oo:----::.oo~---:600=---=SOO:::----:-IOOO~----",.!2oo· 200
DAC Input Code

(b) The INL profile for I FS = 27mA (c) The DNL profile for I FS = 27mA

IFS=lmA IFS=lmA
0.5r--_-_-~--~-_-..,

0.'
0.3

~-0.1
0_0•2

-0.3

-0.'
-O.50L--2:-:-oo:---40-0--60~0:---SO":'0-~L---' 1200
DAC Input Code

(d) The INL profile for I FS = ImA (e) The DNL profile for I FS = ImA

Figure 7.36: The INL and ONL error as a function of the full scale current for the 10
bit OfA converter
7.4 High Speed, High Accuracy D/A Converters 137

71

69

iii' 67
~
[[
0 65
u..
en
63

61

59

57

55
0 0.05 0.1 0 .15 0.2 0 2. 5 0.3 0 3. 5 0.4 0.45 0.5
fs/fel

Figure 7.37: The measured SFDR for a conversion rate of 100 MS/s and 1GS/s

spacing have been applied to the DIA converter at an update rate of 1 GS/s . The
measured SFDR equals 65 dB .
The power consumption has been measured for a 490 MHz input signal at a sample
frequency of I GS/s. The digital part of the chip (the regenerative buffers at the input,
the clock driver, the two decoders and the switch driver) consumes only 62 mW from
a 1.9 V power supply, while the analog part consumes between 6 and 60 mW for a full
scale output current between 2 and 20 rnA. For a 16 rnA full scale current, for which
most of the measurements were done, the total power consumption equals 110m W.

7.4.1.7 Conclusion

This DIA converter achieves a state-of-the-art static and dynamic performance. Mea-
surements indicate that this chip has an intrinsic accuracy of 10 bit and a SFDR higher
than 60 dB over the Nyquist frequency range up to a 1 GS/s update rate. Table 7.11
gives an overview of the realised performance. This is to the author's knowledge the
first current steering D/A converter that is published in literature [VdBos CICCOO]
which achieves such a broadband dynamic performance.
138 Realisations

o
~ -1 0
E
ED
~ -20
E
2 -30
U
~ -40

-
CII
:;
Co -50
::I
o -60
"~
~ -70
nI
CD
::E -80

-90
o 100 200 300 400 500
frequency [MHz)

(a) The output spectrum for a 100 MHz signal at a IGS/s clock

0
-10
E
ED
~
-20

-.
E -30
::I

u
-40

-
CD
Co
CII
::I
-50
Co
:; -60

"..
0
CD -70
::I
CII
nI -80
CD
::E -90
-100
0 100 200 300 400 500
frequency [MHz)

(b) The output spectrum for a 490 MHz signal at a I GS/s clock

Figure 7.38: Some measured output spectra of the 10 bit DIA converter
7.4 High Speed, High Accuracy D/A Converters 139

74

72

70

m 68
~
a::
0 66
LL
C/)

64

62

60

58
0 2 4 6 8 10 12 14 16 18 20 22
full scale current [rnA]

Figure 7.39: The measured SFDR versus the full scale currentfora signal of 100 MHz
at a 1GS/s update rate

-10

E
III
-20
~

-
E -30
...
::l
CJ

--
CII
Q. -40
C/)

::l
Q. -50
::l
0
'C
...::lCII -60
Ul
ca
CII -70
==
-80

-90
85 90 95 100 105 110 115 120 125
Frequency [MHz]

Figure 7.40: A dual tone spectrum measured at a clock rate of 1GSample/s

140 Realisations

resolution 10 bit
update rate 1000 MS/s

INL error 0.2LSB

DNLerror 0.14 LSB
SFDR (50MHz@100MS/s) 64 dB
SFDR (500MHz@IGS/s) 61 dB

power consumption 1l0mW

active area 0.35 mm 2
process 0.35 fJ.,m

Table 7.11: Summary of the 10 bit DAC peiformance

AVT 8.9 mVfJ.,m

AfJ 1.9 %fJ.,m

a(l)/1 0.25 %
(VGS - VT)cs IV
1FS 20mA
segmentation 5-7

(W /L)cs 1.8fJ.,m/30fJ.,m
(W / L)sw 0.5fJ.,m/0.7fJ.,m
(W / L)cas 0.5fJ.,m/l.4fJ.,m
technology 0.35fJ.,m

Table 7.12: The unit current cell specifications for the 12 bit DAC

7.4.2 A 12-bit 500-MS/s Current-Steering CMOS D/A Converter

7.4.2.1 The Floorplan

Fig.7.41 shows the ftoorplan of the 12 bit 500 MS/s CMOS D/A converter. The
5 MSBs are converted using the unary approach while the 7 LSBs are converted using
the binary approach. Using this architecture, a trade-off between a good static and dy-
namic performance and a moderate power/complexity of the D/A converter has been
achieved.
7.4 High Speed, High Accuracy DIA Converters 141

Bl B2 B3 B4 B5 B6 B7 Clock B8 Bl0 Bll B12

Thermometer Decoder

ill)(LID CL§) CL§) CL§) (LID (LID (LID

OUTPUT L-.----r----y---.--..--..--r----' (LID~CL§)CL§)(LIDCL§)(LID(LID
(LID(LIDILSJCL§)(LID~~~
(hID(hID~~(LID~~
OUTPUT ~LJLl----.l---.l.---.l.---.l._ _ _ __ _ _ _ __ -':o::Di:I:iI.rncrncm:iD::.:ii:IIIl~

o
o 0 0
00 o
o

Current Source Array

0 0 0
00
o

Figure 7.41: The jloorplan o/the 12 bit DIA converter (LS = latch and switch)

7.4.2.2 Design of the swatch cell and the thermometer decoder

Based on the combination of a 99.7% yield specification for the D/A converter and
the transistor mismatch equations [Pelgr JSSC89], the dimensions of the unity cur-
rent source have been determined (W=1.8 J.lm, L=30 J.lm). An overview of the di-
mensions of the unit current cell is given in table 7.12. The dynamic performance
of the DIA converter has been obtained by the use of a well designed synchronised
switch driver and by a careful design of the DAC's output impedance as to minimise
any non-linearity caused by its frequency dependent value. To obtain a second order
harmonic distortion that is better than 72 dB , the required output impedance of the
DI A converter has to be larger than 100 M Q over the frequency area of interest (here
250 MHz). To achieve such a hard requirement, the frequency dependency of the out-
put impedance has been optimised by using a cascoded current source (efr. chapter
5). Fig.7.42 shows the basic schematic of the current cell and the switch driver. To
achieve the very stringent impedance requirement, the cascode transistors have twice
the minimal gate-length, as a result of the design trade-off between the resistive output
impedance (required large value) of the D/A converter and the parasitic capacitance at
the internal node (required low value).

The same thermometer decoder architecture has been chosen as for the 10 bit
design. The NANDINOR circuits of the last logic level have been adjusted to drive
142 Realisations

inp inn

SWITCH DRIVER

CURRENT CELL

Figure 7.42: The current cell and the switch driver circuit

a higher load. Furthermore, symmetry has been fully exploited both at the logical
design level as at the final layout stage. A dummy decoder has been inserted for the
binary bits as to avoid timing problems.

7.4.2.3 The switching scheme

Apart from the random matching errors, the systematic errors caused by technologi-
cal, electrical and temperature gradients over the die have been compensated by the
implementation of a special triple centroid switching scheme. Since the first 7 LSBs
are implemented in a binary way, the value of the unary current source equals 128
times the LSB current (hSB)' This unary current source has been split up into 16
current sources with a value of 8* hSB. The current source array has been divided
into 16 squares and the current sources are placed symmetrically around the center of
each square as is indicated in fig . 7.43. As a result, any two dimensional symmetrical
and/or graded error is fully compensated. Four additional dummy rows and columns
have been added to create identical surroundings for the current sources situated at the
edge of the current source array.
7.4 High Speed, High Accuracy DIA Converters 143

symmetri~

graded erro r =========--rC

=n====-====

, 2 2
, , 2 2
,
878 Mo M 8 ••
.78 Mo M 8

, , , ,
2 2 2 2

II II .2 B3 B1 B1 8 1 8 1 • 2 II M•
M Mo .2 B4 e1 91 8181 831:12 II II

, 2 2
, ,
2 2
,

,
.,.
87

,
M M.
M II

,
•••
8' •

,
, , 2 2

Figure 7.43: The triple centroid switching scheme

7.4.2.4 The layout

The chip has been realised in a single-poly five-metal layer standard 0.35 {tm CMOS
technology. The analog circuits are isolated from the noise generated by the digital
part of the chip by the use of guard rings, separate power supplies and by placing the
latches in a separate array from the current sources. Furthermore, all the intercon-
nections between the different building blocks of the thermometer decoder have been
made identical and have been put on top of the blocks. The same principle has been
used for the analog part of the chip. The routing needed for realising the switching
scheme has been done on top of the current source array. In this way, the additional
silicon area used for interconnect purposes has been strongly reduced, resulting in a
very compact chip. The total active area of the 12 bit D/A converter is only 1 mm 2 .
Fig.7.44 shows a chip photograph.
144 Realisations

Figure 7.44: The chip photograph of the 12 bit DIA converter

7.4.2.5 Measurement results

7.4.2.5.1 Static measurements All measurements are single ended and have been
performed with a 3 V analog power supply and a 2 .2 V digital power supply. The
load resistor equals 25Q. Fig.7.45.a and fig.7.45.b show the measured INL and DNL
profile of the 12 bit D/A converter. The INL error is better than 0.3 LSB proving the
12-bit accuracy. The DNL error is better than 0.25 LSB.

7.4.2.5.2 Dynamic measurements The dynamic performance of the presented DIA

converter is summarised in fig.7.46 and fig.7.47. In fig.7.46, the SFDR for differ-
ent update rates as a function of the input signal frequency is given. At an update
rate of 500 MS/s, the SFDR is still 62 dB for a sinusoidal input signal of 125 MHz.
The dynamic performance of the presented DIA converter is better than all recently
in open literature published 12 bit current-steering D/A converters [Basto CICC96,
7.4 High Speed, High Accuracy D/A Converters 145

0.8

0.6

0.4

iii'
(f) 0.2
:::!.
....I
iii:
U
~-0.2

-0.4

-0.6

-0.8

_1L-__ ~ ____ ~ ____ ~ ____ ~ ____ ~ __ ~~ __ ~ ____ ~

o 512 1024 1536 2048 2560 3072 3584 4096

DAC Input Code

(a) The measured INL performance of the 12 bit OfA converter

0.8

0.6

0.4

iii'
(f)
:::!.
....I
Z
C
U

'"
C

-0.6

-0.8

_1L-__ ~ ____ ~ ____ ~ ____ ~ ____ ~ __ ~~ __ ~ ____ ~

o 512 1024 1536 2048 2560 3072 3584 4096

DAC Input Code

(b) The measured ONL performance of the 12 bit OfA converter

Figure 7.45: The static performance of the 12 bit D/A converter

146 Realisations

80

70

iij'60
~
a:
c
LL
(/) 50

40

30

20~~~~--~~~~~~~~~~w-~~~~~~~

10-' 10- 1 10° 10' 10'

fsignal [MHz]

Figure 7.46: The SFDR as afunction of fsignal for different update rates

VdBos CICC98] (to the author's knowledge). Fig.7.47.a and fig.7.47.b show the mea-
sured output spectrum for a 1 MHz and a 125 MHz sinusoidal output signal at an
update rate of 500 MSfs. The SFDR for the 1 MHz signal equals 70.5 dB while the
SFDR is still 62 dB for a 125 MHz output signal.
To give a more complete image of the dynamic performance of the presented DfA
converter in comparison with existing 12 bit designs, fig.7.48 is given. Fig.7.48.a
shows the SFDR in function of the update rate for a 1 MHz output signal. The mea-
surement results of [Marqu ISSCC98] are also indicated on the same figure. It can be
clearly seen that the SFDR for the 1 MHz output signal remains above 70 dB up to a
600 MSfs update rate for the presented Df A converter where previous designs reach
this limit for update rates around 300 MSfs . Fig.7.48.b shows the SFDR in function
of the output signal for an update rate of 300 MSfs in order to make a further compar-
ison with [Marqu ISSCC98] possible. This figure clearly shows the superior dynamic
performance of the presented DfA converter. In fig.7.49, the maximal reported SFDR
is shown in function of the input signal frequency for different 12 bit designs. It
can be concluded from this figure that the presented chip has a dynamic performance
competitive with the best chips on the market [datasheet AD9753, datasheet AD9752,
datasheet AD9765] for output signals up to 50 MHz. The power consumption has
been measured for a near Nyquist full-scale sinusoidal output signal at a 500 MSfs
update rate and equals 110 mW. The digital part of the chip consumes 63 mW.
7.4 High Speed, High Accuracy D/A Converters 147

-10
E
III -20
:!:!.
E -30
2

..'S..
t> -40
c.
-50
c.
'S -60
0

....
-0
~ -70
~

-80
~
-90

-100
O.OOE+OO 2.00E+06 4 .00E+06 6.00E+06 8.00E+06 1.00E+07
frequency [Hz)

(a) The measured output spectra for a IMHz output signal at a 500MS/s update rate

o
-10
E
~ -20
E
2 -30

..
t>
~ -40

"[ -50
:;
o
-0 -60
f

..
::I
~ -70
~
-80
-90 L -________________________________________________ ~

O.OOE+OO 5.00E+07 1.00E+08 1.50E+08 2.00E+08 2.50E+08

frequency [Hz)

(b) The measured output spectra for a 125MHz output signal at a 500MS/s update rate

Figure 7.47: Some measurement spectra of the 12 bit D/A converter

148 Realisations

80r---~---r--~----r---~--~--~---- __--~--~

in
~
a:
cLA.
If)

100 200 300 400 500 600 700 800 900 1000
update rate [MS/s]

(a) The SFDR (@ 1MHz output) versus the update rate

80r---~-----r-----r----~---- __--~----~----~

in
~
a:
cLA.
If)

35

30L-__ ~____ ~____ ____J -_ _ _ _L -_ _

~ ~~ _ _- J_ _ _ _ ~

o 20 40 60 80 100 120 140 160

fsignal [MHz]

(b) The SFDR (@300MS/sclock)versusthe output signal

Figure 7.48: The SFDR as a function of the update rate and the input signal frequency
7.5 Low Power High Speed D/A Converters 149

85,------.-----,------,------,------,------r-----.

Iii'
~
a: VdBos ISSCCOl
cLL
en 60

55

50
VdBos
CICC98
45

40

35
0 25 50 75 100 125 150 175
fsignal [MHz]

Figure 7.49: The maximum reported SFDR as a function of the output signal for dif-
ferent 12 bit designs

7.4.2.6 Conclusion

This D/A converter together with the 10 bit design of the previous section validates the
fact that the dynamic behaviour of a current steering D/A converter is dependent on its
output impedance. The constraint imposed by this impedance becomes more difficult
to achieve for higher resolutions. However, this design proves that the combination of
a high resolution and a good frequency domain performance at a high update rate is
no longer an illusion. The measurement results are summarised in table 7.13.

7.5 Low Power High Speed DIA Converters

7.5.1 Introduction

Typical low power D/A converters, available in open literature and/or in major ven-
dors ' data sheets, are only functional for output signals up to at most a few 100 kHz.
On the other hand, high speed converters have been reported that are able to generate
linear output signals in the MHz range. However, these realisations have the main
drawback that they consume a considerable amount of power. The presented D/A
150 Realisations

resolution 12 bit
update rate 500 MS/s
INL error 0.3 LSB
DNLerror 0.25 LSB
SFDR (125MHz@500MS/s) 62 dB
SFDR (lMHz@500MS/s) 70 dB
power consumption 1l0mW
active area 1 mm 2
process 0.35 f1,m

Table 7.13: Summary of the 12 bit DAC performance

converter offers a unique combination of a linear high speed output signal and a low
power consumption. This is achieved by using a fully binary implementation.

7.5.2 A Low Power 10 bit fully binary D/A Converter

7.5.2.1 Floorplan

A schematic overview of the data converter chip is shown in fig.7.50. It shows the
cascoded current source matrix, the differential switches and the synchronising switch
drivers. Also an on-chip clock driver was implemented. The 10 bit D/A converter has
a fully binary topology. No thermometer decoder had to be implemented leading to a
considerable area and power consumption decrease.

7.5.2.2 Design of the swatch cell

Since this D/A converter has been implemented in the same standard 0.35f1,m CMOS
technology as the 1 GS/s 10 bit D/A converter, the dimensions of the current source
transistor are the same ( W = 2f1,m; L = 8f1,m). Also the same driver topology
has been used. An overview of the dimensions of the unit current cell is repeated in
table 7.14.

7.5.2.3 The switching scheme

In this design, all binary current sources are implemented as a number of parallel
unity current sources with common drain interconnection. Thanks to the symmetrical
7.5 Low Power High Speed D/A Converters 151

B10 Clock

Differential Switches & Synchronization

B8

e"'
c:
32 x 32 array
o"
<J
>-
E
1024 unity current sources B7

E
"
"0
N
2'Ounity cells

B6

B1 B2 B3 B4 B5

Figure 7.50: Topology of the realized 10 bit binary DAC

AVT 8.9 mV f.Lm

AJ'l 1.9 %f.Lm
a(l)1 I 0.5 %
(VGS - VT)cs IV
hs 20 rnA
segmentation 0-10

(W 1L)cs 2f.Lm/8f.Lm
(W 1L)cas If.LmI0.7 f.Lm
(W 1L)sw O.5f.LmI0.35f.Lm
technology 0.35f.Lm

Table 7.14: The unit current cell specifications for the 10 bit DAC
152 Realisations

current source pattern, the systematic effects have been minimised. Fig.7 .51 shows the
switching scheme for the implemented chip. In both the horizontal and the vertical
direction, additional dummy current source transistors have been placed to provide
identical surroundings for the current sources at the edge of the array (the shaded
area). It can be noticed that the insertion of the dummy rows and columns implies a
50 % area increase of the current source array (42x36 versus 32x32).

7.5.2.4 The Layout

The chip microphotograph is shown in fig.7.52. The chip has been implemented in
a standard 0.35 11m CMOS process. Due to the fully binary architecture of the D/A
converter, the layout has proven to be less complex than the previous ones. However,
also here the decoupling between the noise generated by the digital part of the chip
and the analog part is essential. In this design symmetry has been exploited wherever
possible. Dummy loads have been placed at the driver level for the LSB's. In order
to minimise the timing inaccuracies internally in the synchronising drivers, the MSB
drivers consist of a parallel sequence of less significant bit drivers.

7.5.2.5 Measurement Results

7.5.2.5.1 Static measurements All measurements have been performed on a single-

ended output. A 2 .7 Vpower supply has been used for the current cell and for the clock
driver. The load resistor equals 25Q. The synchronising circuits before the differen-
tial switches operate at a reduced 1.3 V in order to optimise the dynamic performance.
For a 30 MS/s near Nyquist operation, the synchronising latches consume 661lA and
342 IlA is used for the clock driver, resulting in a total digital power consumption
as low as 1 mW. The analog full scale output current (FSOC) is 2.5 rnA, resulting in
a maximal 7.8 mW total power consumption (FSOC*2.7 V+ 1 mW) at the 30 MS/s
Nyquist operation. Five chips have been measured. For all the samples, both the INL
and DNL error were better than 0.5 LSB (fig.7.53 and fig.7.54).

7.5.2.5.2 Dynamic measurements The dynamic performance of a current steer-

ing DIA converter is dependent on the amount of segmentation. The dynamic error
due to the switching operation is proportional to the number of simultaneous switch-
ing current sources. Also the performance sensitivity to the timing accuracy of the
switch control signals increases with lower segmentation. These elements indicate
that a design trade-off exists between a high SFDR, a low area and a low power con-
sumption. Due to a detailed analysis of the non linearity effects for current steering
D/A converters and an appropriate switch driver design, good dynamic specifications
have been achieved.
7.5 Low Power High Speed D/A Converters 153

[It J' 1I 1I
,I I I I II II

I ~. • h ,' " ,~. ·I';-"jo.' "," ' :' ,, - ::

I ":'"~",'" •••• "-"~ " '.'," . ~.

~~ ~~~ ~~oo~ :~~~ ~~oo~

~~ ~~~~~~oo~~~~I ~, ~oo
o~o
o_~- 0 0 0
_~_~_~_~C~
::P 0

, oco a- a-._r-_a-._
0 0 0 00.0 I ~ 0-
- 00 - -
154 Realisations

Figure 7.S2: The chip photograph o/the 10 bit DIA converter

The measured SFDR at a 30 MS/s and at a SO MS/s update rate is shown in

fig.7.SS.a. It indicates that a better than 60 dB SFDR is achieved for all input sig-
nal frequencies up to a IS MHz. To relax the system specifications on e.g. filters in
the signal path, it can be beneficial to use a higher clock speed. Fig .7.SS.b shows the
measured SFDR for a 1 MHz signal for various values of the update rate. It shows that
more than 60 dB is achieved up to an update rate of 800 MS/s. Fig.7.S6 shows some
typical measured output spectra for a Nyquist, a Nyquist/2 and a Nyquist/SO input sig-
nal frequency at a 30 MS/s update rate. They all achieve more than 60 dB SFDR over
the whole Nyquist frequency band.
7.5 Low Power High Speed D/A Converters 155

0.5 0.5

OA OA

0.3 0.3

0.2 0.2

m 0.1 ii=. 0. 1
=.
.... ....
;!;
0 z 0
0

"
~ -O.l "
< -0.1
0
-0.2 -0.2

-0.3 - 0.3

- 0.4 -0.4

-0.5 -0.5
0 126 256 364 512 640 766 696 1024 0 126 256 364 512 640 766 696 102'
OAe Input Code OAC Input Code

0.5 0.5

OA 0.4

0.3 0.3

0.2 0.2

jj 0.1
iii
~ 0.1
=.
.... ....Z
0 0
;!; 0

"
~ -O.l
"
<-0.1
0
-0.2 -0.2

-0.3 - 0.3

-0.4 -OA

-0.5 -0.5
0 126 256 364 512 640 766 696 1024 0 126 256 384 512 640 766 6" 1024
OAe Input Code OAe Input Code

0.5

0.4

0.3

0.2

! 0.1

.... 0
;!;

"~ -O.l

-0.2

-0.3

-OA

-0.5
0 128 256 364 512 640 766 696 1024 128 256 364 512 640 1024
OAe Input Code OAe Input Code

Figure 7.53: The first 3 samples of the binary 10 bit DIA converter
156 Realisations

Figure 7.54: The last 2 samples of the binary 10 bit DIA converter

7.5.2.6 Conclusion

To prove that it is fundamentally possible to achieve state-of-the-art specifications at

the extreme low segmentation side of the design space, the realised chip has a fully
binary topology. Major important advantages of this binary implementation are the
design simplicity (very fast design cycle), the reduced power consumption and the
small silicon area. Measurements prove that this 10 bit DIA converter can be used in
many telecommunication systems since it combines a good dynamic performance in
the frequency range of several MHz (up to 15 MHz) and a low power consumption
(less than 8 mW). It is the author's belief that better dynamic specifications could have
been achieved if the layout of the clock interconnections had been optimised. In this
design unfortunately, no clock tree has been used and as a consequence significant
timing mismatches occur between the different driver circuits that normally solve the
synchronisation issues for the switch control signals. An overview of the realised
performance is given in table 7.15.
7.S Low Power High Speed D/A Converters IS7

70

65

iii'
~
2i 60
IL
(J)
't)
I!!
..
:::I
U>
GI
::IE
55

50

45

40L---~~~~~~--~----~~~~--~~~~~~----~
10' 10' 10' 107
Output Signal Frequency [Hz]

(a) SFDR versus signal frequency at a 30MS/s and a 50MS/s update rate

70,---_,--_,----,---~----.---_,--_,--~~==~==~

iii'
~
II:
o
IL
(J)
't)
I!!
:::I
U>
m
:;;
50

45

40 L----L----~ __ ~ _____ L_ _ _ _L __ _ _ _ _ __ L_ _ _ _L __ _ _ _
~ ~ ~

o 100 200 300 400 500 600 700 800 900 1000
Update Rate [MHz]

(b) The SFDR for a fixed output signal of IMHz versus the update rate

Figure 7.55: The dynamic performance of the binary 10 bit DAC

158 Realisations

0
~ -20
III
~ -40
0
0 -60
C/)
II..-80
<I:
E -100
III 0 2 4 6 8 10 12 14 16
N x 10·
@ 0
...co - 20
ti
8.
C/)
- 40

'SCo -60

'S -80
0
CII -100
.~ 0 2 4 6 8 10 12 14 16
1;j x 10·
'iii 0
II:
-20
...CII
'1J

:::l -40
I/)
co -60
CII
:: -80
- 100
0 2 4 6 8 10 12 14 16
Output Signal Frequency [Hz) x 10·

Figure 7.56: Typical measured output spectra

resolution 10 bit
update rate 30 MS/s
INL error 0.2LSB
DNL error 0.2LSB
SFDR (15MHz@30MS/s) 61 dB
SFDR (IMHz@800MS/s) 60 dB
power consumption 7.8mW
active area 0.23 mm 2
process 0.35 p.,m

Table 7.15: Summary a/the binary 10 bit DAC performance

7.6 Overview of Realised DACs 159

7.6 Overview of Realised DACs

Six different implementations have been discussed in detail. Before comparing these
DIA converters with recently published circuits, an overview is given of the most
important specifications of the presented realisations. This is done in table 7.16.

7.7 Comparison with literature

7.7.1 The Figure of Merit

To be able to compare the performance of the presented D/A converter with recently
presented current steering DI A converters, a figure of merit has been introduced
[VdBos AACD01].

FOM =
2N * is@(SFDR =
----..:.~------­
6(N - 1» (7.6)
p

where N is the resolution and P is the power consumption ofthe D/A converter and is
is the input signal frequency where the SFDR has dropped with 6 dB (=1 bit) in com-
parison with the expected result (6*N). For a 12 bit DIA converter, is is the output sig-
nal where the SFDR equals 66 dB. In fig.7.S7 this figure of merit is plotted versus the
inverse of the normalised area. On the same figure, the lines of equal FOM/normalized
area ratio are shown. It can be concluded from this figure that the presented 12 bit
D/A achieves a state-of- the-art performance in comparison to recently published 10,
12 and 14 bit D/A converters. An overview of these D/A converters is given in ta-
ble 7.17. A few remarks have to be made regarding the content of this table. First, the
update rate is the update rate given in the title of the paper and is as a consequence
not the update rate at which Nyquist specifications are realised. The is is the maximal
input signal frequency where the SFDR has dropped with 6 dB and is therefore not
always measured at the update rate mentioned in the table. The indicated power con-
sumption is the one needed to generate the is signal. The silicon area mentioned in
the table represents the active area, which is the area inside the bonding pads (bond-
ing pads excluded). For the references [Bugej JSSC99, Bugej JSSCCOO], no numbers
were found for the active area of the chip and as a consequence the area including the
bonding pads is used to calculate the figure of merit. This implies that in reality, the
points indicating the Bugeja D/A converters in fig.7.S7 are shifted horizontally to the
right yielding a better result.
 ....
0'1
Q

resolution update rate INL DNL SFDR SFDR power area

[bits] [MS/s] [LSB] [LSB] input clock SFDR input clock SFDR [mW] [mm 2 ]

12 200 O.S 0.7 IMHz 200MS/s 6S dB SOOkHz 300MS/s SO dB 140 14

14 ISO 0.3 0.2 2M Hz IS0MS/s 70 dB SOOkHz 200MS/s 70 dB 300 13
6 SOO O.IS 0.13 20MHz SOOMS/s > 30 dB 1 MHz SOOMS/s > 36 dB S6 1.4
10 1000 0.2 0.14 SOMHz 100MS/s 64 dB SOOMHz 1GS/s 61 dB 110 0.3S
12 SOO 0.3 0.2S 12SMHz SOOMS/s 62 dB 1 MHz SOOMS/s 70 dB 110 1
10 30 0.2 0.2 lSMHz 30MS/s 61 dB 1 MHz SOOMS/s 60 dB 7.S 0.23

Table 7.16: Overview a/the presented DIA converters

~
~
rIO
~
a.
c
~
 -.J
:....
\'l
9
't:I
reference resolution update rate INL DNL technology 2N jarea FOM ~
fs power area ..,
~.
[bits] [MS/s] [LSB] [LSB] [MHz] [mW] [mm 2 ] [fLm] [ljmm 2 ] [MHzjmW]
=
~
[V dPla JSSC99] 14 150 0.3 0.2 0.9 300 11 0.5 1489 49
~
[Bugej JSSC99] 14 100 0.5 0.5 20 750 14.4 0.35 1138 437 =:
~
[Bugej JSSCOO] 14 100 0.35 0.25 28 180 11.8 0.35 1388 2549 Q!
[Basto PhD] 12 250 0.5 0.5 0.2 100 1 0.7 4096 8 ::i1
=
[VdBos CICC98] 12 200 0.5 0.7 0.9 140 14 0.5 293 26
[Marqu ISSC98] 12 300 0.6 0.3 4 320 1.9 0.5 2133 5]
[VdBos ISSCCOl] 12 500 0.3 0.25 75 86 1 0.35 4096 3572
[Vital AACDOl] 12 200 0.65 0.3 20 180 2 0.35 2048 455
[Lin JSSC98] 10 500 0.2 0.1 220 125 0.6 0.35 1707 1802
[VdBos CICCOO] 10 1000 0.2 0.14 500 110 0.35 0.35 2926 4655
[Khano VLSI99] 10 400 0.35 0.25 150 90 1.2 0.6 853 1707
[Borre CICCOl] 10 30 0.2 0.2 15 8 0.23 0.35 4452 1920
[Roove AACDOl] 10 200 x x x 130 1.2 0.25 853 x
-

Table 7.17: Overview of the recently published high resolution, high speed DIA converters

.....
="
.....
162 Realisations

::E
oLL

10°L-------~--~--~~~~~~~------~--~--~~--~~~
1~ 1~ 1~
2 N/area [mm 2]

Figure 7.57: The FOM as afunction of the inverse normalised area

7.8 Conclusion

In this chapter four classes of current steering DIA converters have been discussed.
In the first section of this chapter, the design procedure to achieve a high resolution
circuit has been validated by the realisation of both a 12 bit and a 14 bit DIA converter.
All the measured samples ( and this is valid for all the designs in this chapter) have
an INL error that is smaller than 0.5 LSB. In a second stage, the limitations for the
frequency domain performance have been explored by the design of a 6bit high speed
architecture. Combining both a high resolution with a high update rate following the
described design considerations of chapter 6, has led to the realisation of a 10 bit and
a 12 bit high speed DIA converter with a static and dynamic performance that has ( to
the author's knowledge) not been published elsewhere.
Since most telecommunication systems of today do not need a bandwidth of hun-
dreds of MHz but on the contrary need a small circuit with a low power consumption,
a current steering DIA converter has been processed that has an intrinsic accuracy of
7.8 Conclusion 163

10 bit and a SFDR higher than 60 dB over a frequency bandwidth of 15 MHz. This
chip has a power consumption of only 7.8 mW.
According to a figure of merit based on power, speed and accuracy, three designs
compare favourably to all other published Df A converters.
Chapter 8

Transistor Mismatch: Evolution and

Relevance

8.1 Introduction

Measuring the electrical characteristics of a set of transistors with the same gate-length
and gate-width that are processed in the same technology, will not yield the same re-
sults. During the fabrication process small variations will occur that result in a statis-
tical variation of the transistor properties. This variation depends on the dimensions
of the matched component and its biasing conditions. This phenomenon is referred to
as transistor mismatch.
It is easy to understand that the design of high performance analog circuits such
as DfA and AID converters, reference sources, ... requires the availability of reliable
transistor mismatch models. Designers have to be able to rely on accurate simulation
tools if they want to be successful in the realisation of a circuit with a performance
that lies closely to the limits of the given technology. However, the accuracy of such
simulation tools is determined by the underlying models. At this moment, the analog
designer has to introduce large safety margins to guarantee the required performance
of the circuit leading to an unnecessary power consumption and an operation speed
reduction [Kinge CICC96]. In literature, several models have been presented that de-
scribe the mismatch characteristics of the transistor by providing the designer with the
standard deviation of the mismatch in a set of electrical parameters (like the thresh-
old voltage Vr , the current factor (3 , the mobility degradation parameter e, the bulk
threshold parameter y).
In the first part of this chapter, an overview of these models will be given start-
ing with the basic models presented by Lakshmikumar and Pelgrom [Laksh JSSC86,
Pelgr JSSC89]. However, going to submicron technologies, these models have to be
166 Transistor Mismatch: Evolution and Relevance

adapted as to explain the transistor mismatch of short and narrow devices. The mod-
els presented by Abel [Abel ISCAS93] and Bastos [Basto ICMTS95] introduce the
mobility degradation factor. The next two models that are discussed are used in cir-
cuit simulators that are commercially available on the market today. In the model
of Gotarredonna [Gotar KLUWER], the mismatch parameters are accurately fitted
by using a very general mathematical function of the channel length and width in-
stead of the well known first order law of area. The model presented by Griinebaum
[Grune KLUWER] is an extension of the spectral model of Pelgrom. Both methods
have the disadvantage that the physical causes of mismatch remain hidden behind the
mathematics but yield good results in terms of circuit simulations. The next model
described here is the model presented by Drennan [Drenn IEDM99]. In this model,
the transistor mismatch is characterised based on its underlying physical causes. The
main advantage of this model is that it can be used for process diagnosis and monitor-
ing. The last mismatch model is described by Croon [Croon JSSC02] and describes
a model that is continuous from weak to strong inversion and from the linear to the
saturation region.
The second part of this chapter discusses the extraction of the transistor mismatch
parameters for a 0.5 and a 0.4 {Lm CMOS technology and the dependency of the
transistor mismatch parameters on the used topology and the immediate surroundings.
The last part of this chapter discusses the possibility of using a current steering DIA
converter as a test structure for the extraction of the transistor mismatch parameters in
a given technology.

8.2 Model of Lakshmikumar

The first in-depth study on the characterisation and modelling of mismatch in MOS
transistors has been published in 1986 by Lakshmikumar [Laksh JSSC86]. Previous
work mainly focused on either experiments [Akyia IEE] or first crude attempts to
unravel the physical causes of transistor mismatch [Shyu JSSC84].

8.2.1 Characterisation Methodology

Since in most analog circuits the MOS transistors operate in the saturation region, the
mismatch model will be derived using the square law model :

f3 2
(8.1)
1= 2(VcS - VT)
8.2 Model of Lakshmikumar 167

This model has been chosen since it gives an adequate description of the electrical
behaviour of the device and at the same time uses only a limited set of parameters
(threshold voltage VT and the current factor f3). The drain current mismatch in the
saturation region is then given by :

a 2(t,.!) a 2(t,.f3) 4a 2(t,. VT) aCt,. VT) a(t,.f3)

-~...:...
12
=
f32
+ (VGS-VT)2 - 4 * r * VGS-VT -f3- (8.2)

where r is the coefficient that describes the correlation between the mismatches in VT
and f3. However, for the investigated technology (3 f.Lm CMOS), experimental values
for this correlation factor are very small (close to zero) and as a consequence this
factor can be omitted in eq.(8.2) , giving the following drain current mismatch model:

(8.3)

The values for the threshold voltage and the current factor are extracted from mea-
surements of the drain current as a function of the gate voltage for a small value of the
drain-source voltage. The current factor is determined by the maximum slope of the
IDS versus the VGS curve while the threshold voltage is the intercept of this slope with
the VGS axis. The terms on the right hand side of eq.(8.3) can be written as a function
of the dimensions (W,L) of the transistor based on the underlying physical phenomena
that cause the mismatch.

8.2.2 Physical causes for mismatch

8.2.2.1 Threshold Voltage Mismatch

The threshold voltage of a transistor is given by :

'"
VT=<pMS +2'"<pB +QB-QI+qD/
C (8.4)
ox
where <PMS is the gate-semiconductor work function difference, <PB is the Fermi po-
tential in the bulk, Q B is the depletion charge density, QI is the fixed oxide charge
density, D/ is the threshold adjust implant dose and C ox is the gate oxide capacitance.
The standard deviation of the threshold voltage can be calculated using the following
statistical formula for a variable X that is a function of two independent parameters
PI and P2:

(8 .5)
168 Transistor Mismatch: Evolution and Relevance

Since all parameters (¢MS, ¢B, Cox, QB, Qt, D/) are assumed to be independent,
eq.(8.4) can be rewritten as:

Based on eq.(8.4), the partial derivatives can be calculated resulting in :

The Fermi potential ¢B and the work function ¢MS are regarded as constants not
contributing to the transistor mismatch. Furthermore, it has been assumed that all the
charges mentioned in eq.(8.4) have a Poisson distribution [Laksh JSSC86]. The final
equation for the standard deviation of the threshold voltage is thus given by :

(8.8)

where W is the effective channel width, L is the effective channel length and Aox is a
parameter that has to be determined from measurement data.
The most important conclusion to be drawn from this derivation is that the
threshold voltage mismatch is inversely proportional to the square root of the effective
channel area. Measurements have been performed on both nMOS and pMOS devices
(W/L= 48/12, 24/12, 24/6, 12/6, 12/3,613 flm/ flm) to verify this equation.

8.2.2.2 Current factor mismatch

The current factor is given by :

w
f3 = fl Cox - (8.9)
L
8.3 Model of Pelgrom 169

where f.1, is the channel mobility. The standard deviation of the current factor can be
derived similar to the threshold voltage standard deviation and equals:

(8 .10)

The mobility mismatch has been mainly contributed to the non-uniformity of Qf

and since these charges have a Poisson distribution, the final equation for the current
factor mismatch is given by:

a 2 (/1f3) a 2 (/1L) a 2 (/1 W) I

f32 = L2 + W2 +W*L(A/l+A ox ) (8.11)

From eq.(8.11), it can be seen that the current factor mismatch is not solely in-
versely proportional to the square root of the effective channel area but is also deter-
mined by a factor ~2 and i2'
Also here, measurements were performed that validated
the derived equation.

8.3 Model of Pelgrom

The starting point to derive the Pelgrom model is not the wide range of possible mis-
match causes, but a mathematical treatment of classes of mismatch behaviour which
covers all (at that time) known area related physical causes.

8.3.1 Characterisation methodology

The value of a parameter P generally consists out of the sum of a fixed part and a
random varying part so that its value differs from coordinate to coordinate. If the vari-
ations are small, the average value for the parameter can be calculated as the integral
of P(x,y) over the specified area. This integral can be interpreted as the convolution of
a geometry function G(x,y) and the mismatch function P(x,y) [Pelgr JSSC89] :

(8.12)

Representing parameter fluctuations in the Fourier domain has the advantage of an

easy determination of the power contents which can be interpreted as the square of the
standard deviation of the parameter:

(8 .13)
170 Transistor Mismatch: Evolution and Relevance

Using the Fourier analysis, the geometry function Q(w x , w y ) can be calculated for
different transistor topologies. For further details, the reader is referred to [Pelgr JSSC89].
Concerning the contribution of the mismatch function P(wx, w y ) two classes of phys-
ical mismatch causes are dealt with:

• The first class is the spatial "white noise" or short distance variations. In this
class the mismatch is determined by many single events of which the mismatch
contributions can be summed and with a correlation distance that is smaller
than the transistor dimensions. Examples are the local mobility fluctuations, the
oxide charges, ...

• The second class is modelled in the Fourier domain as a fixed low frequency
contribution with a spatial frequency that is inversely proportional to the wafer
diameter. This class takes the effect of a circular parameter distribution into
account which is caused by for example the oxidation process.

Calculating the variance for two rectangular devices leads to the following result:

A2
a 2(8.P) = ---.L
WL
+ S2p D2
x
(8.14)

where Ap is the area proportionality constant and S p is the distance coefficient that
have to be determined through measurements.

8.3.2 Mismatch model

The presented drain current mismatch model is derived from the same drain current
model as used by Lakshmikumar (eq.8.1) and is given by:

a 2(8.l)
----=-- =
a 2(8.f3) 4 [a 2(8. VTO)
+ --------;:----
+ A a 2(8.y)] (8.15)
[2 f32 (VGS - VT)2

with A = J2 ¢ - VSB -,J2¢. This model uses three parameters to describe the
mismatch, namely the threshold voltage VTO , the bulk threshold parameter y and the
current factor f3. This model is identical to the one proposed by Lakshmikumar in
the previous section for transistors that operate in the saturation region and have a
bulk-source voltage equal to zero.
The mismatch contribution of the parameters VTO and y follow the mathematical
derivation in section 8.3.1 and can be written as :
8.4 Other models 171

(S.16)

Also the mobility contribution can be calculated taking into account that variations
in channel length and width are caused by edge roughness and can be modelled as
a 2(L) ex: I/W anda 2(W) ex: I/L:

a 2 (!::,.f3) A~ Ai A~ 2 2
(S.17)
f32 = W2 L + W L2 + WL + Sf3 D
which for large size devices can be simplified to

a 2 (!::"f3) A~ 2 2
f32 = WL + Sf3 D (S.IS)

From eq.(S.16) and eq.(S.17), it becomes clear that - making abstraction of the
distance component -, the expressions for the standard deviations of the mismatch
parameters are similar to the ones derived by Lakshmikumar.
In order to validate the presented model, several modules have been designed and
fabricated which contain 6 transistors of the same size: a reference transistor, a tran-
sistor at 30, 250 and 500 J-Lm spacing, a parallel and a 90 0 rotated transistor (30 J-Lm
spacing). These modules were made for both nMOS and pMOS devices with different
WIL ratios (2.4/1.6, 2.4/20, 3/3, 5/5, 20/5, 20/20 J-Lm/J-Lm). The mismatch parame-
ters have been directly extracted. Measurements show a good agreement between the
model and the measurements. Furthermore, measurement results on devices processed
in a 2.5 J-Lm technology have proven that the influence of the distance component is
only significant for widely spaced devices with a large channel area.
Although the big advantage of this mathematical derivation is that it can also be
used for other devices like capacitors, its major disadvantage is that it does not provide
the reader with any physical insight. The model is only valid if the mismatch processes
belong to the two mathematical classes that were discussed.

8.4 Other models

8.4.1 Model of Abel

The models derived by Lakshmikumar and Pelgrom are valid for devices with a gate-
length higher than 2 J-Lm . However, for short channel transistors, the threshold voltage
172 Transistor Mismatch: Evolution and Relevance

and the current factor are dependent on the channel length, introducing the need for
extended mismatch models to characterise the transistor mismatch of these small size
devices. This model [Abel ISCAS93] determines the drain current mismatch as a
function of the following four transistor parameters: Vro, y, f3 and e starting from
the equations for the drain current in the linear region and in the saturation region.
This leads to the following mismatch models
VT ~ Ves ~ VDS
--~
-- -+ + -~f3 + - - - -- -
- - -~e(Ves Vr)
- (8.19)
Ves - Vr Ves - VT f3 VDS 1 + e(Ves - VT)
based on the drain current model for the linear region
R V2
I - fJ [(\I: - V ) V _ DS] (8.20)
DS- 1 + e (Ves- Vr) es T DS 2

and
~ID -2~Vr 2~Ves ~f3 ~VDS ~e(Ves - Vr)
=
Ves - Vr
+ Ves - Vr
+f3- +VDS
- - -1- -----
+e(Ves - VT)
(8.21)

based on the drain current model for the saturation region

f3 (Ves - Vr)2
IDS = - ------- (8.22)
2 1 + e (Ves - VT)

The following two algorithms were used to extract parameter mismatch parameters
from the measured I D - Ves curves from a pair of transistors in saturation. In the first
algorithm, the ..JlD -Ves curve is considered. The slope of the this curve equals
-Jf3 /2 and the extrapolation to zero drain current gives a value for the VT . The second
algorithm uses the Newton-Raphson iteration method to determine the parameters by
fitting the ID - Ves curves.
A test chip has been implemented in a 0.8 ttm technology consisting out of five
transistor pairs with different W/L ratios. From the measurements, it could be con-
cluded that the three parameters Vro, y, e have a standard deviation of the form:

(8.23)

while the standard deviation of the current factor f3 is given by :

(8.24)

8.4.2 Model of Bastos

In [Basto ICMTS95], the influence of the mobility degradation has been taken into
account. The drain current mismatch models have been derived from eq.(8.22). This
8.4 Other models 173

model describes the transistor mismatch by using three parameters (the threshold volt-
age VT, the current factor f3 and the mobility degradation factor e).
A test structure containing a lOx 12 transistor array has been processed in a 1.2 p,m
technology. Every row contains 10 identical transistors with a different spacing. The
remaining positions are used to implement different layout structures and/or rotated
devices. Four different algorithms have been used to extract the mismatch parameters
and the results have been compared with each other through experimental data. A
short overview of these algorithms is given.
In algorithm 1, the mismatch parameters ~ VT, 1,
~e are directly extracted from
the drain current mismatch model presented in eq.(S.25).

~ID ~f3 2~ VT ~e(VGS - VT)

(S.25)
ID f3 VGS - VT 1 +e(VGS - VT)

This model can be reduced by combining the effective mobility degradation mismatch
term with the current factor mismatch term since both expressions are significant in
the same bias range (high gate-source voltage). This model will be referred to as
algorithm 2 :

~ID ~f3 2~ VT
(S.26)
ID f3 VGS - VT

Algorithm 3 and 4 were already widely known, but have been included to compare
the results with algorithm 1 and 2. In algorithm 3, a Levenberg-Marquardt iteration
method has been used to fit the measured I D versus VG S curve to determine the mis-
match parameters (eq.S.27).

I - f3 (Y. _ V )2 (S.27)
D- 2(1 + e(VGS _ VT» GS T

In algorithm 4, the line with the maximum slope tangent to the Fo versus VGS curve
is extrapolated to zero drain current, determining hereby the value of the threshold
voltage. The slope of the line is equal to If
Measurements indicate that for large transistor sizes, the four algorithms give
equivalent results. For small size transistors, the threshold voltage and the current
factor mismatch deviate significantly from the first order law of area as proposed by
Pelgrom. An extended model is presented that incorporates the mismatch behaviour
of these devices:

(S.2S)
174 Transistor Mismatch: Evolution and Relevance

For the current factor mismatch, the Pelgrom law stays valid for small size devices
if its value is extracted using algorithm 2. This algorithm yields the best results for the
drain current mismatch which can be explained by the correlation that exists between
the current factor and the mobility degradation mismatch. Note that in this case, it is
better to speak of an effective current factor mismatch since the current factor and the
mobility degradation mismatch can not be analysed separately. If both the and t:./
the ~ e parameters have been extracted (algorithm 1), an extended model of the same
form as eq.(8.28) is needed to describe the current factor mismatch:

(8.29)

8.4.3 Model of Gotarredona-Linares

In this section a mismatch model [Gotar ISCAS98, Gotar ICECS99, Gotar KLUWER,
Gotar EDLOO, Gotar ISCASOOb, Gotar ISCASOOa] is presented based on the thresh-
old voltage mismatch ~ VT , the current factor mismatch t:./,
the body factor mis-
match ~ y and the mismatch in the mobility degradation factor ~ eel! which is split
up into two components ~eo and ~ee. In the linear region the value of this parameter
is given by:

2 J.lCox ld Ro
ee!!llin = eo = e + fJ(Rs + RD) = e + ~---="::L~--=- (8.30)

for VDS « VGS - VT and taking both the source (Rs) and drain resistance (RD) into
account. In eq.(8.30), Ro is the diffusion sheet resistance per square and id is the
distance between the gate diffusion edge to the source (and drain) contact region. The
extracted value for eel! is also influenced by velocity saturation v s , resulting in

J.l VDS VDS

eel! = e + f3(Rs + RD) + (--
2vsL
- fJRD)
VGS - VT
= eo + ee * VGS - VT
(8.31)

where VDS is substituted by V DSsat = VGS - VT when the transistor is biased in the
saturation region. Rewriting this equation as a function of the channel length L leads
to the following expression:

2 J.lCox ld Ro J.l 1 VDS

eeff = e + L
+ -(-
L 2vs
- CoxidRO)----'-
VGS - VT
(8.32)

From this equation, the significance of the extra terms besides e for short channel
devices becomes clear. The mismatch of this parameter can be expressed as:
8.4 Other models 175

(8.33)

For a transistor operating in the linear region, the effective mobility degradation mis-
match equals fleo, while for a transistor operating in the saturation region fleejj
equals fleo + flee. It is clear that an extraction in both the linear (VDS = 0) and
the saturation region (VDS = Ves - VT) is necessary.
The drain current mismatch model is given by:

flIDS flf3 (1 + ()effV

2 DS)flVT (Ves - VT)fleO
IDs f3 [Ves - VT - VgS][1 + eeII(Ves - VT)] 1 + eejj(Ves - VT)
(8.34)

for the linear region based on

f3 (Ves - VT - VgS)
IDs =
1 + e (Ves - VT)
* VDS (8.35)

and for the saturation region

fl IDs flf3 (Ves - VT ) (fleo + flee)

=
IDs f3 [Ves - VT][1 +eejj(Ves - VT)] 1 + eejj(Ves - VT)
(8.36)

based on eq.(8.22).
Furthermore,

fl VT = fl VTO + fly [J2¢ + VSB - J2¢] (8.37)

A test chip has been designed in a 1 fLm process that consists out of an array of
identical cells that contain 30 pMOS and 30 nMOS transistors. Additional decod-
ing/selection circuitry has been included as to automate the measurements as much
as possible. The measurement and extraction procedure is based on 4 measurement
curves both in the linear and the saturation region (IDs(Ves) and IDs(VsB». For
further details, the reader is referred to [Gotar KLUWER]. The following parameters
have been extracted: (T(fl VTO) , (T(t), a(fly), a(fleo), a (flee) and the 10 correla-
tion coefficients between the 5 mismatch parameters. From the measurement results,
it could be concluded that for transistors with a channel length higher than 4 fLm, only
the mismatch parameters a(fl VTO), act), a(fly) have to be extracted for one region
of operation. The results are also valid in the other bias region. Also the correlation
terms can be ignored which is in accordance to the Pelgrom model. For small size
176 Transistor Mismatch: Evolution and Relevance

devices, !).()eff can no longer be ignored. Furthermore, to obtain a good drain current
mismatch prediction three correlation coefficients are necessary: r(!'!.{3 ,fliJo) , r(!'!.{3,fliJe )
and r(!'!.{3,!'!.y).
The dependency of the mismatch parameters on the transistor dimensions is based
on the idea that to realise a precise transistor mismatch model, more terms (beside the
ones suggested by Pelgrom) have to be added. A very general mathematical function
(eq.8.38) that accurately fits the measured data is used since the main goal is to use
this model in a circuit simulator and not to acquire knowledge of the physical causes
of the transistor mismatch.

(8.38)

In [Gotar KLUWER], a verification of the characterisation results and the imple-

mentation of the transistor mismatch model in conventional electrical circuit simula-
tors is discussed in more detail.

8.4.4 Model of Griinebaum-Oehm

8.4.4.1 The Spectral model

The starting point for this model is the spectral model presented by Pelgrom. For the
derivation of the model itself, the reader is referred to section 8.3. During the years,
this model has been refined [Grune ESSCIRC97, Oehm ESSCIRC98, Oehm ICECS99,
Grune KLUWER] which resulted in a simulation tool called GAME (General Analy-
sis of Mismatch Effects). The shape of the spectral density for the standard deviation
a (/::;. P) is depicted in fig.8.l. This spectrum can be modelled by

P(u, v) = (8.39)

where A p, k p and a p are three parameters that have to be determined using mea-
surement data. The white noise component A p is identical to the well known first
order area mismatch parameter. The coloured noise component is characterised by
the coefficients k p and a p. Measurement data on different processes indicate that the
value for ap equals 1.5 for all mismatch parameters. Assuming kp = 0, the standard
deviation of mismatch parameter P can be reduced to the first order law of area (cfr.
Lakshrnikumar, Pelgrom).
8.4 Other models 177

-
D..

-
<I
as
E
0'1
coloured noise

·Ui

white noise
Ap "
----------,-~--------------

u,v [1/um]

Figure 8.1: The spectral density function

8.4.4.2 Different mismatch effects explained

Using this model, different parameters that influence the mismatch behaviour of the
transistors can be explained. A short overview is given:

• Long distance mismatch

The Pelgrom model states that the value of the mismatch parameters increases
linearly with the distance between the considered devices. However, the spectral
model states that for larger distances a saturation effect occurs. This has been
verified by measurements.

• Layout topologies
Due to parameter gradients over the wafer, the layout topology of the transistor
pair has a significant effect on the value of the mismatch parameters. This effect
is well known from measurements on common centroid transistor structures.
The advantage of the spectral model is that the influence of the topology can
be correctly modelled and taken into account. Fig.S.2 shows the results from
simulations with the spectral model for three different topologies. The mismatch
between two transistors is the worst when the geometrical device centers are
located far from each other (topology 1).

• Geometry corrections
To obtain a good correspondence between the model and the measurement re-
sults, geometrical corrections of the drawn transistor dimensions are needed.
This has already been indicated by [Lovet JSSC98] where the effective channel
length and width are used instead of the drawn dimensions for small geometry
178 Transistor Mismatch: Evolution and Relevance

-
-
Q.
<:J
co topology 1
E
C)
~=I 'C:::===:J

en
DD
topology 3

,,
topology 2

first order law

of area

sqrt(WL) [urn]

Figure 8.2: A qualitative view of the mismatch dependence on the transistor geometry

devices. Measurements show that introducing the variables D Land Dw allows

for precise mismatch modelling of small devices (for u(.6. VTO».

• Parameter correlations
The correlation that exists between the MOS electrical parameters like VTO and
f3 are caused by their dependence on the same underlying physical technology
parameters like the gate oxide thickness t ox . A strong statistical contribution of
a common physical parameter increases the correlation coefficient between the
model parameters while the contributions from independent physical parameters
lowers the correlation.

8.4.5 Drennan-McAndrew

Most MOS transistor mismatch models that exist today are based on the results pre-
sented by Pelgrom. This model [Drenn IEDM99] approaches the mismatch problem
from another angle .

• This model starts from the physical process parameters VIb, tox , b..L, b..w, nsub,
JIO, Psh (drain region sheet resistance) and Vt/ (length variation of the threshold
voltage). A big advantage of this model is the analysis of the contribution of
these process parameters to the overall mismatch. In this way, the most im-
portant physical causes can be identified which can be used to guide process
diagnosis and improvement.
8.4 Other models 179

• The ~ L dependency of the mismatch parameters is in some cases inadequate.

Several parameters (f.e. 6.L , Psh) exhibit 22' W~2 ' ~2 ' 1
W L' ~ dependencies.

The variance of the mismatch parameters is not characterised directly but extracted
using measurements on the drain current mismatch over different geometry and bias
regions (both in linear and saturation regions) :

~ aId 2
(J2(6.Id) = ~ (_)2 (J (!~...pJ) (8.40)
J apJ

where the sensitivities ~~~ are computed using SPICE models for each bias and ge-
ometry. In this work, the BSIM3 models have been used. Measurements have been
performed on devices processed in a 0.28 /-Lm technology. The results indicate that
the model is able to represent the measured mismatch behaviour quantitatively and
qualitatively over bias and geometry.

8.4.6 Model of Croon

In this model [Croon JSSC02] the drain current mismatch has been calculated by using
a first order Taylor approximation of the drain current equation:

t:...ID 1 aID I aID

- = --t:...P, + --t:...P2 + ... (8.41 )
I D I D a P2 I D a P2

with Pi the mismatch parameters. In this model 4 parameters are introduced. One
describes the threshold voltage mismatch and the others the current factor mismatch.
For the derivation of the threshold voltage mismatch, it has been assumed that the
drain current is only a function of VGS - VT

ID = ID(VGS - VT) (8.42)

leading to the following mismatch model:

6.ID I aID gm
(-)VT = --t:... VT = --6. VT (8.43)
ID ID aVT ID

where t; is calculated from measurement data. It has been assumed that the threshold
voltage mismatch is independent of the drain bias and that it is the same in weak and
in strong inversion. For the bulk bias dependence a physical model has been used
based on the doping concentration and the oxide capacitance instead of the frequently
used body effect factor.
180 Transistor Mismatch: Evolution and Relevance

For the derivation of the current factor mismatch, the following drain current
model has been used:

VDS
ID = f3(VGS - VT - - ) VDS (8.44)
2

The mobility is determined by the bulk mobility, phonon scattering, surface roughness
scattering and velocity saturation. These elements are integrated in the following three
current factor mismatch parameters :

WJLBCox
f30
L
Ssat WCoxVsat
1 L 1
1
--(-+-+Rs)
Ssr WCox aph a sr

giving the following result for the current factor mismatch:

I::!.ID I VDS I I
(-)f3 = -f3I::!.- - f3(VGS - VT - -)I::!.- - f3VDSI::!.- (8.45)
ID f30 2 Ssr Ssat

The complete mismatch model is given by :

I::!.ID I::!.ID I::!.ID

(-) = (-)VT + (-)f3 (8.46)
ID ID ID

The threshold voltage mismatch can be described by the Pelgrom model and is
given by:
a2(I::!.P) = Ao + ~ + Aw + D2 (8.47)
WL WL2 W2L
where the first term on the right hand side describes the variance for a large device, the
second and the third term describe the variation in short and narrow channel effects
and the fourth term is contributed to gradient mismatch.
For the three other parameters, the mismatch can be described as :

(8.48)

For more details, the reader is referred to [Croon JSSC02].

A test chip has been made in a 0.18JLm CMOS technology consisting out of 14
device pairs. From the measurements, it could be concluded that the model is contin-
uous from weak to strong inversion and from the linear to the saturation region and
achieves an accuracy within 20% in the strong inversion region.
8.5 Mismatch parameters for the 0.5 and the 0.4 fl,m CMOS technology 181

8.5 Mismatch parameters for the 0.5 and the 0.4 fLm
CMOS technology

8.5.1 The 0.5 p,m technology

In this paragraph, the extraction of the mismatch parameters for a 0.5 fl,m CMOS
technology will be discussed in more detail. A test structure has been designed that is
built up out of 10 rows and columns. Each row contains 10 nMOS transistors with the
same dimensions. The transistor in the first column is taken as the reference device.
The transistor dimensions have been chosen as to span a wide 1/.JW L range (from
0.05 up to 1.6 fl,m -1) and are given by W!L = 20/20, 10/3.2, 3.2/10, 0.8/20, 20/0.5,
114,111.4,2.8/0.5,110.7,0.8/0.5 fl,m/fl,m. The measurements have been performed
on packaged devices in the saturation region (VBS = 0) using a HP3457 multimeter
with a 5 to 7 112 digits of resolution. The drain current mismatch model that has been
used is given by

(8.49)

From the measurement results, it could be clearly seen that the first order law of
the area does not explain the threshold voltage and current factor mismatch behaviour
for short and narrow devices. Therefore, the following extended model for these mis-
match parameters has been used :

(8.50)

(8.51)

The results are given in fig.8.3.a and fig.8.3.b. In these figures the standard devia-
tion of the threshold voltage mismatch and the current factor mismatch is given as a
function of the inverse of the square root of the channel area of the transistor. The
measurement results are indicated with a '*'. In the figures, also the mean value for
the a(Do Vr) and a( ll/) is given (represented by' +'). The value ofthese standard de-
viations has to be close to zero to exclude any systematic effects [Basto TSM97]. The
solid line indicates the Pelgrom model that for the threshold voltage underestimates
the mismatch value for small size devices and for the current factor overestimates the
mismatch. The results of the extended model are given by the circles on the plot.
There exists a fairly good agreement between the measurement values and the model.
The results are summarised in table 8.1.
182 Transistor Mismatch: Evolution and Relevance

18r-----r----,,----,-----,-----,-----.-----.----~

0.8/0.5
16

14 PE~G~O'" COEF = 7 •. 3mVum

:;- 1/0.7
§. 12 !i>
0;-
C)
.l!!
0
>
"tI
0
.c
'"
f
.c
i
E
C)
'iii

_2~----~----~----~----~-----L----~----~----~
o 0.2 0.4 0.6 0.8 1 1.6
1/sqrt(area) (1/um)

(a) The standard deviation of the threshold voltage mismatch as a func-

tion of the inverse of the square root of the area

2.5,----,-----,-----,-----.------,.-----.-----,------,

2 PELGROM COEF= 1.3 %um

*
* 0.8/0.5
1111.7
2.8/0.5

+
o + + + + +
+
+
+

_0.5 L - - - - ' - - - - - L - - - ' - - - - ' - - - - ' - - - - - - " ' - - - - - ' - - - - - - '

o 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
1/sqrt(size) (1/um)

(b) The standard deviation of the current factor mismatch as a function

of the inverse of the square root of the area

Figure 8.3: The extracted mismatch parameters for a 0.5 fJ,m CMOS technology
8.5 Mismatch parameters for the 0.5 and the 0.4 p.,m CMOS technology 183

Pelgrom coef. Extended Model

AVT[mV p.,m] ATvT[mV p.,mf A~VT[mV p.,mf A~VT[mV p.,m]2
7.3 45.9 43.3 -5.3
A/3[% p.,m] ATB[% p.,m]2 A~B[% p.,m]2 A~B[% p.,m]2
1.3 1.8 -0.4 -0.5

Table 8.1: Extracted mismatch parameters for a 0.5p.,m nMOS process

Pelgrom coef. Extended Model

AVT[mV p.,m] ATvT[mV p.,m]2 A~VT[mV p.,mf A~VT[mV p.,m]2
10.4 112 18.6 -45.8
A/3[% p.,m] ATB[% p.,m]2 A~B[% p.,mf A~B[% p.,m]2
1.6 0.8 -0.3 0.4

Table 8.2: Extracted mismatch parametersfor a O.4p.,m process (nMOS)

In fig.8.4, the threshold voltage and the current factor mismatch are given as a
function of the distance for the transistor with dimensions WIL = 20/20 p.,mj p.,m. As
can be seen from the plots, the mismatch parameters increase linearly with the distance
(as is predicted by the Pelgrom model). The distance coefficients have been derived
and equal:

SVT = 0.2p.,V p.,m (8.52)

S/3 = 0.3 %mm

To validate the characterisation procedure, the measured drain current mismatch

is compared to the drain current mismatch calculated using the extracted values of the
threshold and current factor mismatch (eq.(8.49». The results are given in fig.8.5 for
transistors with a WIL = 114 (top), 3.2/10 (middle) and 0.8/0.5 (bottom) p.,mj p.,m.

8.5.2 The 0.4 fJ-m technology

The same extraction procedure has been followed. The test structure was buit up out of
transistors with the following dimensions WIL = 8/8, 1.25/15,4/4, 32/0.4,2/2, 8/0.4,
1.25/1.25,1.25/0.4 p.,mj p.,m. For each transistor pair 100 samples were measured. The
results are given in table 8.2 for the nMOS transistors and in table 8.3 for the pMOS
transistors.
184 Transistor Mismatch: Evolution and Relevance

0.9

0.8
:;-
.s
G)
0.7
*
Cl
.l9 0.6
'0
>
'C 0.5
'0
..c:: *
III
!! 0.4 *
..c::
~
to 0.3
E
Cl
'0;
0.2 DISTANCECOEF = 0.2 uV .urn

0.1

oL-__ ~ __ ~ __
- L_ _~_ _~_ _ _ _L -_ _~_ _~_ _- L_ _~

o 100 200 300 400 500 600 700 800 900 1000
distance (urn)

O.4.--,------.--.----,-----,---.----,---r--,----,

0.35

*
0.3 DISTANCE COEF =0,3 % mm
~
~O.25
u
J!!
~ 0.2
::I
u
IO.15
Cl
'0;

0.05 *

0L-_~ _ _L_~_ _L__~_ _ L _ - J_ _L__J-_~

o 100 200 300 400 500 600 700 800 900 1000
distance (urn)

Figure 8.4: The threshold voltage and current factor mismatch as a function of the
distance for a transistor with a WIL = 20120 f..Lm / f..Lm
8.5 Mismatch parameters for the 0.5 and the 0.4 fl-m CMOS technology 185

I .•

I .•

~
£1.4
~
E 1.2

I
;;
e
1

.;;
c O.8
E
;;'"
a .•

a.' a .•
0.' a.' 1.2 1.' I .• 1.'
VGS-V T M

a .•

0.7
~
:2
~ a .•
~
E 0.5
;:
~
B a.'
e
~
:2-
0.3
11
'"
;;
0.2

0.1
A .• 0.6 0.8 1.2 I.. 1.6 1.'
Vc;.S-VT IV]

•
[
~
~
E
;:
~
u
e

~
=
11
'"
;;

I.'
I
O. A.' 0.' 1.2 1.' I .•
VGS- VY [V]

Figure 8.5: The measured (0) and calculated (solid line) drain current mismatch for
transistors with a W/L = 114 (top), 3.211 0 (middle) and 0.8/0.5 (bottom) fl-m/ fl-m
186 Transistor Mismatch: Evolution and Relevance

Pelgrom coef. Extended Model

AVT[mV fLm] AivT[mV fLm]2 A~VT[mV fLmf A~VT[mV fLm]2
14.2 212.5 8.2 -2.4
Ap[% fLm] Aitl [% fLmf A~tl[% fLm]2 A~tl[% fLm]2
1.1 2.41 -0.5 0.3

Table 8.3: Extracted mismatch parameters/or a O.4fLm process (pMOS)

8.5.3 Evolution of the mismatch parameters A VT and A,B

In fig.8.6, the Pe1grom area proportionality mismatch parameters (A VT and Atl) are
given as a function of the gate-length. This data has been derived from [Pelgr IEDM98,
Uyten CICC01] and from measurements at the ESAT-MICAS laboratory of the K.U.
Leuven. As can be seen from this figure, the threshold voltage parameter A VT scales
down with technology due to its dependence on the oxide thickness. However, the
current factor parameter Ap remains constant over the different technologies. Note
that this implies that for technologies with a small gate-length, the contribution of the
current factor mismatch gains in importance in comparison with the contribution of
the threshold voltage mismatch.

8.6 Transistor mismatch dependency on its geometry

8.6.1 Introduction

In literature, the effect of the transistor topology on the mismatch behaviour has been
investigated [Basto ICMTS96, Wong ICMTS95, Wong ICMTS96] for different layout
structures. In the first part of this section, a short overview is given of the main results
that have been published. In the second part, a new transistor layout structure will
be discussed that has a low parasitic source and drain capacitance and a matching
behaviour similar to that of the finger style topology [VdBos TSMOO].

8.6.2 Different Layout Structures

In [Basto ICMTS96], the transistor mismatch dependency on topology is discussed.

From measurements performed on a test structure processed in a 0.7 fLm CMOS tech-
nology containing transistor pairs with an interdigitated quad, an interdigitated waffle,
a finger and an interdigitated finger structure with dimensions WfL= 105011,660/0.7,
336/3, 360/0.7, 10011 60/0.7 fLm/ fLm, the following conclusions have been drawn.
The interdigitated waffle and quad transistor layout structures have a threshold
8.6 Transistor mismatch dependency on its geometry 187

25r-----.-----~----~----._----,_----_.----~

20

oL-----L-----~----~ ____~____~_____ L_ _ _ _~
o 0.2 0.4 0.6 0.8 1.2 1.4
gate-length [um]

3r-----.-----~----,-----._----,_----_.----~

2.6

E:::J
~ 2.2
j
«
1.8
;Ii * *
* *

1.4

1 L-____L-____ ~ ____ ~ ____ ~ _____ L_ _ _ __ L_ __ _ ~

o 0.2 0.4 0.6 0.8 1.2 1.4

gate-length [um]

Figure 8.6: The mismatch parameters A VT and A.s as a function of the gate-length for
nMOS devices
188 Transistor Mismatch: Evolution and Relevance

5 5
5 01 5 02 5 S 5 5
5 5 01 5 5
02 5 01 S 02 5 01 S 02 S
S 02 S S 01 5

S 02 5 01 5 5 5 5 02 5 S

5 5 02 S
01 S 02 S 01 S 02 5 01 5
5 5 01 5 S
S 01 5 02 5 5 5
5 5 ..........

Figure 8.7: the interdigitated waffle, the square structure and the hexagonal structure

voltage and current factor mismatch that is inversely proportional to the square root
of the area. However, for the finger style layouts, the current factor mismatch is con-
siderably higher than that of the common centroid structures. This has been explained
by stress that is induced into the silicon chip during packaging. More details can be
found in [Basto TSM97].
In [Wong ICMTS95, Wong ICMTS96], the transistor mismatch has been investi-
gated for an interdigitated quad transistor pair, a 90° rotated transistor pair, a parallel
transistor pair and an interdigitated finger structure. Also here measurements prove
that the best matching performance is given for the interdigitated quad topology al-
though this behaviour can also be obtained by the parallel transistor pair if dummy
transistors are placed. The 90° rotated structure shows the worst mismatch due to its
inherent asymmetry.

8.6.3 The hexagonal transistor

8.6.3.1 Introduction

Since the demand for devices with a higher operation speed and a higher resolution
increases, the role of the parasitic capacitance of the transistor is one of major im-
portance. A small parasitic capacitance has not only a beneficial effect on the speed
requirement but also on the power consumption of the chip which is one of the key is-
sues in integrated design (GSM, DECT, ...). Therefore alternative layout structures are
implemented that reduce the parasitics as much as possible. The hexagonal transistor
structure (fig.8.7.c) has a very small drain and source capacitance in comparison to the
rectangle and finger style transistors that are generally used. In section 8.6.3.2, a gen-
eral discussion of the hexagonal transistor is given. The structure of the transistor and
the derivation of its effective WfL ratio is discussed in detail. In section 8.6.3.3, the
drain and source capacitance as well as the matching parameters of the new transistor
structure are calculated, measured and compared with the generally used transistors.
8.6 Transistor mismatch dependency on its geometry 189

DRAIN 1 DRAIN 2
V gate
SOURCE DRAIN 1
~

~..
M....
.. V gate -1 ~ V gate
DRAIN 2 SOURCE

Figure 8.8: The parasitic transistor created by the interdigitated waffie structure

8.6.3.2 The Hexagonal Transistor

8.6.3.2.1 The transistor structure Fig.8.7.a represents a transistor pair imple-

mented in an interdigitated waffle structure, which is recommended for optimum
matching performance [Basto ICMTS96]. However, this implementation is not the
equivalent of a simple MOS transistor pair circuit but is equivalent to the circuit of
fig.8 .8. A parasitic transistor M par is formed between the drain areas of the two
transistors of the transistor pair. To avoid this parasitic transistor, an alternative im-
plementation is proposed. It is based on the principle that every drain area has to be
surrounded by source areas so that no direct contact between any two drains is pos-
sible. This approach can be applied to the square drain areas of the waffle transistors
(fig.8.7.b) leading however to a transistor with a large source area and thus a large
source capacitance. This can be avoided by the use of a hexagonal shaped source and
drain (fig.8.7.c). In section 8.6.3.3, it will be shown that this transistor structure has a
source capacitance that is 25 percent lower than the source capacitance of the square
transistor structure.

8.6.3.2.2 The transistor parameters Before this transistor can be effectively used
in circuit design, the effective WfL ratio has to be determined. This ratio will be ap-
proximated by integrating the current-voltage relationship for an infinitesimal distance
dx over the total gate length of the transistor (fig.8.9) [Gray, Laker]. The calculation
is performed for a transistor operating at the transition point between the linear and
the saturation region. In this case, the voltage drop along the channel is linear and
Vgs - VT equals Vds . The incremental voltage drop along the channel (with respect to
the source) is given by:
190 Transistor Mismatch: Evolution and Relevance

SOURCE

• gate-poly

Figure S.9: Calculation o/the effective width

The incremental resistance depends on the mobile channel charge:

dxcos(300)
dRds = --------- (S.54)
x JlCox(v gs - VT - vcs(x))
The current through the channel is proportional to the voltage drop dvcs(x) across the
resistance d Rds :

Iv
W2cos(300) dx
ids - =
Iv
W2cos(300) JlC v 2
ox ds (WI -
x
)dx (S.55)
Wlcos(300) x WI cos (30°) (WI - W2)2cos 2(300) cos (30°)
Taking into account the six sides of the hexagon, the current-voltage characteristic is
given by:
W 6
(-)eff = -=w:-----
L In(w~)cos(300 )
(S.56)
This formula links the geometrical parameters WI and W2 of the gate all around the
transistor to its effective WIL ratio. For a hexagonal transistor with a minimum gate-
length L of 0.5Jlm, the effective gate-width W equals 7.6Jlm taking into account the
ground rules of the used technology. In [Grign EDS2] an analytical expression for the
W /L ratio can be found for transistors with a non-rectangular gate geometry. However,
the analysis is quite complex. Solving the equations for the hexagonal transistor gives
almost an identical result as the one obtained by eq.(S.56). In fig.S.lO, the measured
IDS - VGS characteristic for different WIL 's is plotted versus Hspice simulations
using the calculated WIL ratio. As can be seen from this figure, there exists a good
agreement between the measured and the simulated values. For reasons of complete-
ness, the value of the W /L ratio for the square structure is given here. The result can
be easily verified by using a similar calculation as the one for the hexagonal transistor.
W S
(S.57)
(T)eff = In(W2)
WI
8.6 Transistor mismatch dependency on its geometry 191

0.09

0.08

0.07

~ 0.06
III
_0

0.05

0.04

0.03

0.02

0.01

0
0.5 1.5
VGS[VI

Figure 8.10: The drain current characteristic of the hexagonal transistor

8.6.3.3 Transistor Properties of the Hexagonal Structure

8.6.3.3.1 The drain and source capacitance The drain area of the hexagonal tran-
sistor is solely determined by the layout rules of the used technology (dimension of
a contact hole, distance between a contact hole and the gate,... ). As was indicated in
section 8.6.3 .2, the smallest possible effective W equals 7 .6/Lm in the used 0.5/Lm
technology. A comparison will now be made between the drain and source capac-
itance of the finger style and the hexagonal transistor structure. In a first step, the
drain capacitance has been calculated. Using fig.8.11 , the drain area of the hexagonal
transistor can be easily calculated:

(8.58)

For the finger style transistor, the drain area is minimal for an even number of
fingers, since in that case no drain regions are located at the edges of the transistor.
For the used technology, it can be determined that the minimal value for the transistor
is given by:

AD - F = 0.9 W (8.59)
192 Transistor Mismatch: Evolution and Relevance

:: --/-1 ,\___ 1
\
:/
:,

\:
'\
!)
(,',

(~
~ l.
:, \ /:
:, \ / ':
/
: ____ ~......_ _ _ _ _........ ____ oJ"

Figure 8.11: Calculation of the drain area

From eq.(8.58) and eq.(8.59), it follows that

AD-HEX 2.9 r2 AD-F

(8.60)
(WjL)HEX WHEX (WjL)F
where W HEX represents the gate-width implemented by the hexagonal structure. For
a minimum size transistor (WHEX = 7.6 11m, LHEX = 0.5 11m and r ~ 1), this ratio
equals

-AD-HEX
- - - = 0.4 -AD-F
-- (8.61)
(WjL)HEX (WjL)F
which means a 60 % improvement for the hexagonal topology in comparison to the
finger topology. Fig.8.12 shows the drain capacitance as a function of the effective
width of the transistor for different layout structures.
It should be noted that in the presented structure - which will be referred to as
D-HEX -, only the area of the drain has been minimised. Another interesting option
is the minimisation of both the source and the drain area (SD-HEX structure) as is
indicated in fig.8.l3. This figure shows the hexagonal structure when respectively
only the drain area (D-hex) and when both the drain and the source area (SD-hex) are
optimised. Although the SD-hex structure has no influence on the drain capacitance
(fig.8.I2), it has a positive impact on the source area as will be explained in the next
paragraph.
Since the source area of the hexagonal transistor has the same shape as the drain
area, eq.(8.58) is still valid. However, when multiple unit drain hexagonals are used
in a honeycomb type structure, each source is used for more than one drain. Taking
into account the outer bounds of the matrix, which are source cells, every drain in
the hexagonal structure has on the average three source areas. Also the value of the
8.6 Transistor mismatch dependency on its geometry 193

140~--------~----~----~--------~----~--~

120

100 finger

"'~ 80
E
2-
o
<I: 60

40

20

oL-__ ~ ____- L_ _ _ _ ~ _ _ _ _L -_ _ ~ _ _ _ _- L_ _ _ _ ~ __ ~

o ~ ~ 00 00 100 1~ 1~ 1M
W[um]

Figure 8.12: The drain area/or the D-HEX, SD-HEX and finger style structure

parameter r* will be different from the drain cells and equals r* = r + st(tcfo).

*2 ° # sources
AS-HEx=3r cos(30) . (8.62)
drain
For the finger style structure, the source area for an even number of fingers is given
by:

#F * WF
AS-F = (2 H + (- - 1) H ) - = Z WF (8.63)
2 #F
with #F the number of fingers (2,4,6, ... ), H the length of the source area at the edges
of the transistor and H* the lenght of the source area between two fingers. From
eq.(8.62) and eq.(8.63), it follows that :

9 r*2 cos (30°) AS- F

AS- HEX = ------~--..:... --.:::...-~ (8.64)
Z WHEX (W / L)F
For a minimum size transistor this ratio reduces to (r * = 1.58 11m )

2.56 AS-F
AS-HEX = -z- (W/L)F (8.65)
which means that for a transistor with 2 fingers, the source area of the hexagonal
structure is 70 % larger than that of the finger transistor. For the optimised SD-HEX
194 Transistor Mismatch: Evolution and Relevance

Figure 8.13 : The D-HEX and the optimised SD-HEX structure

8.6 Transistor mismatch dependency on its geometry 195

600

500

400
"'~
E
2-
«
(/)
300

200

100

0
0 20 40 60 80 100 120 140 160
W [urn]

Figure 8.14: The source area/or the D-HEX, SD-HEX andfinger style structure

structure, the derivation for the source area is similar to the one of the D-HEX struc-
ture. The value of the r* parameter changes and equals r* = r + 2~~(~~O). This
implies an area decrease of 66 %. As a consequence, eq.(8.65) changes to

1.71 AS- F
AS-HEX = -z- (W/L)F (8.66)

which results in a source area for the hexagonal structure which is only 14 % larger
than the finger style topology with 2 fingers. Fig.8.14 shows the source capacitance
versus the effective W for different layout styles.

8.6.3.3.2 The matching performance For transistors with a large WIL ratio -as is
the case for the hexagonal structure- the layout style has an influence on the matching
performance of the devices [Basto PhD, Wong ICMTS95]. Common centroid geome-
tries are recommended to reduce the effects of spatial parametric variations on the
transistor mismatch [Vitto lSSC85, Elzin ICMTS96]. In this paragraph the mismatch
results will be discussed for an interdigitated hexagonal transistor pair.
The structure has been implemented as a part of a test structure for a O.5lim stan-
dard CMOS technology. Fig.8.15 shows the chip layout of this test structure. The tech-
nology has not been adapted in any way to make the realisation of this structure pos-
sible. Fifty test chips have been fabricated and measured. The transistor dimensions
196 Transistor Mismatch: Evolution and Relevance

Figure 8.15: The chip photograph of the test structure

I AVT[mV jLm] I AfJ[%jLm]

finger (Lmin) I 11 1 l.2
hexagonal (Lmin) I 8.5 I 0.93

Table 804: Extracted mismatch parameters for the hexagonal structure

of the hexagonal structure equal 304/0.5, 18204/0.5 and 30A/0.5jLmj jLm. The tran-
sistors have all been measured in the saturation region (V DS = 3V), where mismatch
is the most important for analog design. The matching parameters [Pelgr JSSC89]
have been extracted using the method described in [Basto ICMTS96]. Fig.8.16.a and
fig.8.16.b show the threshold voltage and the current factor standard deviation cal-
culated with the data extracted from the test structure for the two layout styles: the
interdigitated finger and the hexagonal transistor pair. It can be concluded from this
figure that the mismatch behaviour of the hexagonal transistors is in the same order of
magnitude as that of the finger style transistors. The values of the extracted mismatch
parameters are given in table 804.
8.6 Transistor mismatch dependency on its geometry 197

14r-------,--------,--------.-------~------_,

12

~10
>
.§.
~8
S
Gi
"0
~6
lU
E
en hexagonal
'iii 4

0.2 0.4 0.6 0.8

1/sqrt(WL) [l/um]

2.-------,--------,--------,-------,--------.

_1.5
~
g-
O>

~
.n 1
~
a;
'0
'iU
E
0>
'0;
0.5
hexagonal

O~------~------~--------L-------~------~
o 0.2 0.4 0.6 0.8
1/sqrt(WL) [1/um]

Figure 8.16: The matching behaviour of the hexagonal transistor

198 Transistor Mismatch: Evolution and Relevance

8.6.3.4 Conclusion

A new hexagonal transistor realised in a standard CMOS technology has been pre-
sented. The main advantages are the very low drain and source area. The I-V char-
acteristics have been determined and compared to the simulations. The transistor pair
mismatch has been investigated and compared with the results of traditional finger
type transistors.

8.7 Influence of the surroundings of the transistors on

the mismatch behaviour

8.7.1 Side Effects

In [Wong ICMTS95], a study has been made on the effect of dummy devices on the
matching behaviour of a transistor pair. It has been shown that adding dummy struc-
tures can result in the same level of matching as the cross coupled pair while having a
much better silicon area budget. In a current steering DIA converter one of the main
building blocks is the current source array. To optimise the mismatch behaviour of the
current sources, extra rows and columns of dummy transistors have to be added at the
edges of the current source matrix.

8.7.2 Metal Coverage

To minimise the area in D/A converters, the routing needed for the complex switch-
ing schemes has been placed on top of the current source transistors. This has been
done as symmetrically as possible. In [Tuinh ICMTS97], a large number of test struc-
tures is presented to evaluate the mismatch effects caused by metal lines running over
matched transistor pairs. This subject gains in importance as more and more mixed
signal IC's are processed in multilevel metal CMOS processes. In this paragraph, the
most important results will be discussed. For more details the reader is referred to
[Tuinh ICMTS97].

From measurements it seems that covering the transistor with metal lines has a
significant effect. Asymmetrical metal coverage can cause drain current mismatches
in the range of 3 to 50 %. Calculating the median value of the drain current mismatch
distributions shows that both the reference and the symmetrically covered module have
a value smaller than 0.5 %, while for the asymmetrical covered transistors this value
is about 10 times larger. It has been concluded that the observed systematic mismatch
is caused by mechanical stress that influences the mobility of the transistor.
8.8 The CMOS current steering D/A Converter as a test structure for 199
transistor mismatch parameter extraction

8.8 The CMOS current steering D/A Converter as a

test structure for transistor mismatch parameter
extraction

8.8.1 Introduction

For the VLSI manufacturer, it is very important to be able to provide his customers
with the necessary quantitative data of the matching quality of his technology. This
can be achieved by the use of dedicated test circuits that are especially designed for
this purpose (low parasitics, high measurement accuracy, ... ). Furthermore, it is nec-
essary to follow the evolution of the matching performance of the technology over
different runs in time. This requires a test circuit that gives a good indication of the
matching technology for a low cost. However, these circuits are of no further use
to the manufacturer or the designer and therefore an alternative structure has been
sought for. A high performance current steering D/A converter is highly dependent
on the matching quality of the technology. Furthermore, the evaluation of the D/A
converter's performance poses no problem since there exist standardised test proce-
dures. In this chapter, the D/ A converter's performance will be directly translated in
the matching characteristics of the technology. In section 8.8.2 the test structures as
they exist now will be shortly discussed. In the next section the D/A converter ap-
proach will be presented. In this section the transistor mismatch extraction procedure
is discussed. Measurement results will be shown and evaluated for a standard 0.5 fLm
CMOS technology.

8.8.2 The Test Structure Approach

Until now, the test circuits are constructed using an array of about fifty to one hun-
dred transistors with some additional digital/selection logic to be able to automate the
measurements to a large extent [Basto ICMTS95, Serra ISCAS98]. Fig. 8.17 shows
a simplified schematic of such a test structure. The dimensions of the transistors are
chosen in such a way that the k of the transistors span a wide interval. By mea-
suring a large number of chips, an accurate determination of the mismatch parameter
coefficients Ail and A VT of the Pelgrom equation [Pelgr JSSC89] is possible. The
test chip normally exhibits a large geometrical symmetry and consists of an array of
identical cells. Furthermore, the chip area has to be kept as small as possible to re-
duce the cost. As is mentioned earlier, these test chips have no other function than
the mismatch determination of the technology and as such are a cost overhead to the
manufacturer. Therefore, both designers as manufacturers are looking for alternative
structures to determine the transistor mismatch parameters.
200 Transistor Mismatch: Evolution and Relevance

drain 1 drain 2 drain m

gate 1
.---~-.--;------------,.-~

gate n
,---+--.---+-------------r---r

Figure 8.17: An example of the test structure approach

8.8.3 The DIA converter Approach

8.8.3.1 The DIA converter architecture as a test structure

A current steering DIA converter is based on an array of identical current cells. The
achievable resolution is dictated by the matching properties of these cells which are
determined by the used process and can only be improved by increasing the current
source transistor sizes orland adjusting the bias voltages. The close relationship be-
tween the D/A converter's performance and the transistor mismatch parameters makes
this circuit the ideal process monitor. An unary architecture is chosen because in this
implementation every current source can be accessed separately while in a binary im-
plementation the current sources are grouped bit by bit. The resolution of the D/A
converter is chosen to be seven or eight bits so that enough measurements are avail-
able to be able to work with gaussian distributions when processing the data. Such a
D/A converter can also be used in applications in the area of e.g. video and HDTY.
This leads us to the major advantage of using a current-steering D/A converter as a
test structure. This chip has further use, no silicon area has gone to waste. Further-
more, the chip area can be made in the order of only a few mm 2 . This enables the
manufacturer to place it on every wafer having in this way a continuous monitoring of
his technology.
8.8 The CMOS current steering D/A Converter as a test structure for 201
transistor mismatch parameter extraction

line fitted through the

measurement points

2
slope - 0' (~V T)

2
1/(V -V T)

Figure S.lS: The quadratic relative standard deviation in function of the inverse
quadratic gate overdrive voltage of the current source transistors

8.8.3.2 Measurement and extraction procedure of the transistor mismatch pa-

rameters

The measurements of the D/A converter can be fully automated. A program has been
written that drives the data generator (HPSOOOO) so that for different values for the
(VGS- VT )cs the current at the output of the D/A converter will be measured (HP3457
multimeter) and stored. At this point, for every gate overdrive voltage of the current
source transistors 2N - 1 measured currents are available leading to 2N - 2 transistor
pairs (Ii, [HI) with i=l to 2N - 2. Using MATLAB the values for the relative current
difference (!1 [ / I) and the relative current standard deviation (J (~l / I) can be easily
calculated. This gives us a curve as is depicted in fig.S .IS.

The formula for the relative current standard deviation is easily derived (from
eq.S.3):
2 !1[ 2 !1fJ 4(J 2(!1 VT)
(J (T) = (J (73) + (VGS - VT)2 (S.67)

For large values of the gate overdrive voltage this formula simplifies to :

(S.6S)

Using Pelgrom's equation a value for the current factor mismatch coefficient can then
202 Transistor Mismatch: Evolution and Relevance

be calculated :
(S.69)

On the other hand, for small values of (VGS - VT k S the influence of the current factor
is negligible and the relative unit current standard deviation is given by :

(S.70)

Since the characteristic of fig.S.IS is a straight line, a fitting of a 2 (/)./ / /) calculated

from the measurement data gives us the threshold voltage mismatch coefficient:

(S.71)

To avoid the influence of edge effects dummy rows and columns are used in current-
steering D/A converters. This guarantees the fact that all measured transistor pairs
have identical surroundings.

8.8.3.3 Measurement Results

As an example, the six bit current-steering D/A converter has been measured. The
chip has been processed in a standard CMOS 0.5 JLm technology. The results of
the extraction procedure described in the previous paragraph are given in fig.S.19.
From this figure the following values for the mismatch parameter coefficients can be
obtained using eq.(S.69) and eq.(S.71) :

AVT = SmVJLm

(S .72)

These results are in good agreement with the results obtained from the test structures
described in the previous chapter (AvT = 7.3m V JLm and All = 1.3%). This proves
that the D/A converter can indeed be successfully used as a process monitor for mis-
match.

8.9 Conclusion
In this chapter, different transistor mismatch models have been discussed that have
been presented in literature over the last two decades. It should be noted that the
8.9 Conclusion 203

0.5

0
0
0.4
0

0
~
~ 0.3
'iU
E 0
0>
:! y=0.11 x + 0.09
0.2

0.1

o~--------~--------~--------~--------~
1 1.5 2.5 3

Figure 8.19: The measured quadratic relative current standard deviation in function
of the inverse of the quadratic gate overdrive voltage of the current sources

models referred to in this text are by no means complete. A lot of research has been
done on transistor mismatch models in the last few years. The main goal of presenting
these models was to provide the reader with some important notions about the issue
of transistor mismatch and its importance for analog designers.
Based on the Pelgrom model and the model of Bastos, the transistor mismatch pa-
rameters have been extracted for a standard 0.5 f.im CMOS technology and a prelimi-
nary 0.4 f.im CMOS technology. The transistor mismatch dependency on the topology
has not only been addressed but a new topology has been presented. The hexagonal
structure combines a very low drain capacitance with a source capacitance and a mis-
match behaviour similar to the one of a finger style transistor.
In the last section of this chapter, the CMOS current steering D/A converter has
been presented as a test structure for matching purposes. Using a D/A converter as a
test structure has a large cost advantage. The time to implement these circuits and the
silicon area they consume can now be used to design a circuit (=D/A converter) that
can be further used in e.g. telecommunication applications. The extraction procedure
of the transistor mismatch parameters has been described and has been verified by
comparing the measurement results of a six bit current-steering DIA converter and the
results obtained from the classical test structures.
Appendix 1

In chapter 4, a formula has been derived that accurately predicts the relationship be-
tween the mismatch behaviour of the current source transistors and the achievable
INL_yield of the current steering D/A converter. This formula is given by:

u(I)
(.1)
I

. he
Wit = 'lnV.Jlorm(-x,x) (0 . 5 + IN L 2yield) .
= lnV.JlOrm(-x,x) (Z) .

In fig. 1, the value for C can be found starting from the specification for the INLyield
or starting from the calculated value for z. From the same figure, it is also possible
to obtain the value for C starting from the allowed percentage of faults that can be
tolerated.
 N
=
="

z inv norm{z Yield 1%1 Faultsl%1 z in" norm(z) Yield [%1 Faults[%1
0.50000 0.00 0.00 100.00
0.57926 0.20 15.85 84.15 0.99931286 3.20 99.862572 1.37E-01
0.65542 OAO 31.08 68.92 0.99966307 3AO 99.932614 6.74E-02
0.72575 0.60 45.15 54.85 0.99984089 3.60 99.968 178 3.18E-02
0.78814 0.80 57.63 42.37 0.99992765 3.80 99.985530 lA5E-02
0.84 134 1.00 68.27 31.73 0.99996833 4.00 99.993666 6.33E-03
0.88493 1.20 76.99 23.0 1 0.99998665 4.20 99.997331 2.67E-03
0.91924 lAO 83.85 16. 15 0.99999459 4AO 99.998917 1.08E-03
0.94520 1.60 89.04 10.96 0.99999789 4.60 99.999578 4.22E-04
0.96407 1.80 92.8 1 7.19 0.9999992 1 4.80 99.999841 1.59E-04
0.97725 2.00 95.45 4.55 0.9999997 1 5.00 99.999943 5.73E-05
0.98610 2.20 97.22 2.78 0.99999990 5.20 99.999980 1.99E-05
0.99 180 2.40 98.36 1.64 0.99999997 5AO 99.999993 6.66E-06
0.99534 2.60 99.07 0.93 0.99999999 5.60 99.999998 2.14E-06
0.997-+4 2.80 99.49 0.51 1.00000000 5.80 99.999999 6.63E-07
0.99865 3.00 99.73 0.27 1.00000000 6.00 100.000000 1.97E-07

Figure .1: The value of the parameter C as afunction of the INLyield

~
"Q

~
Q.
~ .
....
Appendix 2

In this appendix, the complete derivation of the SFDR as a function of the second and
third order harmonic distortion is given. The main results were given in chapter 5.
For a sin(wt) output signal, the number of switches T that conduct current at a
time t equals:

1 +sin(wt))
T(t)=S ( 2 (.1)

with S the total number of current sources.

The output voltage of the DIA converter is determined by the product of the current
and the load impedance ZL in parallel with T(t) parallel impedances Zimp:

SI (1 + sin(wt))
Vout(t) = ---------- (.2)
2YL + YimpS(l + sin(wt))

with I the current through one switch transistor and Yimp = I/Zimp and YL =
1/ ZL. A Taylor series expansion of the output voltage allows to determine the influ-
ence of Yimp on the dynamic performance of the DIA converter.

Vout(t) = (DC)cj + Asin(wt) + Bsin 2 (wt) + Csin 3 (wt) + DSin 4 (wt) + .. . (.3)
208 Appendix 2

with:
SI
(DCbej
2YL + YimpS
A 2 YL (DC)coej
2h + YimpS
A YimpS
B - * 2YL + YimpS
C A * ( YimpS
2YL + YimpS y
D
- *
A
( YimpS
2YL + YimpS y
A*
( YimpS
r
( r
E
2YL + YimpS
A YimpS
F
- * 2h + YimpS
(.4)

Applying goniometric relations and rearranging of the terms leads to the following
result:

Vour(t) = (DC) cj + [A + 43C] sin(wt) + [-(B 2+ D)] cos (2wt)

[D
(.5)
SE] sin(3wt) + 8" + 16
c + 16
- [ "4 3F] cos(4wt) ...
Inserting the values of eq.4 in eq.S in order to determine the influence of the second
order harmonic on the SFDR performance of a current steering D/A converter, yields
the following result:

1 (2YL + SYimp)(16Yi + 16ShYimp + 7S 2Y?mp)

Q = - 2 2 (.6)
4 SYimp(2YL + 2SYLYimp + S2yimp )

The influence of the third order harmonic is described by :

(2YL + SYimp)2(16Yi + 16SYLYimp + 7S 2Y?mp)

(.7)
T = -4 S2Yi~P(16Yi + 16Sh Yimp _ 9S2Yi~P)
Since YL » SYimp, both equations can be further simplified to:

Q = 4YL + 2SYimp ~ 4h (.8)

SYimp SYimp
 209

(4f£ +
and
T = 2SYim p )2 >:::; ( 4YL )2 (.9)
SYimp SYimp
or written in function of the SFDR :
4Zimp
H D2 = 20Iog(Q) = 20Iog(--) (.10)
SZL
and
4Z'
H D3 = 20Iog(T) = 20 log( ~)2 (.11)
SZL
From this derivation, it becomes clear that if for a 10 bit D/A converter the HD2
distortion component equals 60 dB , the HD3 distortion component equals 120dB.
It can therefore be concluded that the influence of the frequency dependency of the
output impedance has a negligible effect on the third order harmonic distortion com-
ponent.
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