2015 Online International Confernece on Green Engineering and Technologies (IC-GET 2015)

FPGA Implementation of Edge Detection using

Canny Algorithm

Jeyakumar R, Prakash M, Sivanantham S* and Sivasankaran K

School of Electronics Engineering
VIT University
Vellore - 632014, India.
E-mail: {r.jeyakumar23, prakash7494}@gmail.com, {ssivanantham, ksivasankaran}@vit.ac.in

Abstract— Abstract -In this paper we have implemented edge The paper contains the following sections. Section II
detection on a Real Time Image Capture. The video is captured explains about high level designing used. Section III describes
via the Terasic 5MP camera and then interfaced with FPGA kit about the hardware interfacing. Section IV describes about the
and the edge detected image is shown in VGA display. In experiment and the RTL view of the designed system
addition, Canny Edge Detection algorithm is used to obtain the experiment conducted in different arenas for testing. Section V
edge detected version of the RGB image captured by the summarizes the results obtained in terms of dynamic power
interfaced camera. This algorithm provides low error rate as reduction and hardware reduction
compared to the other edge detection algorithm. Our inspiration
emerged from our enthusiasm towards machine vision and
dynamics II. HIGH LEVEL DESIGN
Construction of this search edge detection using FPGA uses
Keywords— FPGA, Canny Edge Detection, Real-time Image
Capture.
following main elements:
 Canny Edge Detection algorithm
 Altera DE2 FPGA Board
I. INTRODUCTION
 Terasic D5M 5MP camera
Video processing and edge detection has always been These hardware components are explained below
tedious challenge for researchers across the world.
Autonomous machine dynamics plays a very important role in
making a device useful for applications such as defence and A. Canny Edge Detection
commercial purposes. The Real time video processing property Canny developed an approach to derive an optimal edge
of our system makes it a very outstanding system. Real time detector based on three criteria for edge detection [9].
video processing is used in many areas in the current scenario.
Advancements made in FPGA system design makes the
 Low error rate of detection: It should find all edges
efficient use of video processing in real time for many
and nothing but edges
applications.
 Localization of edges: The distance between actual
Edge detection is one of the main processes in image and edges in the image and the edges found by the
video processing. Here, we are processing in video that is too algorithm should be minimized.
in real time. For that input should be taken by the system frame  Single response: The algorithm should not return
by frame which will be similar to images that is in continuous multiple edge pixels when only a single edge exists.
flow of action. Edge recognition is broadly utilized as a part of
picture division to separate a picture in to regions comparing to
The model was based on a step edge corrupted by additive
diverse items [7]. Edges happen in parts of the picture with
white Gaussian noise. The original Canny algorithm consists
solid power contrast, which regularly speak to question limits.
Edge detection is now used in many applications like medical, of following steps[1][2].
road tracking, aerospace etc. The size of the image is  Smoothening the input image by Gaussian mask.
comparatively reduced in edge detected image. Hence This eliminates the high frequency components in the
transferring images in real time can be done with low data rate image. The output smoothed image is denoted as I (x,
and with high accuracy to detect the problem. In our case we y).
have developed a hardware system in FPGA such that the  Calculating the horizontal and vertical gradient G x (x,
output of the system gives the edge detected video in real y) and Gy (x, y) respectively at each pixel location by
time[8]. convolving the image I (x, y).
 Computing the gradient magnitude G (x, y) and
direction Өg (x, y) at each pixel location.

978-1-4673-9781-0/15/$31.00 © 2015 IEEE

 2015 Online International Confernece on Green Engineering and Technologies (IC-GET 2015)

 Applying non-maximum suppression (NMS) to thin So we used 640 x480 resolution of image and adjusted the
the edges. camera focus to maximum value under sufficient light
 Computing the hysteresis high and low thresholds condition. After that we set a threshold for gray scale image
based on the histogram of the magnitudes of the which increased the gradient and better edge detection results
gradients of the entire image. were obtained.[10]

B. Altera DE2 FPGA Board:

Altera DE2 board is the suitable hardware that we utilized for CAMERA INPUT
designing our project and it includes an Altera Cyclone II
EP2C35F672C6 FPGA with 114,480 logic elements(LEs), 8
MB SDRAM, 512 KB SRAM, 4 MB Flash, a SD card
interface, a USB master-slave controller, two access controller,
a serial connector (RS-232 DB9 ports), etc. The hardware was
CONVERT RAW IMAGE TO RGB
designed using the Altera Quartus-II v11.1 software.[3] Other
hardware details are given in the Table 1.

TABLE 1: DEVICE SPECIFICATIONS

Family Cyclone II
Device EP2C35F672C6 GRAYSCALE CONVERSION
Total Logical Elements 2,159/33216(6%)
Total Registers 1332
Total Memory Bits 77,728/48,3840
Total PLL’s 25%
Total pins 425/475
IMAGE STORED TO SDRAM FIFO

C. TRDB D5M Camera

Terasic TRDB_D5M 5MP camera is used since it provides a
good frame rate, better low light performance and less dark
currents. Terasic camera provides output video to the Altera PERFORM EDGE DETECTION ON IMAGE
board and the video is processed.
The methodology followed in finding the edge detection is
explained in fig.1
III. HARDWARE INTERFACING
The video input from the camera goes through several OUTPUT RESULT ON SDRAM
stages as mentioned in Fig- [2] before it enters into SRAM
stage. In SRAM the video input is processed using Canny edge
detection algorithm and the pixel above the threshold are given
as 1 and those which are less than threshold is converted to 0.
The pixel values are sent back to SRAM from which the image
is sent to Pixel buffer and then to the VGA display[4][6]. IMAGE OUTPUT ON VGA

IV. EXPERIMENT
Fig.1. Edge detection flow chart,
We have conducted several trials for effective edge
detection. At first, we showed a still picture on the VGA Fig. 1 shows the Edge Detection flow. From this, we have
monitor followed by real time capturization. We also mentioned the steps that we have followed. After taking the
encountered an issue with clock synchronization which was input the conversion is done that is grayscale. The image is
later unraveled by utilizing VGA_Audio_PII to change over first converted into grayscale then it is easy to detect the
Clock_27 to VGA_Ctrl_Clk[5]. particular area. After converted the data need to be stored for
that SRAM is used. At the same time, SRAM can have only
128MB hence we need frame of data’s to store freely. Key and
Then we moved on to the edge detection part and realized
switch are specified for implementing edge detection. The
that lot of images were missed out due to inefficient frame rate.
edge detected output is finally displayed in VGA monitor.
 2015 Online International Confernece on Green Engineering and Technologies (IC-GET 2015)

Initially the normal and rms do not have to be defined. Do not

use abbreviations in the title or heads unless they are
unavoidable.

AUDIO -VIDEO CONFIG

VGA CONTROLLER
VGA
VIDEO IN DECODER

Fig 4 Timing Analysis

DUAL CLOCK FIFO

DUAL CLOCK
CLOCK
BAYER-PATTERN RE- SAMPLER
V. RESULTS
The program for the system was successfully compiled and
following RTL view fig. [5] is obtained. The VGA monitor
PIXEL BUFFER DMA CONTROLLER
output is shown below fig. [6] gives the real-time image of the
PIXEL
PIXEL
BUFFER
BUFFER
CLIPPER DMA
CONTROL surroundings while fig [5] shows the gray scale image.
Different outputs were obtained for different performance
parameters such as lighting conditions and gray scale threshold
variations.

DMA CONTROLLER SRAM The images in the fig. [5] and fig. [6] are obtained from the
SR
MATLAB Simulink and the same is verified in FPGA DE2
board. The edge detected image obtained in FPGA has less
power usage and has higher efficiency compared to the DSP
Fig.2 processor. The specific hardware can be used for the edge
detection and can be transferred over server which occupies
less space.

Fig .3. Power play power analysis

Power can be calculated for the displayed output from the
power analysis tool as shown in fig. 3. To calculate the power
analysis, VCD file should be created. From that dump file is
added with that dump file, the power can be analysed and even Fig.5. RTL View
it is can be reduced The canny edge detection is created as a module and can be
seen in the RTL in fig.5
 2015 Online International Confernece on Green Engineering and Technologies (IC-GET 2015)

VI CONCLUSION
Thus the edge detection using Canny algorithm is
detected and shown in VGA display. From the implementation
in both FPGA and MATLAB we can found that FPGA has
provided good efficiency and easy portability rather than
MATLAB.

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Fig. 8. Edge Detected Image in Altera DE2 board