BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI K K BIRLA GOA CAMPUS

Microelectronics Circuits (ECE/EEE/INSTR F244) Tutorial on Differential Amplifiers

Question 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Design a MOS differential amplifier to have a CMRR of 74 dB. The only source of mismatch in the circuit is

a 1% difference between the W/L ratios of the two transistors. Let I = 100 𝜇A and assume that all transistors

are operated at V𝑜𝑣 = 0.2 V. For the 0.18-𝜇𝑚 CMOS fabrication process available, V′𝐴= = 5 V/𝜇𝑚. What is

the value of L required for the current-source transistor? If the current-source transistor is cascoded with an

identical transistor, what will the CMRR value become?

Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

For the differential amplifier shown below, let Q1 and Q2 have k′𝑝 (𝑊/𝐿) = 5 mA/V2 , and assume that the bias

current source has an output resistance of 50 kΩ. Find |𝑉𝑜𝑣 |, g𝑚 , | 𝐴𝑑 |, | 𝐴𝑐𝑚 |, and the CMRR (in dB) obtained

with the output taken differentially. The drain resistances are known to have a mismatch of 2%.

0.9 V

0.2 mA

V𝑆

V𝐺1 Q1 Q2 V𝐺2

V𝐷1 − V𝑜 + V 𝐷2

4 kΩ 4 kΩ

−0.9 V

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Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A current-mirror-loaded NMOS differential amplifier is fabricated in a technology for which |𝑉 𝐴′ | = 6V/𝜇𝑚. All

the transistors have L = 0.5 𝜇𝑚. If the differential-pair transistors are operated at V𝑜𝑣 = 0.2 V, what open-circuit

differential gain is realized?

Question 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

In a current-mirror-loaded differential amplifier of the form shown in figure below, all transistors are characterized

by 𝑘 ′ (𝑊/𝐿) = 4 mA/V2 , and |𝑉 𝐴 | = 5 V. Find the bias current I for which the gain v𝑜 /v𝑖𝑑 = 25 V/V.

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Question 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

For the differential pairs of figure (a) and (b), calculate the differential voltage gain if I𝑆𝑆 = 1 mA, (W/L)1,2 =

50/0.5, and (W/L)3,4 = 50/1. What is the minimum allowable input CM level if I𝑆𝑆 requires at least 0.4 V across

it? Using this value for V𝑖𝑛,𝐶 𝑀 , calculate the maximum output voltage swing in each case. Also calculate

differential gain of each circuit.

V𝐷𝐷 =3 V, 𝜇 𝑛 C𝑜𝑥 =134 𝜇 𝐴/V2 , V𝑡 ℎ𝑛 =0.7 V, 𝜆 𝑛 =0.1 𝑉 −1 for L=0.5 𝜇𝑚 𝜇 𝑝 C𝑜𝑥 =38.3 𝜇 𝐴/V2 , |V𝑡 ℎ 𝑝 |=0.8 V,

𝜆 𝑝 =0.2 𝑉 −1 for L=0.5 𝜇𝑚

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Question 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

In the circuit of figure below, assume that I𝑆𝑆 = 1 mA and W/L = 50/0.5 for all the transistors.

(a) Determine the voltage gain.

(b) Calculate V𝑏 such that I𝐷5 = I𝐷6 = 0.8(I𝑆𝑆 /2).

(c) If I𝑆𝑆 requires a minimum voltage of 0.4 V, what is the maximum differential output swing?

V𝐷𝐷 =3 V, 𝜇 𝑛 C𝑜𝑥 =134 𝜇 𝐴/V2 , V𝑡 ℎ𝑛 =0.7 V, 𝜆 𝑛 =0.1 𝑉 −1 for L=0.5 𝜇𝑚 𝜇 𝑝 C𝑜𝑥 =38.3 𝜇 𝐴/V2 , |V𝑡 ℎ 𝑝 |=0.8 V,

𝜆 𝑝 =0.2 𝑉 −1 for L=0.5 𝜇𝑚

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