BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI K K BIRLA GOA CAMPUS

Microelectronics Circuits (ECE/EEE/INSTR F244) Tutorial on Differential Amplifiers

Question 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

For an NMOS differential pair with a common-mode voltage V𝐶 𝑀 applied, as shown in figure below, let V𝐷𝐷 =

V𝑆𝑆 = 1.0 V, k′𝑛 = 0.4 mA/V2 , (W/L)1,2 = 10, V𝑡 𝑛 = 0.4 V, I = 0.16 mA, R𝐷 = 5 kΩ, and neglect channel-length

modulation.

(a) Find V𝑜𝑣 and V𝐺𝑆 for each transistor.

(b) For V𝐶 𝑀 = 0, find V𝑆 , I𝐷1 , I𝐷2 , V𝐷1 , V𝐷2 , and V𝑜 .

(c) Repeat (b) for V𝐶 𝑀 = + 0.4 V

(d) Repeat (b) for V𝐶 𝑀 = − 0.1 V

(e) What is the highest value of V𝐶 𝑀 for which Q1 and Q2 remain in saturation?

(f) If current source I requires a minimum voltage of 0.2 V to operate properly, what is the lowest value allowed

for V𝑆 and hence for V𝐶 𝑀 ?

(g) What is the input common-mode range?

V𝐷𝐷

R𝐷 R𝐷

V 𝐷1 − V𝑜 + V𝐷2

Q1 Q2

V𝐶 𝑀 V𝑆 V𝐶 𝑀

−V𝑆𝑆

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Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

For the PMOS differential amplifier shown in figure, let V𝑡 𝑝 =−0.4 V and k′𝑝 (W/L)= 5 mA/V2 . Neglect

channel-length modulation.

(a) For V𝐺1 = V𝐺2 = 0, find |V𝑜𝑣 | and V𝑆𝐺 for each each of Q1 and Q2 . Also find V𝑆 , V𝐷1 , V𝐷2 , and V𝑜 .

(b) If the current source requires a minimum voltage of 0.2 V, find the input common-mode range.

0.9 V

0.2 mA

V𝑆

V𝐺1 Q1 Q2 V𝐺2

V𝐷1 − V𝑜 + V 𝐷2

4 kΩ 4 kΩ

−0.9 V

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Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Design the circuit in figure below to obtain a dc voltage of 0 V at each of the drains of Q1 and Q2 when

v𝐺1 =v𝐺2 =0 V. Operate all transistors at V𝑜𝑣 =0.15V and assume that for the process technology in which the

circuit is fabricated, V𝑡 𝑛 =0.35V and 𝜇 𝑛 C𝑜𝑥 =400 𝜇A/V2 . Neglect channel-length modulation. Determine the

values of R, R𝐷 , and the W/L ratios of Q1 , Q2 , Q3 and Q4 . What is the input common-mode voltage range for

your design?

V𝐷𝐷 = +0.9 V

R𝐷 R𝐷

+0.9 V

0.1 mA
v 𝐺1 Q1 Q2 v 𝐺2
R

0.2 mA

Q4 Q3

−V𝑆𝑆 = −0.9 V

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Question 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure below shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form the differential

pair, while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2 , respectively. The dc

bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. It is required to

design the circuit to meet the following specifications:

(a) Differential gain A𝑑 = 25 V/V.

(b) I𝑅𝐸𝐹 =I=200 𝜇A

(c) The dc voltage at the gates of Q6 and Q3 is +0.4 V.

(d) The dc voltage at the gates of Q7 , Q4 and Q5 is −0.4 V.

The technology available is specified as follows: 𝜇 𝑛 C𝑜𝑥 =4𝜇 𝑝 C𝑜𝑥 =400 𝜇A/V2 ; V𝑡 𝑛 =|V𝑡 𝑝 |=0.4 V, V 𝐴𝑛 =|V 𝐴𝑝 |=5V.

Specify the required value of R and the W/L ratios for all transistors. Also specify 1𝐷 and |V𝐺𝑆 | at which each

transistor is operating. For dc bias calculations you may neglect channel-length modulation.

+1.0V

Q6 Q3
I

I𝑅𝐸𝐹

v𝑖𝑑 /2 Q1 Q2 −v𝑖𝑑 /2
R

−v𝑜𝑑 +

Q4
Q7 Q5

−1.0V

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