SUPER ®

SUPER P6DBS
SUPER P6DBE
SUPER P6DBU
SUPER P6SBU
SUPER P6SBS
SUPER P6SBA

USER’S AND BIOS

MANUAL

Revision 2.3
The information in this User’s Manual has been carefully reviewed and is believed to be
accurate. The vendor assumes no responsibility for any inaccuracies that may be contained
in this document, makes no commitment to update or to keep current the information in this
manual, or to notify any person or organization of the updates. Please Note: For the
most up-to-date version of this manual, please see our web site at
www.supermicro.com.

SUPERMICRO COMPUTER reserves the right to make changes to the product described in
this manual at any time and without notice. This product, including software, if any, and
documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or
reduced to any medium or machine without prior written consent.

IN NO EVENT WILL SUPERMICRO COMPUTER BE LIABLE FOR DIRECT, INDIRECT,

SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR
INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, THE VENDOR SHALL NOT HAVE
LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE
PRODUCT, INCLUDING THE COSTS OF THE REPAIRING, REPLACING, OR RECOVERING
SUCH HARDWARE, SOFTWARE, OR DATA.

Unless you request and receive written permission from SUPERMICRO COMPUTER, you may
not copy any part of this document.

Information in this document is subject to change without notice. Other products and
companies referred to herein are trademarks or registered trademarks of their respective
companies or mark holders.

Copyright © 1998 by SUPERMICRO COMPUTER INC.

All rights reserved.
Printed in the United States of America.
 Preface

About This Manual

This manual is written for system houses, PC technicians and

knowledgeable PC end users. It provides information for the installation and
use of SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA motherboard.
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA supports Pentium II
400/350/333/300/266/233 MHz.

The Pentium II processor with the Dual Independent Bus Architecture is

housed in a new package technology called the Single Edge Contact (S.E.C.)
cartridge. This new cartridge package and its associated "Slot 1" infrastruc-
ture will provide the headroom for future high-performance processors.

Manual Organization

Chapter 1, Introduction, describes the features, specifications and perfor-

mance of the SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA system
board, provides detailed information about the chipset, and offers warranty
information.

Refer to Chapter 2, Installation, for instructions on how to install the Pentium

II processor, the retention mechanism, and the heat sink support. This chap-
ter provides you with the instructions for handling static-sensitive devices.
Read this chapter when you want to install DIM modules and to mount the
system board in the chassis. Also refer to this chapter to connect the floppy
and hard disk drives, IDE interfaces, parallel port, serial ports, as well as the
cables for the power supply, reset cable, Keylock/Power LED, speaker and
keyboard.

If you encounter any problem, please see Chapter 3, Troubleshooting, which

describes troubleshooting procedures for video, memory, and the setup con-
figuration stored in memory. For quick reference, a general FAQ [frequently
asked questions] is provided. Instructions are also included for technical
support procedure, for returning merchandise for service and for BIOS up-
grades using our BBS#.

See Chapter 4 for configuration data and BIOS features.

iii
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA User’s Manual

Chapter 5 has information on running setup and includes default settings for
Standard Setup, Advanced Setup, Chipset function, Power Management, PCI/
PnP Setup and Peripheral Setup.

Appendix A offers information on BIOS error beep codes and messages.

Appendix B shows post diagnostic error messages.

iv
 Preface

Table of Contents
Preface
About This Manual ........................................................................................................ iii
Manual Organization .................................................................................................... iii
Jumper Quick Reference ............................................................................................. viii
Front Control Panel Connector ..................................................................................... i x

Chapter 1: Introduction
1-1 Overview ............................................................................................................ 1-1
SUPER P6DBS .......................................................................................... 1-3
SUPER P6DBE .......................................................................................... 1-4
SUPER P6DBU .......................................................................................... 1-5
SUPER P6SBU .......................................................................................... 1-6
SUPER P6SBS .......................................................................................... 1-7
SUPER P6SBA .......................................................................................... 1-8
SUPER P6DBS Motherboard Layout ....................................................... 1-9
SUPER P6DBE Motherboard Layout ..................................................... 1-10
SUPER P6DBU Motherboard Layout ..................................................... 1-11
SUPER P6SBU Motherboard Layout ..................................................... 1-12
SUPER P6SBS Motherboard Layout ..................................................... 1-13
SUPER P6SBA Motherboard Layout ..................................................... 1-14
440BX AGP SET: System Block Diagram ............................................ 1-15
Motherboard Features ............................................................................ 1-16
1-2 Chipset Overview ........................................................................................... 1-18
1-3 PC Health Monitoring .................................................................................... 1-18
1-4 Solo-1 PCI AudioDrive .................................................................................. 1-20
1-5 ACPI/PC 98 Features .................................................................................... 1-21
1-6 W ake-on-LAN .................................................................................................. 1-22
1-7 Power Supply .................................................................................................. 1-22
1-8 Super I/O ........................................................................................................... 1-23
1-9 AIC 7895 SCSI Controller .............................................................................. 1-24
1-10 AIC 7890 SCSI Controller .............................................................................. 1-24
1-11 W arranty, Technical Support, and Service ............................................... 1-25
W arranty Terms and Conditions ........................................................... 1-25
Returns ...................................................................................................... 1-26

Chapter 2: Installation
2-1 Static-Sensitive Devices ................................................................................. 2-1
Precautions ................................................................................................ 2-1

v
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA User’s Manual

Unpacking ................................................................................................... 2-1

2-2 Pentium II Processor Installation .................................................................. 2-1
OEM Pentium II and Heat Sink Support ............................................... 2-4
Removing the Pentium II Processor ...................................................... 2-4
2-3 Installation of the Universal Retention Mechanism ................................... 2-5
2-4 Special Instructions for the Celeron Processor ......................................... 2-5
2-5 Explanation and Diagram of Jumper/Connector ........................................ 2-7
2-6 Changing the CPU Speed .............................................................................. 2-7
2-7 Mounting the Motherboard in the Chassis .................................................. 2-8
2-8 Connecting Cables ........................................................................................... 2-8
Power Supply Connectors ....................................................................... 2-8
Secondary Power Connector .................................................................. 2-8
Infrared Connector ...................................................................................... 2-8
PW_ON Connector ...................................................................................... 2-9
Reset Connector ........................................................................................ 2-9
Hard Drive LED ......................................................................................... 2-9
Keylock/Power LED Connector ............................................................... 2-9
Speaker Connector ................................................................................. 2-10
Power Save State Select ....................................................................... 2-10
ATX PS/2 Keyboard and Mouse Ports ................................................ 2-10
Universal Serial Bus ............................................................................... 2-10
ATX Serial Ports ...................................................................................... 2-11
CMOS Clear ............................................................................................. 2-11
External Battery ....................................................................................... 2-11
W ake-on-LAN ........................................................................................... 2-11
Fan Connectors ....................................................................................... 2-11
Chassis Intrusion ..................................................................................... 2-12
2-9 Installing the DIM Modules .......................................................................... 2-12
DIM Module Installation ......................................................................... 2-12
2-10 Connecting Parallel, FDD and HDD ........................................................... 2-13
Parallel Port Connector .......................................................................... 2-14
Floppy Connector .................................................................................... 2-14
IDE Interfaces .......................................................................................... 2-14
SCSI Connectors ....................................................................................... 2-15
SCSI LVD 68-pin Connector ................................................................... 2-16
AGP Port ................................................................................................... 2-17

Chapter 3: Troubleshooting
3-1 Troubleshooting Procedures .......................................................................... 3-1

vi
 Table of Contents

Before Power On ....................................................................................... 3-1

Troubleshooting Flowchart ...................................................................... 3-1
No Power .................................................................................................... 3-2
No Video ..................................................................................................... 3-2
Memory Error ............................................................................................. 3-2
Losing the System’s Setup Configuration ............................................ 3-3

3-2 Technical Support Procedures ...................................................................... 3-3

3-3 Frequently Asked Questions .......................................................................... 3-4
3-4 Returning Merchandise for Service .............................................................. 3-7

Chapter 4: AMI BIOS

4-1 Introduction ......................................................................................................... 4-1
4-2 BIOS Features .................................................................................................... 4-2
BIOS Configuration Summary Screen ..................................................... 4-3
AMIBIOS Setup ........................................................................................... 4-3

Chapter 5: Running Setup

5-1 Setup .................................................................................................................... 5-1
5-1-1 Standard Setup ................................................................................. 5-1
5-1-2 Advanced Setup ................................................................................ 5-3
5-1-3 Chipset Setup .................................................................................... 5-7
5-1-4 Power Management ........................................................................ 5-13
5-1-5 PCI/PnP Setup ................................................................................ 5-15
5-1-6 Peripheral Setup ............................................................................. 5-18
5-2 Security Setup .................................................................................................. 5-21
5-2-1 Supervisor/User .............................................................................. 5-21
5-3 Utility Setup ...................................................................................................... 5-21
5-3-1 Anti-Virus .......................................................................................... 5-21
5-3-2 Language ......................................................................................... 5-21
5-4 Default Setting .................................................................................................. 5-22
5-4-1 Optimal Default ............................................................................... 5-22
5-4-2 Fail-Safe Default ............................................................................. 5-22

Appendices:
Appendix A: BIOS Error Beep Codes
and Messages ............................................................................................................. A-1
Appendix B: AMI BIOS Post Diagnostic Error
Messages ..................................................................................................................... B-1

vii
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA User’s Manual

Jumper Quick Reference

P6DBS/P6DBE/P6SBS/P6SBA P6DBU/P6SBU
Jumpers Function Page Jumpers Function Page

JB1, JB2, JB3, JB4 CPU/Bus Ratio Selection 1-9 JB1, JB2, JB3, JB4 CPU/Bus Ratio Selection 1-11
JBT1 CMOS Clear 2-9 JBT1 CMOS Clear 2-9
JP20 Power On/Off State 2-8 JP20 Power On/Off State 2-8
JL2 Manufacturer Default 1-9 S-TERM SCSI Termination
JA5 JA1, JA3, SCSI Termination (default on as terminated) 1-11
(default on as terminated) 1-9 JOH Overheat LED Header 1-11
JA6 JA2 SCSI Termination JPS1 PCI Audio Enable/Disable 1-11
(default on as terminated) 1-9 BZ-ON Overheat Alarm Enable 1-11
JOH Overheat LED Header 1-9 JP11 Bus Speed 1-11
JP11 Bus Speed 1-9 J36 Secondary Power Connector 2-6
J36 Secondary Power Connector 2-6

Connectors Function Page Connectors Function Page

J17 USB 2-8 J17 USB 2-8

J18 USB 2-8 J18 USB 2-8
J19 Parallel Port 2-12 J19 Parallel Port 2-12
J20 COM 1 2-9 J20 COM 1 2-9
J21 COM 2 2-9 J21 COM 2 2-9
J32 ATX Power Connector 2-6 J32 ATX Power Connector 2-6
J34 PS/2 KB and Mouse 2-8 J34 PS/2 KB and Mouse 2-8
JA1, JA2 UW SCSI 2-13 JA2 UW SCSI 2-13
JA3 Ultra SCSI 2-13 JA1 Ultra II LVD/SE 2-14
JBT2 External Battery 2-9 JA3 Ultra SCSI 2-13
JF1 IDE LED 2-7, 2-8 JBT2 External Battery 2-9
Keylock JF1 IDE LED 2-7, 2-8
Speaker Keylock
JF2 IR Connector 2-6, 2-7 Speaker
PW_ON JF2 IR Connector 2-6, 2-7
Reset PW_ON
JL1 Chassis Intrusion 2-10 Reset
SLED SCSI LED 1-9 JL1 Chassis Intrusion 2-10
JT1 CPU 1 Fan 2-9 SLED SCSI LED 1-11
JT2 CPU 2 Fan 2-9 JT1 CPU 1 Fan 2-9
JT3 Thermal Control Fan 2-9 JT2 CPU 2 Fan 2-9
WOL Wake-on-LAN 2-9 JT3 Thermal Control Fan 2-9
JTM1 External Thermal Input 1-9 WOL Wake-on-LAN 2-9
(1-2) sensor 1
(3-4) sensor 3

viii
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA User’s Manual

Front Control Panel Connector

JF2 JF1 JF1

1 1 1

Hard
Drive Hard Drive
LED LED

IR Con

Power Power
LED LED
X

Keyboard
Keyboard
lock
lock
Power On

X
Speaker Speaker

Reset

IR Com
Please see pages 2-6 and 2-7 for
pin definitions.

Power On

Reset

JF2

ix
x
 Chapter 1: Introduction

Chapter 1
Introduction

1-1 Overview

SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA supports Pentium II 233/

266/300/333 MHz processors and *Celeron 266/300 or higher at 66MHz bus
speed or Pentium II 350/400 MHz processors at 100MHz bus speed. SUPER
P6DBU, P6DBS, and P6DBE supports dual Pentium II processors. SUPER
P6SBU/P6SBS/P6SBA supports a single Pentium II processor. All six
motherboards are based on Intel’s 440BX chipset which enables 66/100
MHz system bus speed, Accelerated Graphics Port (AGP), Wake-on-LAN,
SDRAM, concurrent PCI and Ultra DMA 33 MB/s burst data transfer rate.

While all of the motherboards are ATX form factor, P6DBU and P6DBE have
5 PCI and 2 ISA with one shared slot. SUPER P6DBS, P6SBU, P6SBS and
P6SBA have 4 PCI and 3 ISA with one shared slot. All six motherboards
have the AGP port, and can accommodate a total of 1 GB EDO at 66 MHz or
512 MB unbuffered SDRAM or 1 GB registered SDRAM memory with 4 168-
pin DIMM sockets.

AGP reduces contention with the CPU and I/O devices by broadening the
bandwidth of graphics to memory. It delivers a maximum of 532 MB/s 2x
transfer mode which is quadruple the PCI speed!

Wake on LAN allows remote network management and configuration of the

PC, even in off-hours when the PC is turned off. This reduces the com-
plexity of managing the network.

Other features that maximize customer satisfaction and simplicity in manag-

ing the computer are PC 98-ready and support for Advanced Configuration
and Power Interface (ACPI). With PC Health Monitoring, you can protect
your system from problems before they even occur.

Included I/O on all motherboards are 2 EIDE ports, a floppy port, an ECP/EPP
parallel port, a PS/2 mouse and PS/2 keyboard, 2 serial ports, an infrared
port and 2 USB ports. SUPER P6DBUand P6SBU provide on-board Adaptec
7890 Ultra II SCSI controller with data transfer rate of up to 80 MB/s, and
optional RAIDport III (ARO-1130xA-2)**. SUPER P6DBS and P6SBS have

*Note: Celeron is single processor only

** See bottom of page 2

1-1
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

integrated on-board Adaptec 7895 MultiChannel UW SCSI controller. The

dual channels allow data transfer rate of 40 MB/s per channel. Additionally,
these two motherboards have a RAID port on-board to support the Adaptec
ARO-1130xA RAIDport II card** for increase I/O performance and fault
tolerance.

**The x in 1130 xA and 1130 xA-2 refers to the RAIDport workstation driver (1130 CA) or server driver

(1130 SA) depending on software used. Please note: 1130 xA is compatible with NT Workstation, NT

Server and Netware Server. The 1130 xA-2 is only compatible with NT Workstation at this time. Check the

Adaptec web site for further information: www.adaptec.com.

1-2
 Chapter 1: Introduction

SUPER P6DBS

Figure 1-1. SUPER P6DBS Motherboard Picture

1-3
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

SUPER P6DBE

Figure 1-2. SUPER P6DBE Motherboard Picture

1-4
 Chapter 1: Introduction

SUPER P6DBU

Figure 1-3. SUPER P6DBU Motherboard Picture

1-5
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

SUPER P6SBU

Figure 1-4. SUPER P6SBU Motherboard Picture

1-6
 Chapter 1: Introduction

SUPER P6SBS

Figure 1-5. SUPER P6SBS Motherboard Picture

1-7
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

SUPER P6SBA

Figure 1-6. SUPER P6SBA Motherboard Picture

1-8
 Chapter 1: Introduction

9.65"

JT3 PWR_SEC
J34 JT1 JT2
J1 J2 1
PS/2 KB 1 1
PS/2 MOUSE CPU 1 CPU 2 1 J36
FAN FAN
J32
J17, J18 BZ
USB BZ_ON
JOH
1 JA3

ATX POWER
Overheat LED
JA1 1
J21 1
COM2

ULTRA SCSI
UW SCSI
J19
Parallel

Bank3

Bank2

Bank1

Bank0
Port
6"
U2
J20
COM1
BX
JA2 J22
1 1

UW SCSI
12"

FLOPPY
JB3
JB2
JB4

JB1

JP11 JA7
JP20 JA5
1 J8

AGP PORT J15 IDE 1

1
J12 J16 IDE 2
1
PCI 4
U48
J11 JBT1: CMOS Clear
UA1
JBT2: Ext Battery
JL1 JA5, JA6:
Chassis PCI 3 U14
Intrusion SCSI Termination
1 JTM 6"
J10
PIIX4E

JBT1
JBT2
P6DBS

JA6
U37 PCI 2 WOL
1 SCSI LED
J9 JA4
1
PCI 1 RAID PORT JP18 +
®

U15 BATTERY BT2

S UPER

JJ14

SBLINK -
1
J14
U38
IDE LED/KEYLOCK/SPEAKER
JF1
BIOS JF2
J13 IR CON PW_ON RESET

10.65"

——–—— Manufacturer Settings —–——— —————Pentium II CPU Speed–————

JBT1: 1-2 (default) JB1 JB2 JB3 JB4
2-3 CMOS Clear x3 ON OFF ON ON
* To clear the CMOS completely, x3.5 OFF OFF ON ON
disconnect the power source. x4 ON ON OFF ON
JL1: OFF (default) x4.5 OFF ON OFF ON
ON (intrusion) x5 ON OFF OFF ON
JP11: 1-2 Auto x5.5 OFF OFF OFF ON
2-3 66 MHz x6 ON ON ON OFF
OFF 100 MHz ——–—–————————————————
JP20: 1-2 PIIX CTL PD State
2-3 BIOS CTL PD State (default)
WOL: Wake-on-LAN
——–———————–——–—–——–——–—

*Note: To Enable Overheat Buzzer place a

jumper on BZ_On.

Figure 1-7. SUPER P6DBS Motherboard Layout

1-9
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

9.6"

J34 JT1 JT2 JT3

PS/2 KB J1 1 J2 1
PS/2 MOUSE CPU 1 CPU 2 1
FAN FAN Thermal PWR_SEC
J32 Control Fan 1
J17, J18
USB J36
BZ

ATX POWER
Overheat LED J22
J21 JOH1 1
COM2
BZ_ON

J19

Bank1
Bank3

Bank2

Bank0
Parallel
Port
U2
FLOPPY
J20
JP16 J16 J15
COM1
1 1
BX

IDE 2 IDE 1
JB4
JB3
JB2
JB1

12" JP11 12"

JP20
1
J8

AGP PORT

PCI 5 J12
U48
JBT1: CMOS Clear
JBT2: Ext Battery
JL1 PCI 4 J11
Chassis
Intrusion
U14
PCI 3 J10 +
P6DBE

U37 WOL
1 JTM PIIX4E
1
1 JL2 BATTERY BT2
PCI 2 J9 JP18
-
®

J35

JBT2
JBT1
PCI 1
SBLINK
1 U15
S UPER

U38
J14
1
BIOS

J13 IDE LED/KEYLOCK/SPEAKER

JF1
JF2
IR CON PW_ON RESET

9.6"

——–—— Manufacturer Settings —–——— —————Pentium II CPU Speed–————

JBT1: 1-2 (default) JB1 JB2 JB3 JB4
2-3 CMOS Clear x3 ON OFF ON ON
To clear the CMOS completely, x3.5 OFF OFF ON ON
disconnect the power source. x4 ON ON OFF ON
JL1: OFF (default) x4.5 OFF ON OFF ON
ON (intrusion) x5 ON OFF OFF ON
JP11: 1-2 Auto x5.5 OFF OFF OFF ON
2-3 66 MHz x6 ON ON ON OFF
OFF 100 MHz ——–—–————————————————
JP20: 1-2 PIIX CTL PD State
2-3 BIOS CTL PD State (default)
WOL: Wake-on-LAN *Note: To Enable Overheat Buzzer place a
——–—–——————–———–——–——–—
jumper on BZ_On.

Figure 1-8. SUPER P6DBE Motherboard Layout

1-10
 Chapter 1: Introduction

9.65"

J34 JT1 JT2 JT3 PWR_SEC

PS/2 KB J1 1 J2 1 1
PS/2 MOUSE CPU 1 CPU 2 1
J36
FAN FAN Thermal
J32 Control Fan
J17, J18
BZ
USB
BZ_ON
JOH

ATX POWER
JA3
Overheat LED 1
J21 JA2
COM2 1

ULTRA SCSI
UW SCSI
J19
Parallel

Bank3

Bank2

Bank1

Bank0
Port
6"
U2
J20
COM1 JA1
BX 1 J22
1

Ultra II LVD/SE
12"

FLOPPY
JB1
JB2
JB4
JB3

JP11
JP20
1 JBT1: CMOS Clear
J8 JBT2: Ext Battery
JA5, JA6:
AGP PORT SCSI Termination
UA1
J12 S-TERM
PCI 4
U48 IDE 1
1
J11 J15
JL1 IDE 2
Chassis PCI 3 U14 1
Intrusion J16
1 JTM 6"
1 JL2 J10 WOL
PIIX4E
P6DBU

PCI 2 JP18
U37
1

1 SLED
JBT1
J9 JA4 JBT2

PCI 1 RAID PORT +

®

J35
SBLINK U15 BATTERY BT2
S UPER

J14 -

U38
J13 IDE LED/KEYLOCK/SPEAKER
JF1
BIOS JF2
IR CON PW_ON RESET

10.65"

——–—— Manufacturer Settings —–——— —————Pentium II CPU Speed–————

JBT1: 1-2 (default) JB1 JB2 JB3 JB4
2-3 CMOS Clear x3 ON OFF ON ON
* To clear the CMOS completely, x3.5 OFF OFF ON ON
disconnect the power source. x4 ON ON OFF ON
JL1: OFF (default) x4.5 OFF ON OFF ON
ON (intrusion) x5 ON OFF OFF ON
JP11: 1-2 Auto x5.5 OFF OFF OFF ON
2-3 66 MHz x6 ON ON ON OFF
OFF 100 MHz ——–—–————————————————
JP20: 1-2 PIIX CTL PD State
2-3 BIOS CTL PD State (default)
WOL: Wake-on-LAN Note: JA3 is Optional
S-TERM: On: SCSI Termination Enable
Off: Termination Disable Note: To Enable Overheat Buzzer place a
——–———————–——–—–——–——–—
jumper on BZ_On.

Figure 1-9. SUPER P6DBU Motherboard Layout

1-11
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

8.875"

BZ_ON
J34 JT1 JT3

JOH
PS/2 KB J1 1 1
PS/2 MOUSE CPU FAN BZ

J32 JOH: Overheat LED

J17, J18
JT3: Thermal Control Fan
USB
JA5, JA6: SCSI Termination
JA3

ATX POWER
JA1 JA2
1 1 1
J21
COM2

Ultra II LVD/SE
ULTRA SCSI

UW SCSI
J19
Parallel

Bank3

Bank2

Bank1

Bank0
Port
S-TERM
U2
J16 J15
J20 1 1
COM1
J22
BX 1

J37

FLOPPY IDE 2 IDE 1

JP11
12" J35 J44 3860 12"
J39
J8

AGP PORT

ESS J12
1938 UA10
PCI 4 JBT1: CMOS Clear
JBT2: Ext Battery
JPSI
J11 7890
PCI 3 U14

J10
PIIX4E
U56 PCI 2 SCSI LED
JBT1
JBT2
P6SBU

J9 JA4 JB3
JB1
JB2
JB4

1
PCI 1 RAID PORT 1

JJ14
®

JP20
1
S UPER

J14 WOL 1 U38

JT2
BIOS
1
1 JTM1 J13 IDE LED/KEYLOCK/SPEAKER
JF1
JF2
JL1 IR CON PW_ON RESET

8.875"
——–—— Manufacturer Settings —–——— —————Pentium II CPU Speed–————
JBT1: 1-2 (default) JB1 JB2 JB3 JB4
2-3 CMOS Clear x3 ON OFF ON ON
To clear the CMOS completely, x3.5 OFF OFF ON ON
disconnect the power source. x4 ON ON OFF ON
JL1: OFF (default) x4.5 OFF ON OFF ON
ON (intrusion) x5 ON OFF OFF ON
JP11: 1-2 Auto x5.5 OFF OFF OFF ON
2-3 66 MHz x6 ON ON ON OFF
OFF 100 MHz ——–—–————————————————
JP20: 1-2 PIIX CTL PD State
2-3 BIOS CTL PD State (default)
WOL: Wake-on-LAN Note: JA3 is Optional
S-TERM: On: SCSI Termination Enable
Off: Termination Disable Note: To Enable Overheat Buzzer place a
——–———–————–———–——–——–—
jumper on BZ_On.

Figure 1-10. SUPER P6SBU Motherboard Layout

1-12
 Chapter 1: Introduction

8.875"

BZ_ON
J34 JT1 JT3

JOH
PS/2 KB J1 1 1
PS/2 MOUSE CPU FAN BZ

JA5
JA6
J32 JOH: Overheat LED
J17, J18
JT3: Thermal Control Fan
USB
JA5, JA6: SCSI Termination
JA3

ATX POWER
JA1 JA2
1 1 1
J21
COM2

ULTRA SCSI

UW SCSI
UW SCSI
J19
Parallel

Bank3

Bank2

Bank1

Bank0
Port

U2
J16 J15
J20 1 1
COM1
J22
BX 1

JL1 12"
12" Chassis
Intrusion
U48
FLOPPY IDE 2 IDE 1

JP11

J8
+ AGP PORT

BATTERY BT2 J12

JBT1: CMOS Clear UA1
PCI 4
JBT2: Ext Battery
-
J11

PCI 3 U14
1 JTM J10
PIIX4E
JBT1
JBT2
U56 PCI 2 SCSI LED

JB4

JB1
JB3
JB2
P6SBS

1
SBLINK J9 1
1 JA4
PCI 1 RAID PORT

JJ14 JP20
®

1
S UPER

J14 WOL 1 U38

BIOS JT2
J13
IDE LED/KEYLOCK/SPEAKER 1
JF1
JF2
IR CON PW_ON RESET

8.875"
——–—— Manufacturer Settings —–——— —————Pentium II CPU Speed–————
JBT1: 1-2 (default) JB1 JB2 JB3 JB4
2-3 CMOS Clear x3 ON OFF ON ON
To clear the CMOS completely, x3.5 OFF OFF ON ON
disconnect the power source. x4 ON ON OFF ON
JL1: OFF (default) x4.5 OFF ON OFF ON
ON (intrusion) x5 ON OFF OFF ON
JP11: 1-2 Auto x5.5 OFF OFF OFF ON
2-3 66 MHz x6 ON ON ON OFF
OFF 100 MHz ——–—–————————————————
JP20: 1-2 PIIX CTL PD State
2-3 BIOS CTL PD State (default)
WOL: Wake-on-LAN *Note: To Enable Overheat Buzzer place a
——–———–————–———–——–——–—
jumper on BZ_On.

Figure 1-11. SUPER P6SBS Motherboard Layout

1-13
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

7"

J34
PS/2 KB J1 JT1
1 BATTERY
PS/2 MOUSE -
CPU FAN
J32
J17, J18
USB BT2

ATX POWER
+

JOH
J21
J22
COM2
1
+
JT2 FLOPPY
J19
1
Parallel

Bank1
Bank2

Bank0
Port
U9 JT3
1 JF2
RESET
J20
PW_
COM1 BX ON
J15 J16
1 1
IR
CON
JP11
SPEA-
KER
KEY
LOCK
IDE
LED
12" IDE 1 IDE 2 JF1 12"
JP20
1 J8 JL1: Chassis Intrusion
U27 JOH: Overheat LED
AGP PORT JBT1: CMOS Clear
JBT2: Ext Battery
J12
JB1
PCI 4 JB2
U34 JB3
JB4
J11 JL1
WOL JBT2
PCI 3 1
U29
P6SBA

U14 1
J10
JBT1
PCI 2 PIIX4E SW2
BIOS 1
1
1 JTM
1 JL2 J9
®

PCI 1
S UPER

JJ14

J14

J13
PW-LED

7"
——–—— Manufacturer Settings —–——— —————Pentium II CPU Speed–————
JBT1: 1-2 (default) JB1 JB2 JB3 JB4
2-3 CMOS Clear x3 ON OFF ON ON
To clear the CMOS completely, x3.5 OFF OFF ON ON
disconnect the power source. x4 ON ON OFF ON
JL1: OFF (default) x4.5 OFF ON OFF ON
ON (intrusion) x5 ON OFF OFF ON
JP11: 1-2 Auto x5.5 OFF OFF OFF ON
2-3 66 MHz x6 ON ON ON OFF
OFF 100 MHz ——–—–————————————————
JP20: 1-2 PIIX CTL PD State
2-3 BIOS CTL PD State (default)
WOL: Wake-on-LAN
——–———————–———–—–—–——–—

Figure 1-12. SUPER P6SBA Motherboard Layout

1-14
 Chapter 1: Introduction

CPU CPU

Host Bus

AGP SDRAM
440BX
Port

PCI Slots

IO SMBus
APIC PIIX4E
Power IDE Ports SCSI
Management
USB
USB
Ports
ISA Slots

SIO
BIOS

Figure 1-13. 440BX AGP SET:

System Block Diagram (Dual Processors)

1-15
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

Features for P6DBS, P6DBE, P6DBU, P6SBU, P6SBS,

and P6SBA Motherboards*
* Bolded text notes variation in features.

The following list covers the general features of SUPER P6DBS, P6DBE,
P6DBU, P6SBU, P6SBS, and P6SBA.

CPU
• Dual Pentium II processor 233/266/300/333 MHz at 66 MHz bus speed
or 350/400 MHz at 100 MHz bus speed (Note: SUPER P6SBU, P6SBS, and

P6SBA support a Single Pentium II processor.)

Memory
• 1 GB EDO at 66 MHz or 512 MB unbuffered 3.3V SDRAM or 1 GB
registered SDRAM (P6DBS/P6DBE/P6DBU/P6SBU/P6SBS only)

• 768 MB EDO, 768 MB registered DIMM, 384 MB SDRAM (P6SBA only)

(Note: When CPU bus is running at 100 MHz, the SDRAM must be PC-100 compliant DIMMs)

(Note: The maximum memory cacheability size depends on processor capability)

• Error Checking and Correction and Error Checking support

Chipset
• Intel 440BX
Expansion Slots
P6DBS/P6SBU/P6SBS/P6SBA P6DBU/P6DBE

• 4 PCI slots • 5 PCI slots

• 3 ISA slots • 2 ISA slots
[one PCI/ISA shared slot] [one PCI/ISA shared slot]
• 1 AGP slot • 1 AGP slot
BIOS
• 2 Mb AMI® Flash BIOS
• APM 1.2, DMI 2.01, Plug and Play (PnP)
• Adaptec 7890 SCSI BIOS 2.01 (P6DBU/P6SBU only)

• Adaptec 7895 SCSI BIOS (P6DBS/P6SBS only)

PC Health Monitoring
• Seven on-board voltage monitors for CPU core(s), CPU I/O, +3.3V, ±5V,
and ±12V
• Three fans status monitors with firmware/software control on/off
• Environment temperature monitor and control
• CPU fan auto-off in sleep mode
• Chassis overheat alarm, LED, and control
• Chassis intrusion detection
• System resource alert
• Hardware BIOS virus protection

1-16
 Chapter 1: Introduction

• Switching voltage regulator for the CPU core

• SUPERMICRO SUPER Doctor and Intel® LANDesk® Client Manager
(LDCM) support
ACPI/PC 98 Features
• Microsoft OnNow
• Slow blinking LED for suspend-state indicator
• BIOS support for USB keyboard
• Real time clock wake-up alarm
• Main switch override mechanism
• External modem ring-on
On-Board I/O
• 68-pin 16-bit Ultra II LVD/SE SCSI connectors and 68-pin, 16 bit Ultra
Wide SCSI Connector / 50-pin 8-bit Ultra SCSI connector (P6DBU/P6SBU

only)

• 68-pin 16-bit Dual Ultra-Wide SCSI connectors and 50-pin 8-bit Ultra
SCSI connector (P6DBS/P6SBS only)

• RAID port for Adaptec ARO-1130xA RAIDport II card (P6DBS/P6SBS only)

• RAID port for Adaptec ARO-1130xA-2 RAIDport III card (P6DBU/P6SBU only)

• 2 EIDE Bus Master interfaces support Ultra DMA/33 and Mode 4

• 1 floppy port interface
• 2 Fast UART 16550 serial ports
• EPP (Enhanced Parallel Port) and ECP (Extended Capabilities Port)
parallel port
• PS/2 mouse and PS/2 keyboard
• Infrared port
• 2 USB (Universal Serial Bus) ports
• Solo-1 PCI AudioDrive® (P6SBU only)

CD Utilities
• Intel LANDesk Client Manager for Windows NT® and Windows ® 95
(optional)
• PIIX4 Upgrade Utility for Windows 95
• BIOS Flash Upgrade Utility
• SUPER Doctor Utility
• SCSI Utility, manual and driver
Dimensions
• SUPER P6DBS - ATX (12" x 9.65") * See board diagram for full measurements

• SUPER P6DBE - ATX (12" x 9.6")

• SUPER P6DBU - ATX (12" x 9.65") * See board diagram for full measurements

• SUPER P6SBU - ATX (12" x 8.875")

• SUPER P6SBS - ATX (12" x 8.875")
• SUPER P6SBA - ATX (12" x 7")
1-17
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

1-2 Chipset Overview

The 440BX chipset, developed by Intel, is the ultimate processor platform

targeted for 3D graphics and multimedia applications. Along with System-
to-PCI bridge integrated with optimized DRAM controller and data path, the
chipset introduces the Accelerated Graphics Port (AGP) interface. AGP is
a high performance, component level interconnect targeted at 3D applica-
tions and is based on a set of performance enhancements to PCI. The I/O
subsystem portion of the 440BX platform is based on the PIIX4E, a highly
integrated version of Intel's PCI-to-ISA bridge family.

The PCI/AGP and system bus interface controller (82443BX) supports up to

two Pentium II processors. It provides an optimized 72-bit DRAM interface
(64-bit data plus ECC). This interface supports 3.3V DRAM technologies.
The controller provides the interface to a PCI bus operating at 33 MHz. This
interface implementation is compliant with the PCI Rev 2.1 Specification.
The AGP interface is based on the AGP Specification Rev 1.0. It can
support up to 133 MHz (532 MB/s) data transfer rates.

1-3 PC Health Monitoring

This section describes the PC health monitoring features of SUPER P6DBU,

P6DBS, P6DBE, P6SBU, P6SBS, and P6SBA. They have an on-board Sys-
tem Hardware Monitor chip which can support PC health monitoring.

Seven On-Board Voltage Monitors for the CPU Core(s), CPU I/

O, +3.3V, ± 5V, and ± 12V

The on-board voltage monitor will scan the seven monitored voltages con-
tinuously. Once a voltage becomes unstable, it will report a warning or an
error message on the screen. Users can adjust the threshold of the moni-
tored voltage to determine the sensitivity of the voltage monitor.

Three-Fan Status Monitors with Firmware/Software Control

On/Off

The PC health monitor can check the RPM status of the cooling fans. The
on-board 3-pin CPU fan is controlled by the ACPI BIOS and the ACPI enabled
operating system. The thermal fans are controlled by the overheat detec-
tion logic.

1-18
 Chapter 1: Introduction

Environment Temperature Control

The thermal control sensor will monitor the real-time CPU temperature. It will
turn on the back-up fan whenever the CPU temperature goes over the user-
defined threshold. The overheat circuitry runs independently from the CPU.
It can still monitor the overheat condition even if the CPU is in sleep mode.
Once it detects that the CPU temperature is too high, it will automatically turn
on the back-up fan to prevent any overheat damage to the CPU. The on-
board chassis thermal circuitry can monitor the overall system temperature
and alert users when the chassis temperature is too high.

CPU Fan Auto-Off in Sleep Mode

The CPU fan will turn on when the power is on. It can be turned off when
the CPU is in sleep mode. When the CPU is in sleep mode, it will not run at
full power, thereby generating less heat. For power saving purposes, the
user has the option to shut down the CPU fan.

CPU Overheat Alarm, LED and Control in P6DBS/P6DBE/

P6DBU/P6SBU/P6SBS

This feature is available when the user enables the CPU overheat warning
function in the BIOS. The overheat alarm will activate when the CPU tem-
perature exceeds the temperature configured by the user. When the over-
heat alarm is activated both the overheat fan and LED are triggered.

Chassis Intrusion Detection

The chassis intrusion circuitry can detect unauthorized intrusion to the sys-
tem. The chassis intrusion connector is located on JL1. Attach a micro-
switch to JL1. When the micro-switch is closed, it means that the chassis
has been opened. The circuitry will then alert the user with a warning
message when the system is turned on. This feature is available when the
user is running Intel's LANDesk Client Manager, and SUPERMICRO's Super
Doctor.

System Resource Alert

This feature is available when used with Intel's LANDesk Client Manager.
The user can be notified of certain system events. For example, if the
system is running low on virtual memory, the hard drive space is not enough
to save the data, you are then alerted of the potential problems.

1-19
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

Hardware BIOS Virus Protection

The system BIOS is protected by hardware so that no virus can infect the
BIOS area. The user can only change the BIOS content through the flash
utility provided by SUPERMICRO. This feature can prevent viruses from
infecting the BIOS area and loss of valuable data.

Switching Voltage Regulator for the CPU Core

The switching voltage regulator for the CPU core can support up to 20A
current, with auto-sensing voltage ID ranging from 1.8v to 3.5v. This will
allow the regulator to run cooler and make the system more stable.

Intel LANDesk ® Client Manager (LDCM) Support

As the computer industry grows, PC systems have become more complex

and harder to manage. Historically, only experts have been able to fully
understand and control these complex systems. Today's users want man-
ageable systems that interact automatically with the user. Client Manager
enables both administrators and clients to:

• Review system inventory

• View DMI-compliant component information
• Back-up and restore system configuration files
• Troubleshoot
• Receive notification for system events
• Transfer files to and from client workstations
• Remotely reboot client workstations

1-4 Solo-1 TM PCI AudioDrive ® (Optional for P6SBU)

The Solo-1 PCI AudioDrive solution implements a single chip PCI audio solu-
tion, providing high-quality audio processing while maintaining full legacy
DOS game compatibility. With a dynamic range over 80 dB, the Solo-1
complies with the Microsoft PC 97/PC 98 specifications and meets WHQL
audio requirements.

The Solo-1 incorporates a microcontroller, ESFM TM music synthesizer, 3-D

stereo effects processor, 16-bit stereo wave ADC and DAC, 16-bit stereo
music DAC, MPU-401 UART mode serial port, dual game port, hardware
master volume control, a serial port interface to external wavetable music

1-20
 Chapter 1: Introduction

synthesizer, DMA control logic with FIFO, and PCI bus interface logic. There
are three stereo inputs (LINE-IN, LINE-OUT, MIC IN) and a mono microphone
input.

1-5 ACPI/PC 98 Features

ACPI stands for Advanced Configuration and Power Interface. The ACPI
specification defines a flexible and abstract hardware interface that pro-
vides a standard way to integrate power management features throughout
a PC system, including hardware, operating system and application soft-
ware. This enables the system to automatically turn on and off peripherals
such as CD-ROMs, network cards, hard disk drives, and printers. This also
includes consumer devices connected to the PC such as VCRs, TVs,
phones, and stereos.

In addition to enabling operating system-directed power management, ACPI

provides a generic system event mechanism for Plug and Play and an oper-
ating system-independent interface for configuration control. ACPI lever-
ages the Plug and Play BIOS data structures while providing a processor
architecture-independent implementation that is compatible with both Win-
dows 98 and Windows NT 5.0.

Microsoft OnNow

The OnNow design initiative is a comprehensive, system-wide approach to

system and device power control. OnNow is a term for a PC that is always
on but appears off and responds immediately to user or other requests.

Slow Blinking LED for Suspend-state Indicator

When the CPU goes into a suspend state, the power LED will start blinking
to indicate that the CPU is in suspend mode. When the user presses any
key, the CPU will wake-up and the LED will automatically stop blinking and
remain on.

BIOS Support for USB Keyboard

If the USB keyboard is the only keyboard in the system, the USB keyboard
will work like a normal keyboard during system boot-up.

1-21
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

Real Time Clock Wake-up Alarm

The PC is perceived to be off when not in use, but is still capable of

responding to preset wake-up events. In the BIOS the user can set a timer
to wake-up the system at a predetermined time.

Main Switch Override Mechanism

W hen an ATX power supply is used, the power button can function as a
system suspend button. When the user presses on the power button, the
system will enter a SoftOff state. The monitor will be suspended, and the
hard drive will spin down. Pressing the power button again will cause the
whole system to wake-up. During the SoftOff state, the ATX power supply
provides power to keep the required circuitry on the system alive. In case
the system malfunctions and you want to turn off the power, just press
down on the power button for 4 seconds. The power will turn off and no
power is provided to the motherboard.

External Modem Ring-on

Wake-up events can be triggered by a device such as the external modem

ringing when the system is in SoftOff state.

1-6 Wake-On-LAN (WOL)

W ake-on-LAN is defined as the ability of a management application to re-

motely power up a computer which is powered off. Remote PC setup,
updates, and asset tracking can occur after hours and on weekends so
daily LAN traffic is kept to a minimum and users are not interrupted.

The motherboards have a 3-pin header (WOL) used to connect to the 3-pin
header on the Network Interface Card (NIC) which has WOL capability.
Note that Wake-On-Lan can only be used with an ATX power connector on-
board.

1-7 Power Supply

As with all computer products, a stable power source is necessary for

proper and reliable operation. It is even more important for high CPU clock
rates like 233, 266, 300, 333, 350 or 400 MHz Pentium II processor.

1-22
 Chapter 1: Introduction

SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA accommodates ATX

power supplies. Although most power supplies generally meet the specifi-
cations required by the CPU, some power supplies are not adequate.

It is highly recommended that you use a high quality power supply which
meets ATX power supply specification 2.01. Additionally, in areas where
noisy power transmission is present, you may choose to install a line filter
to separate noise from the computer. You can also install a power surge
protector to help avoid problems caused by power surges.

1-8 Super I/O

The disk drive adapter functions of Super I/O chip include a floppy disk
drive controller compatible with the industry standard 82077/765, data
separator, write pre-compensation circuit, decode logic, data rate selection,
clock generator, drive interface control logic, and interrupt and DMA logic.
The wide range of functions integrated onto the Super I/O greatly reduced
the number of components required for interfacing with floppy disk drives.
The Super I/O supports four 360 K, 720 K, 1.2 M, 1.44 M or 2.88 M disk
drives and data transfer rates of 250 Kb/s, 500 Kb/s or 1 Mb/s.

The Super I/O provides two high speed serial communication ports (UARTs),
one of which supports serial Infrared communication. Each UART includes
a 16-byte send/receive FIFO, a programmable baud rate generator, com-
plete modem control capability, and a processor interrupt system. Both
UARTs provide legacy speed with baud rate up to 115.2 Kbps and also
advanced speed with baud rates of 230 K, 460 K, or 921 Kbps which
support higher speed modems.

The Super I/O supports one PC-compatible printer port (SPP), Bi-directional
Printer Port (BPP) and also Enhanced Parallel Port (EPP) and Extended Ca-
pabilities Port (ECP). Also available, through the printer port interface pins,
are: Extension FDD Mode and Extension 2FDD Mode allowing one or two
external floppy disk drives to be connected.

The Super I/O provides functions that comply with ACPI (Advanced Con-
figuration and Power Interface), which includes support of legacy and ACPI
power management through SMI or SCI function pin. It also has auto power
management to reduce power consumption.

1-23
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

The Super I/O complies with Microsoft PC97 Hardware Design Guide.
IRQs, DMAs, and I/O space resources are flexible to adjust to meet ISA PnP
requirement. Moreover, it meets the specification of PC97's requirement in
the power management: ACPI and DPM (Device Power Management).

1-9 AIC -7895 MultiChannelTM single-chip UltraSCSI

SUPER P6DBS/P6SBS has an on-board SCSI controller which is 100% com-

patible with all major operating and hardware platforms. PCI 2.1 and SCAM
Level 1 compliance are assured. Two independent UltraSCSI channels pro-
vide a per channel data transfer rate of 40 MB/s. Connectors include two
68-pin 16-bit Ultra Wide SCSI connectors (JA1/JA2) and a 50-pin 8-bit Ultra
SCSI connector (JA3). You can connect up to 15 devices (seven 8-bit
internal and eight 16-bit internal or external SCSI devices, or 15 Wide inter-
nal and external SCSI devices).

When Fast SCSI devices are connected, the total length of all cables (inter-
nal and external) must not exceed 3 meters (9.8 ft) to ensure reliable opera-
tion. If no Fast SCSI devices are connected, the total length of all cables
must not exceed 6 meters (19.7 ft).

AIC-7895 consolidates the functions of two SCSI chips, eliminating the need
for a PCI bridge. Reducing PCI bus loading enables system capabilities to be
expanded with additional PCI devices.

The AIC-7895 functions with Adaptec RAIDport II (ARO-1130xA) to de-

liver RAID functionality.

1-10 AIC -7890 Ultra II SCSI

Note: If you are using a low voltage differential Hard Drive, it is recommended you use LVD/SE Ultra

II SCSI cable. LVD/SE cable offers increased length, and can accommodate more devices.

SUPER P6DBU/P6SBU has an on-board SCSI controller which is 100% com-

patible with all major operating and hardware platforms. The AIC-7890
controller provides advanced PCI-to-SCSI Ultra2 SCSI host adapter features
in a 272-pin Ball Grid Array (BGA) package, as well as containing an inte-
grated dual mode (LVD/SE) transceiver. The AIC-7890 Ultra2 SCSI chip
connects to a 32-bit PCI bus. It is PCI 2.1 compliant, and fully supports the
power management requirements specified in Microsoft's PC 97 guidelines
and it provides SCAM level 2 support. The AIC-7890 functions with
Adaptec RAIDport III (ARO-1130xA-2) to deliver RAID functionality.

1-24
 Chapter 1: Introduction

The AIC-7890 Ultra2 SCSI controller, used together with the AIC-3860 trans-
ceiver, allows Ultra2 and single-ended devices to operate together on the
same SCSI bus without inpacting Ultra2 performance and cable lengths.
The AIC-7890 controller can support external High Voltage Differential
(HVD) transceivers only for Ultra data rates.

1-11 Warranty, Technical Support, and Service

The manufacturer will repair or exchange any unit or parts free of charge
due to manufacturing defects for two years (24 months) from the original
invoice date of purchase.

Warranty Terms and Conditions

Super Micro Computer, Inc. warrants its products to be free from defects in
material and workmanship. The warranty period is two years (24 months)
beginning from the original purchase date. Super Micro shall, at our option
and cost, repair or replace the defective product if the product is returned
within the applicable warranty period and if the product is found by Super
Micro to be defective within the terms of this warranty. Before presenting
any motherboard for warranty service, the customer must first remove the
CPU(s), memory, or other peripherals.

This warranty shall not apply to any failure or defect caused by misuse,
abnormal or unusually heavy use, neglect, abuse, alteration, improper in-
stallation, unauthorized repair or modification, improper testing, accident or
causes external to the product such as, but not limited to, excessive heat or
humidity, power failure, power surges, or acts of God/Nature. Super Micro
makes no warranty with respect to (i) expendable components, (ii) any
software products supplied by us, (iii) any experimental or developmental
products, and (iv) products not manufactured by us; all of which compo-
nents, software and products are provided "AS-IS."

This warranty is in lieu of any other warranty expressed or implied. In no

event will Super Micro be held liable for incidental or consequential dam-
ages, such as loss of revenue or loss of business arising from the pur-
chase of Super Micro products.

1-25
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

Returns

If you must return products for any reason, refer to Chapter 3 in this
manual, “Returning Merchandise for Service.”

1-26
 Chapter 2: Installation

Chapter 2
Installation

2-1 Static-Sensitive Devices

Static-sensitive electric discharge can damage electronic components. To

prevent damage to your system board, it is important to handle it very
carefully. The following measures are generally sufficient to protect your
equipment from static discharge.

Precautions

• Use a grounded wrist strap designed for static discharge.

• Touch a grounded metal object before you remove the board from the
anti-static bag.
• Handle the board by its edges only; do not touch its components, periph-
eral chips, memory modules, or gold contacts.
• When handling chips or modules, avoid touching their pins.
• Put the system board and peripherals back into their anti-static bags
when not in use.
• Be sure your computer system’s chassis allows excellent conductive
contacts between its power supply, case, mounting fasteners, and the
system board for grounding purposes.

Unpacking

The system board is shipped in anti-static packaging to avoid static damage.

When unpacking the board, be sure the person handling the board is static-
protected.

2-2 Pentium II Processor Installation

When handling the Pentium II processor, avoid placing

!
direct pressure on the label area of the fan.

1. Check the Intel boxed processor kit for the following items: the proces-
sor with the fan heatsink attached, two black plastic pegs, two black plastic
supports, and one power cable.

2-1
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

2. Install the retention mechanism attach mount under the motherboard. Do

this before mounting the motherboard into the chassis. Do not screw too
tightly. Mount the two black plastic pegs onto the motherboard (Figure 2.1).
These pegs will be used to attach the fan heatsink supports. Notice that
one hole and the base of one peg are larger than the other hole and peg
base. Push each peg into its hole firmly until you hear it "click" into place.

Figure 2-1. Mounting the Pegs

Retention
Mechanism

Large peg and hole

3. Slide a black plastic support onto each end of the fan heatsink, making
sure that the hole and clip are on the outside edge of the support. If the
supports are reversed, the holes will not line up with the pegs on the
motherboard. Slide each support toward the center of the processor until
the support is seated in the outside groove in the fan housing.

4. Slide the clip (A) on each support toward the processor, exposing the
hole that will fit over the peg on the motherboard. Push the latches (B) on
the processor toward the center of the processor until they click into place.

5. Hold the processor so that the fan shroud is facing toward the pegs on
the motherboard. Slide the processor (C in Figure 2-2) into the retention
mechanism and slide the supports onto the pegs. Ensure that the pegs on
the motherboard slide into the holes in the heatsink support and that the

2-2
 Chapter 2: Installation

alignment notch in the SEC cartridge fits over the plug in Slot 1. Push the
processor down firmly, with even pressure on both sides of the top, until it
is seated.

Figure 2-2. Retention Mechanism

Top of Processor

Do not screw too tightly!

6. Slide the clips on the supports (A) forward until they click into place to
hold the pegs securely. Apply slight pressure on the peg and push the peg
toward the clip while pushing the clip forward. Push the latches on the
processor (B) outward until they click into place in the retention mechanism.
The latches must be secured for proper electrical connection of the proces-
sor.

7. Attach the small end of the power cable (C in Figure 2-3) to the three-
pin connector on the processor, then attach the large end to the three-pin
connector on the motherboard.

2-3
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

Figure 2-3. Attaching the Fan Power Cable

OEM Pentium II and Heat Sink Support

The heat sink support consists of a top bar, a base bar, four posts on the
top bar and two posts on the base bar. The two posts on the base snap
into the motherboard. Install the two pins into the base bar. Insert the
Pentium II with the heat sink on it into Slot 1. Install the top support bar. The
four top posts should be close to Slot 1. The bottom most row of fins in the
heat sink should fit between the top support bar and the bottom support bar
as shown in Figure 2-4.

Removing the Pentium II Processor

To remove the Pentium II processor from the motherboard, follow the re-
verse of the installation process. Note: Do not reuse the pegs.

Figure 2-4. Heat Sink Support

2-4
 Chapter 2: Installation

When removing the Pentium II processor, avoid pressing

down on the motherboard or components. Instead, press
!
down on the plastic connectors.

2-3 Installation of the Universal Retention

Mechanism (URM)*

Please Note! Screws and washers attach from the bottom of the
board and must be installed before mounting the board to the
chassis. (See figures 2-5 and 2-6)
1. When Installing the URM be sure Left (L) and Right (R) sides are
placed accordingly.

2. Lift arms upright and slide processor into socket, noting that notches
need to line up.

*These directions may not apply to second source URMs

2-4 Special Instructions for the Celeron Processor

Please Note! The Celeron Processor requires special caps to hold

it in place (caps are bundled with the motherboard). (See figures
2-5 and 2-6)
1. Lift URM's arms to upright position.

2. Slide Celeron into the socket, noting that notches need to line up.

3. Slide the special Celeron caps over the ends of the retention arms.
Make sure the arrows face outward and that the Left (L) and Right (R)
cap are on the appropriate sides of the URM. Caps should snap into
place.

4. To remove caps, pull out on the tab (arrows points to tab), then pull
up.

2-5
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

Figure 2-5. Installing the Celeron Processor

Figure 2-6. URM and Celeron Installation

Supero

L R
R
L

Screw holes for

retention
mechanism URM with arms folded

Note: Left and Right arms are defined

R

Note notch in socket

Tab

Top view of Celeron cap

2-6
 Chapter 2: Installation

2-5 Explanation and

Diagram of Jumper/
Connector Connector
Pins

3 2 1
To modify the operation of the
motherboard, jumpers can be used
Jumper
to choose settings. Jumpers cre- Cap

ate shorts between two pins and

change the function of the con-
Setting
nector. Pin 1 is identified with a
square. Pin 1-2 short

2-6 Changing the CPU

Speed Table 2-1
Pentium II Speed Selection

To change the CPU speed for a CPU Core/

Bus Ratio JB1 JB2 JB3 JB4
Pentium II processor, change the 3.0 ON OFF ON ON
3.5 OFF OFF ON ON
jumpers shown on Table 2-1. The 4.0 ON ON OFF ON
example on the right will show you 4.5 OFF ON OFF ON
5.0 ON OFF OFF ON
which CPU Core/Bus Ratio to use. 5.5 OFF OFF OFF ON
6.0 ON ON ON OFF
The general rule is to divide the
CPU speed by the bus speed (100 400 MHz = 100 MHz x 4.0

MHz). If you have a 400 MHz CPU, CPU Speed = Bus Freq. x Ratio

dividing it by 100 will give you a Example of 4.0

CPU Core/Bus Ratio
CPU Core/BUS Ratio of 4.0. After JB1 JB2 JB3 JB4
ON ON OFF ON
determining the CPU Core/Bus Ra-
tio, refer to Table 2-1 for settings
of JB1, JB2, JB3 and JB4.

Note: SUPER P6DBU/P6SBU must be running at

100 MHz bus speed to support Pentium II 350/400

MHz processors.

2-7
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

2-7 Mounting the Motherboard in the Chassis

All the motherboards have standard mounting holes to fit different types of
chassis. Chassis may come with a variety of mounting fasteners, made of
metal or plastic. Although a chassis may have both metal and plastic fas-
teners, metal fasteners are the most highly recommended because they
ground the system board to the chassis. Therefore, use as many metal
fasteners as possible for better grounding.

2-8 Connecting Cables

Table 2-2
Power Supply Connector ATX Power Supply Connector
Pin Definitions for J32

After you have securely mounted Pin Number Definition Pin Number Definition
1 3.3V 11 3.3V
the motherboard to the chassis, 2 3.3V3 12 -12V
3 Ground 13 Ground
you are ready to connect the 4 5V 14 PS-ON
cables. Attach power supply 5 Ground 15 Ground
6 5V 16 Ground
cables to J32 for an ATX power 7 Ground 17 Ground
8 PW-OK 18 -5V
supply. See Table 2-2 for pin defi- 9 5VSB 19 5V
nitions of an ATX power supply. 10 12V 20 5V

Secondary Power Connector

Table 2-3
Secondary Power Connector
The Secondary Power Connector J36
Pin
is recommended when a heavy Number Definition
load of peripherals have been 1 Ground
2 Ground
connected to the motherboard. 3 Ground
4 +3.3V
Note: Be sure to use a 1 X 6 pin connector and
5 +3.3V
check the power supply layout before attach- 6 +5V (keyed)

ing it. The Secondary Power Con- *P6DBE/P6DBS/P6DBU only

nector is located on J36. See
Table 2-3 for pin definitions.
Table 2-4
Infrared Pin
Infrared Connector Definitions
for JF2
Pin
The infrared connector is located Number Definition
on pins 1-8 of JF2. See Table 2-4 1 +5V
2 Key
for pin definitions. 3 IRRX
4 Ground
5 IRTX
6 NC
7 NC
8 NC

2-8
 Chapter 2: Installation

PW_ON Connector

The PW_ON connector is located

on pins 9 and 10 of JF2. Momen-
Table 2-5
tarily contacting both pins will PW-ON Connector
power on/off the system. The Pin Definitions
for JF2
user can also configure this but-
Pin
ton to function as a suspend but- Number Definition
9 PW_ON
ton. (See BIOS setup information 10 Ground
on page 5-13). To turn off the
power when set to suspend mode,
hold down the power button for at
least 4 seconds. See Table 2-5
for pin definitions.

Reset Connector
Table 2-6
Reset Pin
The reset connector is located on Definitions
for JF2
pins 12 and 13 of JF2. This con-
Pin
nector attaches to the hardware Number Definition
12 Ground
Reset switch on the computer 13 Reset
case. See Table 2-6 for pin defi-
nitions.
Table 2-7
Hard Drive LED Pin
Hard Drive LED Definitions
for JF1

The hard drive LED is located on Pin

Number Definition
pins 1 to 4 of JF1. Attach the hard 1 +5V
2 HD Active
drive LED cable onto pins 1 and 2. 3 HD Active
See Table 2-7 for pin definitions. 4 +5V

Keylock/Power LED Table 2-8

Connector Keylock/Power LED Pin Definition
for JF1
Pin
The keylock/power LED connector Number Function Definition
5 VCC +5V Red wire, LED power
is located on pins 5 to 9 of JF1.
6 VCC +5V Red wire, LED power
See Table 2-8 for pin definitions. 7 Ground LED control
8 Keyboard inhibit
Pins 5 and 7 are for the power 9 Ground Black wire
LED. Pins 8 and 9 are for the
keylock.

2-9
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

Table 2-9
Speaker Connector Speaker Connector Pin Definitions for
JF1

The speaker connector is located Pin

Number Function Definition
on pins 10 to 13 of JF1. See Table 10 + Red wire, Speaker data
11 Key No connection
2-9 for pin definitions. 12 Key
13 Speaker data

Power Save State Select

Refer to Table 2-10 to set JP20. Table 2-10

Power Save State Select
Power Save State Select is used Pin Definitions
when you want the system to be for JP20
Jumper
in power off state the first time
Position Definition
you apply power to the system or 1-2 PIIX4 Ctrl
2-3 Save PD State
when the system comes back
from AC power failure. In this
Position Position
state, the power will not come on 1-2 2-3
unless you hit the power switch

Save PD State
on the motherboard. PIIX4 control
PIIX4 Ctrl

is used if you want the system to

be in power on state the first time
you apply power to the system or
when the system comes back
from AC power failure.
Table 2-11
ATX PS/2
Keyboard
and PS/2 Mouse
ATX PS/2 Keyboard and Ports
Pin Definitions
PS/2 Mouse Ports for J34

Pin
The ATX PS/2 keyboard and the Number Definition
1 Data
PS/2 mouse are located on J34. 2 NC
3 Ground
See Table 2-11 for pin definitions. 4 VCC
5 Clock
6 NC

Table 2-12
Universal Serial Bus Pin Definitions
Universal Serial Bus
J17 J18
Pin Pin
The two Universal Serial Bus con- Number Definition Number Definition
1 +5V 1 +5V
nectors are located on J17 and 2 P0- 2 P0-
J18. See Table 2-12 for pin defini- 3 P0+ 3 P0+
4 Ground 4 Ground
tions. 5 N/A 5 Key

2-10
 Chapter 2: Installation

ATX Serial Ports Table 2-13

ATX Serial Ports Pin Definitions
J20 J21
ATX serial port COM1 is located Pin Number Definition Pin Number Definition
on J20 and serial port COM2 is 1 DCD 6 CTS
2 DSR 7 DTR
located on J21. See Table 2-13 3 Serial In 8 RI
4 RTS 9 Ground
for pin definitions. 5 Serial Out 10 NC

CMOS Clear
Table 2-14
Refer to Table 2-14 for instruc- CMOS Clear Pin Definitions
for Number JBT1
tions on how to clear the CMOS.
Jumper
For ATX power supply, you Position Definition
1-2 Normal
need to completely shut down 2-3 CMOS Clear
the system, then use JBT1 to
Position Position
clear the CMOS. Do not use the 1-2 2-3
PW_ON connector to clear the
CMOS. A second way of reset-

CMOS Clear
Normal
ting the CMOS contents is by
pressing the <ins> key, then turn-
ing on the system power. Release
the key when the power comes
on.
Table 2-15
External Battery Pin
External Battery Definitions
for JBT2
Pin
Connect an external battery to Number Definition
1 +3V
JBT2. Refer to Table 2-15 for pin 2 NC
3 NC
definitions. 4 Ground

Table 2-16
Wake-on-LAN Wake-on-LAN Pin
Definition located at
WOL
The Wake-on-LAN connector is lo-
Pin
cated on WOL. Refer to Table 2- Number Definition
16 for pin definitions. 1 +5V Standby
2 Ground
3 Wake up

Fan Connectors* Table 2-17

Fan Connectors Pin
Definitions for JT1, JT2, JT3
The thermal/overheat fan is lo- Pin
cated on JT3. The CPU fans are Number Definition
1 Ground (black)
located on JT1 and JT2. Refer to 2 +12V (red)
3 Tachometer
Table 2-17 for pin definitions.
* Caution: These fan connectors
are DC direct.

2-11
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

Chassis Intrusion
Table 2-18
Chassis Intrusion
The Chassis Intrusion Detector is Detector Settings on
JL1
located on JL1. See chapter one,
Pin
board layouts, and PC Health Moni- Number Definition
tor page 1-18 for more information. 1 Intrusion Input
2 Ground
See Table 2-18 for pin definitions. Open = Default, Close = Intrusion

2-9 Installing the DIM Modules

CAUTION
Exercise extreme care when installing or removing the DIM
modules to prevent any possible damages.

DIM Module Installation

1. Insert DIM modules in Bank 0 through Bank 3 as required for the

desired system memory.
2. Insert each DIM module vertically into its socket. Pay attention to the
two notches to prevent inserting the DIMM at a wrong position. The
component side of the DIM module must face the CPU socket. The
prior statement is applicable for DIMMs with components on one side
only.
3. Gently press the DIM module until it snaps upright into place in the
socket.

4. For best results, install DIMM starting from bank 0 (the DIMM socket
farthest from BX chip)

2-12
 Chapter 2: Installation

Side View of DIMM Installation into Socket

PC100 PC100
To Install: Notches Notches

Insert DIMM
vertically,
press down
until it snaps
into place. Note: Notches
Pay attention should align
with the
to the two receptive points
notches. on the socket

DIMM Socket

To Remove:
Use your thumb to
Top View of DIMM Socket gently push the
edge of the socket
and release the
module. Do this on
both sides for each
module.

Figure 2-7. Installing the DIMM

2-10 Connecting Parallel, Floppy and Hard Disk Drives

Use the following information to connect the floppy and hard disk drive
cables.

• The floppy disk drive cable has seven twisted wires.

• A red mark on a wire typically designates the location of pin 1.
• A single floppy disk drive ribbon cable has 34 wires and two connectors
to provide for two floppy disk drives. The connector with twisted wires
always connects to drive A, and the connector that does not have the
twisted wires always connects to drive B.
• An IDE hard disk drive requires a data ribbon cable with 40 wires, and a
SCSI hard disk drive requires a SCSI ribbon cable with 50 wires. A wide
SCSI hard disk drive requires a SCSI ribbon cable with 68 wires.
• A single IDE hard disk drive cable has two connectors to provide for two
drives. To select an IDE disk drive as C, you would normally set the
drive select jumper on the drive to DS1 (or Master). To select an IDE disk
drive as D, you would normally set the drive select jumper on the drive to
DS2 (or Slave). Consult the documentation that came with your disk
drive for details on actual jumper locations and settings.
• A single SCSI ribbon cable typically has three connectors to provide for

2-13
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

two hard disk drives and the SCSI adapter. (Note: most SCSI hard drives
are single-ended SCSI devices.) The SCSI ID is determined by jumpers or
a switch on the SCSI device. The last internal (and external) SCSI device
cabled to the SCSI adapter must be terminated.

Table 2-19
Parallel Port Pin Definitions for Connector J19

Pin Number Function Pin Number Function

1 Strobe- 2 Auto Feed- Parallel Port Connector
3 Data Bit 0 4 Error-
5 Data Bit 1 6 Init-
7 Data Bit 2 8 SLCT IN- The parallel port is located on J19.
9 Data Bit 3 10 GND
11 Data Bit 4 12 GND See Table 2-19 for pin definitions.
13 Data Bit 5 14 GND
15 Data Bit 6 16 GND
17 Data Bit 7 18 GND
19 ACK 20 GND
21 BUSY 22 GND
23 PE 24 GND Table 2-20
25 SLCT 26 NC Floppy Connector Pin Definitions for J22
Pin Number Function Pin Number Function
1 GND 2 FDHDIN
3 GND 4 Reserved
5 Key 6 FDEDIN
7 GND 8 Index-
Floppy Connector 9 GND 10 Motor Enable
11 GND 12 Drive Select B-
13 GND 14 Drive Select A-
The floppy connector is located 15 GND 16 Motor Enable
on J22. See Table 2-20 for pin 17 GND 18 DIR-
19 GND 20 STEP-
definitions. 21 GND 22 Write Data-
23 GND 24 Write Gate-
25 GND 26 Track 00-
27 GND 28 Write Protect-
29 GND 30 Read Data-
31 GND 32 Side 1 Select-
33 GND 34 Diskette

Table 2-21
IDE Connector Pin Definitions

Pin Number Function Pin Number Function

1 Reset IDE 2 GND
3 Host Data 7 4 Host Data 8
5 Host Data 6 6 Host Data 9
7 Host Data 5 8 Host Data 10
9 Host Data 4 10 Host Data 11
11 Host Data 3 12 Host Data 12
13 Host Data 2 14 Host Data 13 IDE Interfaces
15 Host Data 1 16 Host Data 14
17 Host Data 0 18 Host Data 15
19 GND 20 Key There are no jumpers to config-
21 DRQ3 22 GND
23 I/O Write- 24 GND ure the on-board IDE interfaces
25 I/O Read- 26 GND
27 IOCHRDY 28 BALE
J15 and J16. Refer to Table 2-
29 DACK3- 30 GND 21 for the pin definitions.
31 IRQ14 32 IOCS16-
33 Addr 1 34 GND
35 Addr 0 36 Addr 2
37 Chip Select 0 38 Chip Select 1-
39 Activity 40 GND

2-14
 Chapter 2: Installation

Table 2-22
68-pin Single End SCSI Connector Pin

Pin Number Function Pin Number Function

1 GND 35 -DB (12)
2 GND 36 -DB (13)
3 GND 37 -DB (14)
4 GND 38 -DB (15)
5 GND 39 Parity H
SCSI Connectors 6 GND 40 -DB (0)
7 GND 41 -DB (1)
8 GND 42 -DB (2)
There are no jumpers to configure 9 GND 43 -DB (3)
10 GND 44 -DB (4)
the on-board Single End SCSI in- 11 GND 45 -DB (5)
12 GND 46 -DB (6)
terface. Refer to Table 2-22 for 13 GND 47 -DB (7)
pin definitions. Refer to Table 2- 14 GND 48 Parity L
15 GND 49 GND
23 for the pin definitions for Wide 16 GND 50 Termpwrd
17 Termpwrd 51 Termpwrd
SCSI pin definitions. 18 Termpwrd 52 Termpwrd
19 GND 53 NC
20 GND 54 GND
21 GND 55 -ATTN
22 GND 56 GND
23 GND 57 -BSY
24 GND 58 -ACK
25 GND 59 -RST
26 GND 60 -MSG
27 GND 61 -SEL
28 GND 62 -CD
29 GND 63 -REQ
30 GND 64 -IO
31 GND 65 -DB (8)
32 GND 66 -DB (9)
33 GND 67 -DB (10)
34 GND 68 -DB (11)

Table 2-23
50-pin Wide SCSI Connector Pin Definitions
Pin Number Function Pin Number Function
1 GND 26 -DB (0)
2 GND 27 -DB (1)
3 GND 28 -DB (2)
4 GND 29 -DB (3)
5 GND 30 -DB (4)
6 GND 31 -DB (5)
7 GND 32 -DB (6)
8 GND 33 -DB (7)
9 GND 34 -DB (P)
10 GND 35 GND
11 GND 36 GND
12 Reserved 37 Reserved
13 Open 38 Termpwr
14 Reserved 39 Reserved
15 GND 40 GND
16 GND 41 -ATN
17 GND 42 GND
18 GND 43 -BSY
19 GND 44 -ACK
20 GND 45 -RST
21 GND 46 -MSG
22 GND 47 -SEL
23 GND 48 -C/D
24 GND 49 -REQ
25 GND 50 -I/O

2-15
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

Table 2-24
SCSI LVD 68-pin Connector

Connector Connector
Contact Contact
Number Signal Names Number Signal Names

1 +DB(12) 35 -DB(12)
2 +DB(13) 36 -DB(13)
3 +DB(14) 37 -DB(14)
4 +DB(15) 38 -DB(15)
5 +DB(P1) 39 -DB(P1)
6 +DB(0) 40 -DB(0)
7 +DB(1) 41 -DB(1)
8 +DB(2) 42 -DB(2)
9 +DB(3) 43 -DB(3)
10 +DB(4) 44 -DB(4)
11 +DB(5) 45 -DB(5)
12 +DB(6) 46 -DB(6)
13 +DB(7) 47 -DB(7)
14 +DB(P) 48 -DB(P)
15 GROUND 49 GROUND
16 DIFFSENS 50 GROUND
17 TERMPWR 51 TERMPWR
18 TERMPWR 52 TERMPWR
19 RESERVED 53 RESERVED
20 GROUND 54 GROUND
21 +ATN 55 -ATN
22 GROUND 56 GROUND
23 +BSY 57 -BSY
24 +ACK 58 -ACK
25 +RST 59 -RST
26 +MSG 60 -MSG
27 +SEL 61 -SEL
28 +C/D 62 -C/D
29 +REQ 63 -REQ
30 +I/O 64 -I/O
31 +DB(8) 65 -DB(8)
32 +DB(9) 66 -DB(9)
33 +DB(10) 67 -DB(10)
34 +DB(11) 68 -DB(11)

SCSI LVD 68-pin

Connector

Refer to Table 2-24 for

the pin definitions.

2-16
 Chapter 2: Installation

Table 2-25
AGP Port Pin Definitions for J8

Pin # B A Pin # B A
1 Spare 12V 34 Vddq3.3 Vddq3.3
2 5.0V Spare 35 AD21 AD22
3 5.0V Reserved* 36 AD19 AD20
4 USB+ USB- 37 GND GND
5 GND GND 38 AD17 AD18
6 INTB# INTA# 39 C/BE2# AD16
7 CLK RST# 40 Vddq3.3 Vddq3.3
8 REQ# GNT# 41 IRDY# Frame#
9 VCC3.3 VCC3.3 42
10 ST0 ST1 43 GND GND
11 ST2 Reserved 44
12 RBF# PIPE# 45 VCC3.3 VCC3.3
13 GND GND 46 DEVSEL# TRDY#
14 Spare Spare 47 Vddq3.3 STOP#
15 SBA0 SBA1 48 PERR# Spare
16 VCC3.3 VCC3.3 49 GND GND
17 SBA2 SBA3 50 SERR# PAR
18 SB_STB Reserved 51 C/BE1# AD15
19 GND GND 52 Vddq3.3 Vddq3.3
20 SBA4 SBA5 53 AD14 AD13
21 SBA6 SBA7 54 AD12 AD11
22 KEY KEY 55 GND GND
23 KEY KEY 56 AD10 AD9
24 KEY KEY 57 AD8 C/BE0#
25 KEY KEY 58 Vddq3.3 Vddq3.3
26 AD31 AD30 59 AD_STB0 Reserved
27 AD29 AD28 60 AD7 AD6
28 VCC3.3 VCC3.3 61 GND GND
29 AD27 AD26 62 AD5 AD4
30 AD25 AD24 63 AD3 AD2
31 GND GND 64 Vddq3.3 Vddq3.3
32 AD_STB1 Reserved 65 AD1 AD0
33 AD23 C/BE3# 66 SMB0 SMB1

AGP Port

There are no jumpers to

configure the AGP port J8.
Refer to Table 2-25 for the
pin definitions.

2-17
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

2-18
 Chapter 3: Troubleshooting

Chapter 3
Troubleshooting

3-1 Troubleshooting Procedures

Use the following procedures and chart to troubleshoot your system. If you
have followed all of the procedures below and still need assistance, refer
to the ‘Technical Support Procedures’ and/or ‘Returning Merchandise for
Service’ section(s) in this chapter.

Before Power On

1. Make sure there is no short circuit between motherboard and

chassis.
2. Disconnect all ribbon/wire cables from the motherboard.
3. Remove all the add-in cards except the video graphics card. (Be
sure the video/graphic card is inserted properly.)
4. Install a CPU, a chassis speaker and power LED to this motherboard.
(Check all the jumper settings as well)
5. Install one bank of memory module.
6. Check power supply voltage monitor 115 V / 230 V switch.

Figure 3-1. Troubleshooting Flowchart

Power On
* See "Before Power On,"
above, before proceding with
these steps.

N Sytem Power
LED on?

Power N
Supply OK? Video Y
Display?

Y N N
System Hold?
Replace Power
Supply Motherboard
Speaker Y Good
Beeps? Check BIOS
Y Setting & Add-
N on Card
Remove
Memory

Speaker
Y Beeps? Number of
Beeps 8
N Video Card
6 Problem
Check CPU &
BIOS Memory
Problem:
Check Memory
Speaker
Y Beeps?

N
Replace
Motherboard

3-1
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

No Power

1. Make sure the default jumper is on and CPU is correctly setup.

2. Turn power switch on and off to test system.
3. If power is still not on, turn off system power to move jumper setting
on JP20 from 2-3 to 1-2.
4. If moving jumper setting has not helped: Clear CMOS.
5. Check power supply voltage monitor. (Check power supply 115 V /
230 V switch)

No Video

Use the following steps for troubleshooting your system configuration.

1. If the power is on but you have no video, remove all the add-in
cards and cables.
2. Check for shorted connections, especially under the motherboard.
3. Check the jumpers settings, clock speed, and voltage settings.
4. Use the speaker to determine if any beep codes exist. Refer to
Appendix A for details about beep codes.

NOTE

If you are a system integrator, VAR or OEM, a POST diagnos-

tics card is recommended for port 80h codes. Refer to
Appendix B.

Memory Error

If you encounter memory error, follow the procedures below.

1. Check to determine if DIM modules are improperly installed.

2. Make sure that different types of DIMMs have not been installed in
different banks (e.g., a mixture of 2MB x 36 and 1 MB x 36 DIMMs in
Banks 0).
3. Determine if different speeds of DIMMs have been installed, and the
BIOS setup is configured for the fastest speed of RAM used. It is
recommended to use the same RAM speed for DIMMs in the system.
4. Check for bad DIM modules or chips.
5. Try to install the minimum memory first (single bank).

3-2
 Chapter 3: Troubleshooting

Losing the System’s Setup Configuration

1. Check the jumper JBT1 setting. Ensure that you are using a high
quality power supply. A poor quality power supply may cause the
system to lose CMOS setup. Refer to Chapter 1 of this manual for
details.
2. If the above step does not fix the Setup Configuration problem,
contact your vendor for repair.

3-2 Technical Support Procedures

1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently

Asked Question' (FAQ) sections in this chapter of the manual or check
our web site FAQ (http:// www.supermicro.com) before contacting
Technical Support.
2. Take note that as a motherboard manufacturer Super Micro does not
sell directly to end-users, so it is best to check with your distributor or
reseller for troubleshooting services. They should know of any pos-
sible problem(s) with the specific system configuration that was sold
to you.
3. BIOS upgrades can be downloaded from the SUPER BBS# (408) 895-
2022, 24 hours a day, using 1200-28800 baud, 8 data bits, 1 stop bit
and no parity. BIOS upgrades can also be downloaded from our web
site at http://www.supermicro.com.
Note: Not all BIOS can be flashed depending on the modifications to
the boot block code.
4. If you still cannot resolve the problem, include the following information
when you e-mail Super Micro for technical support:
• BIOS release date/version
• System board serial number
• Product model name
• Invoice number and date
• System configuration
Due to the volume of e-mails we recieve and the time it takes to repli-
cate problems, a response to your question may not be immediately
available. Please understand that we do not have the resources to
serve every end-user, however we will try our best to help all our
customers.
5. Distributors: For immediate assistance, please have your account
number ready when placing a call to our technical support depart-
ment.

3-3
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

3-3 Frequently Asked Questions

Question: What are the differences between the various memo-

ries that the 440BX motherboard can support?

Answer: The 440BX integrates a main memory DRAM controller that sup-
ports a 64-bit or 72-bit (64 bit memory data plus 8 ECC bits.) DRAM from 8
MB to 512 MB for SDRAM and from 8 MB to 1 GB for EDO or registered
DIMM. The DRAM types supported are either Extended Data Out (EDO),
Synchronous DRAM (SDRAM) or Registered DIM modules. *Note: EDO
DIM Modules are not recommended for running 100 MHz bus speed.

1. Mixing ECC and non-ECC will result in non-ECC operation.

EC/ECC is supported properly in the 440BX, only if all the memory are 72
bit wide. A system with a mixture of 64 and 72-bit wide memory will
disable ECC mode.

2. EDO memory and SDRAM cannot be mixed.

3. Registered SDRAM and unbuffered SDRAM cannot be mixed.

4. Mixing PC/100 DIMM and PC/66 DIMM will result in an unexpected

memory count or system errors.

5. User should populate the DIMM starting with the DIMM socket located
the furthest from the BX chip (U2 on P6DBS/P6DBE/P6SBS, U4 on P6DBU/
P6SBU or U9 on P6SBA).

6. If EDO memory is used, the CPU bus should be set at 66 MHz Bus
speed only.

Question: How do I update my BIOS?

Answer: Update BIOS files are located on our web site at http://
www.supermicro.com. Please check the current BIOS revision and make
sure it is newer than your BIOS before downloading. Select your
motherboard model and download the BIOS file to your computer. Unzip the
BIOS update file and you will find three files: readme.txt (flash instructions),
sm2flash.com (BIOS flash utility), and the BIOS image file (xxxxxx.rom).
Copy these files onto a bootable floppy and reboot your system. It is not
necessary to set BIOS boot block protection jumpers on the motherboard.

3-4
 Chapter 3: Troubleshooting

At the DOS prompt, enter the command "sm2flash." This will start the flash
utility and give you an opportunity to save your current BIOS image. Flash
the boot block and enter the name of the update BIOS image file. NOTE: It
is important to save your current BIOS and rename it "super.rom" in case
you need to recover from a failed BIOS update. Select flash boot block,
then enter the update BIOS image. Select "Y" to start the BIOS flash proce-
dure and do not disturb your system until the flash utility displays that the
procedure is complete. After updating your BIOS, please clear the CMOS
then load Optimal Values in the BIOS.

Question: After flashing the BIOS my system does not have video.
How can I correct this?

Answer: If the system does not have video after flashing your new BIOS,
it indicates the flashing procedure failed. To remedy this, first clear the
CMOS per instructions in this manual and retry BIOS flashing procedure. If
you still do not have video, please use the following BIOS recovery proce-
dure. Turn your system off and place the floppy disk with the saved BIOS
image file (see above FAQ) in drive A. Press and hold "CTRL" and "Home"
at the same time, then turn on power with these keys pressed until your
floppy drive starts reading. Your screen will remain blank until the BIOS
program is done. If system reboots correctly, then recovery is done.

Question: I have memory problems. What is the correct memory

to use and which BIOS setting should I choose?

Answer: The correct memory to use on the SUPER P6DBS/P6DBE/P6DBU/

P6SBU/P6SBS/P6SBA is 168-pin DIMM 3.3v non-buffered SPD (Serial Present
Detection) SDRAM, SDRAM and EDO memory. SPD SDRAM is preferred but
is not necessary. IMPORTANT: Please do not mix memory types; the results
are unpredictable. If your memory count is exactly half of the correct
value, please go to the BIOS in Chipset Setup and set "SDRAM AUTOSIZING
SUPPORT" to Enabled. Change between available options until one setting
correctly displays your memory.

Question: Which Operating System (OS) supports AGP?

Answer: At present Windows 98 and Windows NT 5.0 are the only OS

that will have built-in support for AGP. Some AGP video adapters can run
Windows 95 OSR2.1 with special drivers. Please contact your graphics
adapter vendor for more details.

3-5
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

Question: Do I need the CD that came with your motherboard?

Answer: The supplied compact disc has quite a few drivers and programs
that will greatly enhance your system. We recommend that you review the
CD and install the applications you need. Applications included on the CD
are PCI IDE Bus Master drivers for Windows 95 and Windows NT, 440BX
chipset drivers for Windows 95, and Super Doctor Monitoring software.

Question: How do I install an on-board SCSI device controller for

my P6DBS/P6SBS motherboard.

Answer: First install 3 NT installation disks and then follow the on-screen
instructions to complete the procedure. "Safe mode" is best for this instal-
lation.

Question: Why can't I turn off the power using the momentary
power on/off switch?

Answer: The instant power off function is controlled by the BIOS. When
this feature is enabled in the BIOS, the motherboard will have instant off
capabilities as long as the BIOS has control of the system. When this
feature is disabled or when the BIOS is not in control, such as during
memory count (the first screen that appears when the system is turned on),
the momentary on/off switch must be held for more than four seconds to
shut down. This feature is required to implement ACPI features on the
motherboard.

Question: I see some of my PCI devices sharing IRQs, but the

system seems to be fine, is this correct or not?

Answer: Some PCI Bus Mastering devices can share IRQs without perfor-
mance penalties. These devices are designed to work correctly while shar-
ing IRQs.

Question: When I connect my Ultra II LVD Hard Drive on the JA1

SCSI connection, the drive was not recognized by BIOS or it failed
to boot. Do I need a special cable?

Answer: Yes, for Ultra II LVD Drive, you need a special 68-pin cable with
active termination at the end of the cable, since Ultra II LVD Hard Drive does
not have termination on the drive.

3-6
 Chapter 3: Troubleshooting

3-4 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is

required before any warranty service will be rendered. You can obtain
service by calling your vendor for a Returned Merchandise Authorization
(RMA) number. When returning to the manufacturer, the RMA number
should be prominently displayed on the outside of the shipping carton, and
mailed prepaid or hand-carried. Shipping and handling charges will be ap-
plied for all orders that must be mailed when service is complete.

This warranty only covers normal consumer use and does not cover dam-
ages incurred in shipping or from failure due to the alternation, misuse,
abuse, or improper maintenance of products.

During the warranty period, contact your distributor first for any product
problems.

3-7
SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Manual

3-8
 Chapter 4: AMI BIOS

Chapter 4
AMI BIOS

4-1 Introduction

This chapter describes the AMIBIOS for the Intel 440BX Pentium II 400/350/
333/300/266/233 MHz processors. The AMI ROM BIOS is stored in the
Flash EEPROM and is easily upgraded using a floppy disk-based program.

System BIOS

The BIOS is the basic input output system used in all IBM® PC, XT™, AT ® ,
and PS/2® compatible computers. The WinBIOS is a high-quality example of
a system BIOS.

Configuration Data

AT-compatible systems, also called ISA (Industry Standard Architecture)

must have a place to store system information when the computer is turned
off. The original IBM AT had 64 bytes of non-volatile memory storage in
CMOS RAM. All AT-compatible systems have at least 64 bytes of CMOS
RAM, which is usually part of the Real Time Clock. Many systems have 128
bytes of CMOS RAM.

How Data Is Configured

AMIBIOS provides a Setup utility in ROM that is accessed by pressing <Del>

at the appropriate time during system boot. Setup configures data in CMOS
RAM.

POST Memory Test

Normally, the only visible POST routine is the memory test. The screen that
appears when the system is powered on is shown on the next page.

An AMIBIOS Identification string is displayed at the left bottom corner of the

screen, below the copyright message.

4-1
BIOS User's Manual

American
Mega AMIBIOS (c) 1997 American Megatrends, Inc.
Trends
0404981500 Pentium II Motherboard Made in USA R1.0
SUPER
Checking NVRAM BIOS date code
xxxxx KB OK
BIOS revision code

Hit <DEL> if you want to run SETUP

(C) Super Micro Computer, Inc.,

XX-XXXX-XXXXXX-XXXXXXXX-XXXXXX-XXXX-X

4-2 BIOS Features

• supports Plug and Play V1.0A and DMI 2.1

• supports Intel PCI 2.1 (Peripheral Component Interconnect) local bus

specification

• supports Advanced Power Management (APM) specification v 1.1

• supports xACP2

• supports Flash ROM

AMIBIOS supports the LS120 drive made by Matsushita-Kotobuki Electronics

Industries Ltd. The LS120:

• can be used as a boot device

• is accessible as the next available floppy drive

AMIBIOS supports PC Health Monitoring chips. When a failure occurs in a

monitored activity, AMIBIOS can sound an alarm and display a message.
The PC Health Monitoring chips monitor:

• CPU temperature

• additional temperature sensors

• chassis intrusion detector

4-2
 Chapter 4: AMI BIOS

• five positive voltage inputs

• two negative voltage inputs

• three fan speed monitoring inputs

BIOS Configuration Summary Screen

AMIBIOS displays a screen that looks similar to the following when the
POST routines complete successfully.

AMIBIOS System Configuration (C) 1985-1997 American Megatrends Inc.,

Main Processor : Pentium(tm) II Base Memory Size : 640 KB

Math Processor : Built-In Ext. Memory Size : 64512 KB
Floppy Drive A: : 1.44 MB, 3 1 / 2 Display Type : VGA/EGA
Floppy Drive B: : None Serial Port(s) : 3F8, 2F8
AMI-BIOS Date : 7/15/95 Parallel Port(s) : 378
Processor Clock : 350MHz External Cache : 512 KB

PCI Devices
PCI Onboard PCI Bridge PCI Onboard Bridge Device
PCI Onboard USB Controller PCI Onboard IDE
PCI Onboard SCSI, IRQ 10 PCI Onboard SCSI, IRQ 10
PCI Slot 4 VGA, IRQ 11

*Note: The picture above reflects a board equipt with SCSI, but may be taken as a general example.

AMIBIOS Setup
See the following page for examples of the AMIBIOS Setup screen,
featuring options and settings. Figure 4-1 shows the Standard option
highlighted. To highlight other options, use the arrow keys, or use the
tab key to move to other option boxes. Figure 4-2 shows the settings
for the Standard setup. Settings can be viewed by highlighting a desired
option and pressing <Enter>. Use the arrow keys to choose a setting.
Note: Optimal settings for all options can be set automatically. Go to the
Optimal icon in the default box and press <Enter>. Use the arrow keys
to highlight yes, then press <Enter>.

4-3
BIOS User's Manual

Figure 4-1. Standard Option Highlighted

Figure 4-2. Settings for Standard Option

4-4
 Chapter 5: Running Setup

Chapter 5
Running Setup*

*Optimal and Fail-Safe default settings are bolded in text unless otherwise
noted.

The WinBIOS Setup options described in this section are selected by

choosing the appropriate high-level icon from the Standard Setup screen.
All displayed icons are described in this section, although the screen
display is often all you need to understand how to set the options.

5-1 Setup

5-1-1 Standard Setup

Pri Master
Pri Slave
Sec Master
Sec Slave
Select these options to configure the drive named in the option. Select
Auto Detect IDE to let AMIBIOS automatically configure the drive. A
screen with a list of drive parameters appears. Click on OK to configure
the drive.

Type How to Configure

SCSI Select Type. Select Not Installed on the drive

parameter screen. The SCSI drivers provided by
the SCSI manufacturer should allow you to configure
the SCSI drive.

IDE Select Type. Select Auto to let AMIBIOS determine the

parameters. Click on OK when AMIBIOS displays the
drive parameters. Select LBA Mode. Select On if the
drive has a capacity greater than 540 MB. Select the
Block Mode. Select On to allow block mode data
transfers. Select the 32-bit mode. Select On to allow
32-bit data transfers. Select PIO mode. Select On
to allow AMIBIOS to determine the PIO Mode. It

5-1
BIOS User's Manual

is best to select Auto to allow AMIBIOS to determine

the PIO mode. If you select a PIO mode that is not
supported by the IDE drive, the drive will not work
properly. If you are absolutely certain that you know
the drive's PIO mode, select PIO mode 0-4, as
appropriate

CD Select Type. Select CDROM. Click on OK when

ROM AMIBIOS displays the drive parameters.

Entering Drive Parameters

You can also enter the hard disk drive parameters. The drive parameters
are:

Parameter Description

Type The number for a drive with certain identification parameters.

Cylinders The number of cylinders in the disk drive.

Heads The number of heads.

Write The size of a sector gets progressively smaller as the track

Precompensation diameter diminishes. Yet each sector must still hold 512 bytes.
Write precompensation circuitry on the hard disk compensates for
the physical difference in sector size by boosting the write
current for sectors on inner tracks. This parameter is the track
number where write precompensation begins.

Sectors The number of sectors per track. MFM drives have 17 sectors
per track. RLL drives have 26 sectors per track. ESDI drives
have 34 sectors per track. SCSI and IDE drive may have even
more sectors per track.

Capacity The formatted capacity of the drive is (Number of heads) x

(Number of cylinders) x (Number of sectors per track) x (512
bytes per sector)

5-2
 Chapter 5: Running Setup

Date and Time Configuration

Select the Standard option. Select the Date/Time icon. The current
values for each category are displayed. Enter new values through the
keyboard.

Floppy A
Floppy B
Choose the Floppy Drive A or B icon to specify the floppy drive type.
The settings are Not Installed, 360 KB 5¼ inch, 1.2 MB 5¼ inch, 720 KB
3½ inch, 1.44 MB 3½ inch or 2.88 MB 3½ inch. Note: The Optimal
and Fail-Safe settings for Floppy Drive A are 1.44 MB 3 1/2 inch
and for Floppy Drive B are Not Installed.

5-1-2 Advanced Setup

Quick Boot
The Settings are Disabled or Enabled. Set to Enabled to permit
AMIBIOS to boot quickly when the computer is powered on. This option
replaces the old Above 1 MB Memory Test Advanced Setup option. The
settings are:

Setting Description

Disabled AMIBIOS tests all system memory. AMIBIOS waits

up to 40 seconds for a READY signal from the IDE
hard disk drive. AMIBIOS waits for .5 seconds after
sending a RESET signal to the IDE drive to allow the
IDE drive time to get ready again. AMIBIOS checks
for a <Del> key press and runs AMIBIOS Setup if the
key has been pressed.

Enabled AMIBIOS does not test system memory above 1 MB.

AMIBIOS does not wait up to 40 seconds for a READY

signal from the IDE hard disk drive. If a READY signal
is not received immediately from the IDE drive, AMIBIOS
does not configure that drive. AMIBIOS does not wait
for .5 seconds after sending a RESET signal to the IDE
drive to allow the IDE drive time to get ready again. In
Enabled, keyboard will be bypassed.

Note: You cannot run AMIBIOS Setup at system boot, because

there is no delay for the Hit <Del> to run Setup message .

5-3
BIOS User's Manual

Pri Master ARMD Emulated as

Pri Slave ARMD Emulated as
Sec Master ARMD Emulated as
Sec Slave ARMD Emulated as
Options for Pri Master ARMD Emulated as, Pri Slave ARMD Emulated as,
Sec Master ARMD Emulated as and Sec Slave ARMD Emulated as are
Auto, Floppy or Hard disk.

1st Boot Device

2nd Boot Device
3rd Boot Device
The options for 1st Boot Device are Disabled, 1st IDE-HDD, 2nd IDE-
HDD, 3rd IDE-HDD, 4th IDE-HDD, Floppy, ARMD-FDD, ARMD-HDD,
ATAPI CD ROM, SCSI, Network or I20. The options for 2nd Boot Device
are Disabled, 1st IDE-HDD, 2nd IDE-HDD, 3rd IDE-HDD, 4th IDE-HDD,
Floppy, ARMD-FDD, ARMD-HDD or ATAPI CD ROM. The options for
3rd Boot Device are Disabled, 1st IDE-HDD, 2nd IDE-HDD, 3rd IDE-
HDD, 4th IDE-HDD, Floppy, ARMD-FDD, ARMD-HDD or ATAPI CD
ROM.

1st IDE-HDD, 2nd IDE-HDD, 3rd IDE-HDD and 4th IDE-HDD are the four
hard disks that can be installed by the BIOS. 1st IDE-HDD is the first
hard disk installed by the BIOS, 2nd IDE-HDD is the second hard disk, and
so on. For example, if the system has a hard disk connected to Primary
Slave and another hard disk to Secondary Master, then 1st IDE-HDD will
be referred to as the hard disk connected to Primary Slave and 2nd IDE-
HDD will be referred to as the hard disk connected to the Secondary
Master. 3rd IDE-HDD and 4th IDE-HDD are not present. Note that the
order of the initialization of the devices connected to the primary and
secondary channels are Primary Master first, Primary Slave second,
Secondary Master third, and Secondary Slave fourth.

The BIOS will attempt to read the boot record from 1st, 2nd, 3rd and 4th
boot device in the selected order until it is successful in reading the
booting record. The BIOS will not attempt to boot from any device which
is not selected as the boot device.

Try Other Boot Device

This option controls the action of the BIOS if all the selected boot devices
failed to boot. The settings for this option are Yes or No. If Yes is
selected and all the selected boot devices failed to boot, the BIOS will try
to boot from the other boot devices (in a predefined sequence) which are
present but not selected as boot devices in the setup (and hence not yet

5-4
 Chapter 5: Running Setup

been tried for booting). If selected as No and all selected boot devices
failed to boot, the BIOS will try not to boot from the other boot devices
which may be present but not selected as boot devices in setup.

Initial Display Mode

This option determines the display screen with which the POST is going
to start the display. The settings for this option are BIOS or Silent. If
selected as BIOS, the POST will start with the normal sign-on message
screen. If Silent is selected, the POST will start with the silent screen.

Display Mode at Add-on ROM Init

This option determines the display mode during add-on ROM (except
Video add-on ROM) initialization. The settings for this option are Force
BIOS or Keep Current. If selected as Force BIOS, the POST will force
the display to be changed to BIOS mode before giving control to any add-
on ROM. If no add-on ROM is found, then the current display mode will
remain unchanged even if this setup question is selected as Force BIOS.
If selected as Keep Current, then the current display mode will remain
unchanged.

Floppy Access Control

The settings for this option are Read-Write or Read-Only.

Hard Disk Access Control

The settings for this option are Read-Write or Read-Only.

S.M.A.R.T. for Hard Disks

S.M.A.R.T. (Self-Monitoring, Analysis and Reporting Technology) is a
technology developed to manage the reliability of the hard disk by
predicting future device failures. The hard disk needs to be S.M.A.R.T.
capable. The settings for this option are Disabled or Enabled. *Note:
S.M.A.R.T. cannot predict all future device failures. S.M.A.R.T.
should be used as a warning tool, not as a tool to predict the
device reliability.

Boot Up Num-Lock
Settings for this option are On or Off. When this option is set to On, the
BIOS turns off the Num Lock key when the system is powered on. This
will enable the end user to use the arrow keys on both the numeric
keypad and the keyboard.

5-5
BIOS User's Manual

PS/2 Mouse Support

Settings for this option are Enabled or Disabled. When this option is set
to Enabled, AMIBIOS supports a PS/2-type mouse.

Primary Display
This option specifies the type of display adapter card installed in the
system. The settings are Absent, VGA/EGA, CGA40x25, CGA80x25 or
Mono.

Password Check
This option enables the password check option every time the system
boots or the end user runs WinBIOS Setup. If Always is chosen, a user
password prompt appears every time the computer is turned on. If
Setup is chosen, the password prompt appears if WinBIOS Setup is
executed.

Boot to OS/2
If DRAM size is over 64 MB, set this option to Yes to permit AMIBIOS to
run with IBM OS/2. The settings are No or Yes.

CPU Microcode Updation

Set this option to Enabled to permit the CPU to be updated on line. The
settings for this option are Enabled or Disabled.

Internal Cache
This option is for enabling or disabling the internal cache memory. The
settings for this option are Disabled or WriteBack.

System BIOS Cacheable

When set to Enabled, the contents of the F0000h system memory
segment can be read from or written to cache memory. The contents of
this memory segment are always copied from the BIOS ROM to system
RAM for faster execution. The settings are Enabled or Disabled. Note:
The Optimal default setting is Enabled and the Fail-Safe default
setting is Disabled. Set this option to Enabled to permit the
contents of F0000h RAM memory segment to be written to and
read from cache memory.

CPU ECC
The settings for this option are Enabled or Disabled. This option
enables Pentium II L2 cache ECC function.

5-6
 Chapter 5: Running Setup

MPS Revision
The settings for this option are 1.1 or 1.4.

C000, 16K Shadow

C400, 16K Shadow
These options specify how the 32 KB of video ROM at C0000h is treated.
The settings are: Disabled, Enabled or Cached. When set to Disabled,
the contents of the video ROM are not copied to RAM. When set to
Enabled, the contents of the video ROM area from C0000h-C7FFFh are
copied (shadowed) from ROM to RAM for faster execution. When set to
Cached, the contents of the video ROM area from C0000h-C7FFFh are
copied from ROM to RAM, and can be written to or read from cache
memory.

C800, 16K Shadow

CC00, 16K Shadow
D000, 16K Shadow
D400, 16K Shadow
D800, 16K Shadow
DC00, 16K Shadow
These options enable shadowing of the contents of the ROM area named
in the option. The ROM area not used by ISA adapter cards is allocated to
PCI adapter cards. The settings are: Disabled, Enabled or Cached.
When set to Disabled, the contents of the video ROM are not copied to
RAM. When set to Enabled, the contents of the video ROM area from
C0000h-C7FFFh are copied (shadowed) from ROM to RAM for faster
execution. W hen set to Cached, the contents of the video ROM area
from C0000h-C7FFFh are copied from ROM to RAM and can be written to
or read from cache memory.

5-1-3 Chipset Setup

USB Function
The settings for this option are Enabled or Disabled. Set this option to
Enabled to enable the USB (Universal Serial Bus) functions.

USB KB/Mouse Legacy Support

The settings for this option are Keyboard, Auto, Keyboard+Mouse or
Disabled. Set this option to Enabled to enable the USB keyboard and
mouse.

5-7
BIOS User's Manual

SERR# (System Error)

The settings for this option are Enabled or Disabled. Set to Enabled to
enable the SERR# signal on the bus. BX asserts this signal to indicate a
system error condition. SERR# is asserted under the following condi-
tions:
- In an ECC configuration, the 82443BX asserts SERR#, for single bit (correctable) ECC errors or multiple

bit (non-correctable) ECC errors if SERR# signaling is enabled via the ERRCMD control register. Any

ECC errors received during initialization should be ignored.

- The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated PCI

cycle

- The 82443BX can also assert SERR# when a PCI parity error occurs during the address or data phase

- The 82443BX can assert SERR# when it detects a PCI address or data parity error on AGP

- The 82443BX can assert SERR# upon detection of access to an invalid entry in the Graphics Aperature

Translation Table

- The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture

and outside of main DRAM range (i.e. in the 640k - 1M range or above TOM)

- The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture.

- The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated AGP

cycle

PERR#
This option signals data parity errors of the PCI bus. The settings are
Enabled or Disabled. Set to Enabled to enable the PERR# signal.

WSC# Handshake (Write Snoop Complete)

This signal is asserted active to indicate that all the snoop activity on the
CPU bus on the behalf of the last PCI-DRAM write transaction is complete
and that it is safe to send the APIC interrupt message. The settings for
this option are Enabled or Disabled. Set to Enabled to enable hand-
shaking for the WSC# signal.

USWC Write Post

The settings for this option are Enabled or Disabled. This option sets
the status of USWC (Uncacheable, Speculative, Write-Combining) posted
writes and is used to combine several partial writes to the frame buffer
into a single write in order to reduce the data bus traffic. Set to Enabled
to enable USWC posted writes to I/O. Set to Disabled to disable USWC
posted writes to I/O.

5-8
 Chapter 5: Running Setup

BX/GX Master Latency Timer (CLKs)

This option specifies the master latency timings (in PCI clocks) for
devices in the computer. It defines the number of PCI clocks a PCI master
can own on the bus after PCI central arbiter removes the grant signal.
The settings are Disabled, 32, 64, 96, 128, 160, 192 or 224.

Multi-Trans Timer (Clks)

This option specifies the multi-trans latency timings (in PCI clocks) for
devices in the computer. It reduces overhead switching between
different masters. The settings are Disabled, 32, 64, 96, 128, 160, 192
or 224.

PCI1 to PCI0 Access

PCI1 refers to AGP in BX and LX chipsets. PCI0 is the normal PCI bus.
Note: Normally AGP master should not access to a PCI target.
The settings for this option are Enabled or Disabled. Set to Enabled to
enable access between two different PCI buses (PCI1 and PCI0).

Memory Autosizing Support

The dynamic detection and sizing of SDRAM and EDO is performed by the
BIOS in a system populated with memory which has no SPD information.
When set to Enable, memory does not have the SPD information. The
settings for this option are Auto or Enable.

DRAM Integrity Mode

The settings for this option are None, EC or ECC Hardware. Note: For
ECC memory only. See the table below to set the type of system
memory checking. (Note: New BIOS versions automatically detect
setting and do not need to be set by user.)

Setting Description

None No error checking or error reporting is done.

EC Multibit errors are detected and reported as parity

errors. Single-bit errors are corrected by the chipset.
Corrected bits of data from memory are not written
back to DRAM system memory.

ECC Multibit errors are detected and reported as parity

Hardware errors. Single-bit errors are corrected by the
chipset and are written back to DRAM system memory.
If a soft (correctable) error occurs, writing the fixed

5-9
BIOS User's Manual

data back to DRAM system memory will resolve the

problem. Most DRAM errors are soft errors. If a hard
(uncorrectable) error occurs, writing the fixed data
back to DRAM system memory does not solve the
problem. In this case, the second time the error
occurs in the same location, a Parity Error is reported,
indicating an uncorrectable error. If ECC is selected,
AMIBIOS automatically enables the System
Management Interface (SMI). If you do not want to
enable power management, set the Power
Management/APM option to Disabled and set all
Power Management Setup timeout options to
Disabled. To enable power management, set Power
Management/APM to Enabled and set the power
management timeout options as desired.

DRAM Refresh Rate

This option specifies the interval between Refresh signals to DRAM
system memory. The settings for this option are 15.6 us (micro-sec-
onds), 31.2 us, 62.4 us, 124.8 us or 249.6 us.

Memory Hole
This option specifies the location of an area of memory that cannot be
addressed on the ISA bus. The settings are Disabled, 15 MB-16 MB, or
512 KB-640 KB.

SDRAM CAS# Latency

This option regulates the column address strobe. The settings are 2
SCLKs, 3 SCLKs or Auto.

SDRAM RAS# to CAS# Delay

This option specifies the length of the delay inserted between the RAS
and CAS signals of the DRAM system memory access cycle if SDRAM is
installed. The settings are Auto (AMIBIOS automatically determines the
optimal delay), 2 SCLKs or 3 SCLKs. Note: The Optimal default
setting is Auto and the Fail-Safe default setting is 3 SCLKs.

SDRAM RAS# Precharge

This option specifies the length of the RAS precharge part of the DRAM
system memory access cycle when Synchronous DRAM system memory
is installed in the computer. The settings are Auto (AMIBIOS automatically

5-10
 Chapter 5: Running Setup

determines the optimal delay), 2 SCLKs or 3 SCLKs. Note: The Optimal

default setting is Auto and the Fail-Safe default setting is 3
SCLKs.

Power Down SDRAM

BX supports SDRAM power down mode to minimize SDRAM power
usage. The settings for this option are Enabled or Disabled. The
Enabled setting enables the SDRAM Power Down feature.

ACPI Control Register

The settings for this option are Enabled or Disabled. Set this option to
Enabled to enable the ACPI (Advanced Configuration and Power Inter-
face) control register.

Gated Clock
Signal GCLKEN enables internal dynamic clock gating in the 82443BX
when a AGPset "IDLE" state occurs. This happens when the 82443BX
detects an idle state on all its buses. The settings for this option are
Enabled or Disabled. The Enabled setting enables the gated clock.

Graphics Aperture Size

This option specifies the amount of system memory that can be used by
the Accelerated Graphics Port (AGP). The settings are 4 MB, 8 MB, 16
MB, 32 MB, 64 MB, 128 MB, or 256 MB.

Search for MDA (Monochrome Adapter) Range (B0000h-B7FFFh)

Resources
Legacy support requires the ability to have a second graphics controller
(monochrome) in the system. In an AGP system, accesses in the normal
VGA range are forwarded to the AGP bus. Since the monochrome
adapter may be on the PCI (or ISA) bus, the 82443BX must decode
cycles in the MDA range and forward them to PCI. The settings for this
option are Yes or No. Set this option to Yes to let AMIBIOS search for
MDA resources.

AGP Multi-Trans Timer (AGP Clks)

This option sets the AGP multi-trans timer. The settings are in units of
AGP clocks: 32, 64, 96, 128, 160, 192, or 224.

AGP Low-Priority Timer

This option controls the minimum tenure on the AGP for low priority data
transaction for both read and write. The settings are Disabled, 32, 64,
96, 128, 160, 192 or 224.

5-11
BIOS User's Manual

AGP SERR (Advanced Graphic Port System Error)

BX asserts this signal to indicate a AGP system error condition. The
settings for this option are Enabled or Disabled. Set to Enabled to
enable the AGP SERR# signal.

AGP Parity Error Response

The settings for this option are Enabled or Disabled. Set to Enabled to
enable the AGP (Accelerated Graphics Port) to respond to parity errors.

8bit I/O Recovery Time

This option specifies the length of a delay inserted between consecutive
8-bit I/O operations. The settings are Disabled, 1 SYSCLK, 2 SYSCLKs,
3 SYSCLKs, 4 SYSCLKs, 5 SYSCLKs, 6 SYSCLKs, 7 SYSCLKs or 8
SYSCLKs.

16bit I/O Recovery Time

This option specifies the length of a delay inserted between consecutive
16-bit I/O operations. The settings are Disabled, 1 SYSCLK, 2
SYSCLKs, 3 SYSCLKs, 4 SYSCLKs, 5 SYSCLKs, 6 SYSCLKs, 7
SYSCLKs or 8 SYSCLKs.

PIIX4 SERR#
This signal is asserted to indicate a PIIX4 System Error condition. The
settings for this option are Enabled or Disabled. The Enabled option
enables the SERR# signal for the Intel PIIX4 chip.

USB Passive Release

BX releases USB bus when it is idle to maximize the USB bus usage.
The settings for this option are Enabled or Disabled. Set this option to
Enabled to enable passive release for USB.

PIIX4 Passive Release

This option functions similarly to USB Passive Release. The settings for
this option are Enabled or Disabled. Set to Enabled to enable passive
release for the Intel PIIX4 chip.

PIIX4 Delayed Transaction

BX is capable of PIIX4 transaction to improve PIIX4 interrupt efficiency.
The settings for this option are Enabled or Disabled. Set this option to
Enabled to enable delayed transactions for the Intel PIIX4 chip.

5-12
 Chapter 5: Running Setup

Type F DMA Buffer Control1

Type F DMA Buffer Control2
These options specify the DMA channel where Type F buffer control is
implemented. The settings are Disabled, Channel-0, Channel-1, Chan-
nel-2, Channel-3, Channel-4, Channel-5, Channel-6 or Channel-7.

DMA0 Type
DMA1 Type
DMA2 Type
DMA3 Type
DMA5 Type
DMA6 Type
DMA7 Type
These options specify the bus that the specified DMA channel can be
used on. The settings are PC/PCI, Distributed, or Normal ISA.

Memory Buffer Strength

The settings for this option are Strong or Auto.

Manufacturer's Setting
Note: The user should always set this option to mode 0. All other
modes are for factory testing only.

5-1-4 Power Management

Power Management
The settings for this feature are: APM, ACPI or Disabled. Set to APM to
enable the power conservation feature specified by Intel and Microsoft
INT 15h Advance Power Management BIOS functions. Set to ACPI if your
operating system supports Microsoft's Advanced Configuration and Power
Interface (ACPI) standard.

Power Button Function

This option specifies how the power button mounted externally on the
computer chassis is used. The settings are: Suspend or On/Off. When
set to On/Off, pushing the power button turns the computer on or off.
When set to Suspend, pushing the power button places the computer in
Suspend mode or Full On power mode.

Green PC Monitor Power State

This option specifies the power state that the green PC-compliant video
monitor enters when AMIBIOS places it in a power savings state after the

5-13
BIOS User's Manual

specified period of display inactivity has expired. The settings are

Standby, Suspend or Off. Note: The Optimal default setting for this
option is Suspend and the Fail-Safe setting is Standby.

Video Power Down Mode

This option specifies the power conserving state that the VGA video
subsystem enters after the specified period of display inactivity has
expired. The settings are Disabled, Standby, or Suspend. Note: The
Optimal default setting for this option is Suspend and the Fail-
Safe default setting is Disabled.

Hard Disk Power Down Mode

This option specifies the power conserving state that the hard disk drive
enters after the specified period of hard drive inactivity has expired. The
settings are Disabled, Standby, or Suspend. Note: The Optimal
default setting for this option is Suspend and the Fail-Safe
default setting is Disabled.

Hard Disk Timeout (Minutes)

This option specifies the length of a period of hard disk drive inactivity.
W hen this length of time expires, the computer enters power-conserving
state specified in the Hard Disk Power Down Mode option. The settings
are Disabled and 1 Min through 15 Min in 1 minute intervals.

Power Saving Type

The settings for this option are Sleep, Stop Clock or Deep Sleep.

Standby/Suspend Timer Unit

This allows you to set the standby timeout and suspend timeout timer unit.
The settings are 32 secs, 4 msecs, 4 min or 4 secs.

Standby Timeout
This option specifies the length of a period of system inactivity while in
full power on state. When this length of time expires, the computer
enters standby power state. The settings are Disabled and 4 Min
through 508 Min in 4 minute intervals.

Suspend Timeout (Minutes)

This option specifies the length of a period of system inactivity while in
standby state. When this length of time expires, the computer enters
suspend power state. The settings are Disabled and 4 Min through 508
Min in 4 minute intervals.

5-14
 Chapter 5: Running Setup

Slow Clock Ratio

The value of the slow clock ratio indicates the percentage of time the
STPCLK# signal is asserted while in the thermal throttle mode. The
settings are Disabled, 0-12.5%, 12.5-25%, 25-37.5%, 37.5-50%, 50-
62.5%, 62.5-75%, or 75-87.5%.

Display Activity
This option specifies if AMIBIOS is to monitor display activity for power
conservation purposes. When this option is set to Monitor and there is
no display activity for the length of time specified in the Standby Timeout
(Minute) option, the computer enters a power savings state. The settings
are Monitor or Ignore.

Device 6 (Serial port 1)

Device 7 (Serial port 2)
Device 8 (Parallel port)
Device 5 (Floppy disk)
Device 0 (Primary Master IDE)
Device 1 (Primary Slave IDE)
Device 2 (Secondary Master IDE)
Device 3 (Secondary Slave IDE)
When set to Monitor, these options enable event monitoring on the
specified hardware interrupt request line. If set to Monitor and the
computer is in a power saving state, AMIBIOS watches for activity on the
specifies IRQ line. The computer enters the Full On state if any activity
occurs. AMIBIOS reloads the Standby and Suspend timeout timers if
activity occurs on the specified IRQ line. Note: The Optimal default
setting for each option is Ignore with the exception of Devices 0
(Primary Master IDE) and 6 (Serial Port 1) which should be set to
Monitor. The Fail-Safe default for each option is Monitor.

LAN Wake-Up
RTC Wake-UP
Options for LAN Wake-Up and RTC Wake-Up are Disabled or Enabled.
When enabled, the Hour and Minute functions become available.

5-1-5 PCI/PnP Setup

Plug and Play-Aware OS

The settings for this option are No or Yes. Set this option to Yes if the
operating system in the computer is aware of and follows the Plug and
Play specification. AMIBIOS only detects and enables PnP ISA adapter

5-15
BIOS User's Manual

cards that are required for system boot. Currently, only Windows 95 is
PnP-Aware. Set this option to No if the operating system (such as DOS,
OS/2, Windows 3.x) does not use PnP. You must set this option cor-
rectly. Otherwise, PnP-aware adapter cards installed in the computer will
not be configured properly.

PCI Latency Timer (PCI Clocks)

This option specifies the latency timings in PCI clocks for all PCI devices.
The settings are 32, 64, 96, 128, 160, 192, 224, or 248.

PCI VGA Palette Snoop

The settings for this option are Disabled or Enabled. W hen set to
Enabled, multiple VGA devices operating on different buses can handle
data from the CPU on each set of palette registers on every video device.
Bit 5 of the command register in the PCI device configuration space is the
VGA Palette Snoop bit (0 is disabled). For example: if there are two
VGA devices in the computer (one PCI and one ISA) and this option is
disabled, data read and written by the CPU is only directed to the PCI
VGA device's palette registers. If enabled, data read and written by the
CPU is directed to both the PCI VGA device's palette registers and the
ISA VGA palette registers. This will permit the palette registers of both
devices to be identical. This option must be set to Enabled if any ISA
adapter card installed in the system requires VGA palette snooping.

PCI IDE Busmaster

The settings for this option are Disabled or Enabled. Set to Enabled to
specify the IDE Controller on the PCI bus has bus mastering capabilities.
Under Windows 95, you should set this option to Disabled and install the
Bus Mastering driver.

Offboard PCI IDE Card

This option specifies if an offboard PCI IDE controller adapter card is
installed in the computer. The PCI expansion slot on the motherboard
where the offboard PCI IDE controller is installed must be specified. If an
offboard PCI IDE controller is used, the onboard IDE controller is automati-
cally disabled. The settings are Auto (AMIBIOS automatically determines
where the offboard PCI IDE controller adapter card is installed), Slot 1,
Slot 2, Slot 3, Slot 4, Slot 5 or Slot 6.

5-16
 Chapter 5: Running Setup

This option forces IRQ14 and IRQ15 to a PCI slot on the PCI local bus.
This is necessary to support non-compliant ISA IDE controller adapter
cards. If an offboard PCI IDE controller adapter card is installed in the
computer, you must also set the Offboard PCI IDE Primary IRQ and
Offboard PCI IDE Secondary IRQ options.

Offboard PCI IDE Primary IRQ

Offboard PCI IDE Secondary IRQ
These options specify the PCI interrupt used by the primary (or second-
ary) IDE channel on the offboard PCI IDE controller. The settings are
Disabled, Hardwired, INTA, INTB, INTC, or INTD.

PCI Slot1 IRQ Priority

PCI Slot2 IRQ Priority
PCI Slot3 IRQ Priority
PCI Slot4 IRQ Priority
These options specify the IRQ priority for PCI devices installed in the PCI
expansion slots. The settings are Auto, (IRQ) 3, 4, 5, 7, 9, 10, or 11, in
priority order.

DMA Channel 0
DMA Channel 1
DMA Channel 3
DMA Channel 5
DMA Channel 6
DMA Channel 7
These DMA channels control the data transfers between the I/O devices
and the system memory. The chipset allows the BIOS to choose which
channels to do the job. The settings are PnP or ISA/EISA.

IRQ3
IRQ4
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
These options specify which bus the specified IRQ line is used on and
allow you to reserve IRQs for legacy ISA adapter cards. If more IRQs

5-17
BIOS User's Manual

must be removed from the pool, the end user can use these options to
reserve the IRQ by assigning an ISA/EISA setting to it. Onboard I/O is
configured by AMIBIOS. All IRQs used by onboard I/O are configured as
PCI/PnP.

IRQ14 and 15 will not be available if the onboard PCI IDE is enabled. If all
IRQs are set to ISA/EISA and IRQ14 and 15 are allocated to the onboard
PCI IDE, IRQ 9 will still be available for PCI and PnP devices. This is
because at least one IRQ must be available for PCI and PnP devices. The
settings are PCI/PnP or ISA/EISA.

Reserved Memory Size

This option specifies the size of the memory area reserved for legacy
ISA adapter cards. The settings are Disabled, 16K, 32K or 64K.

Reserved Memory Address

This option specifies the beginning address (in hex) of the reserved
memory area. The specified ROM memory area is reserved for use by
legacy ISA adapter cards. The settings are C0000, C4000, C8000,
CC000, D0000, D4000, D8000 or DC000.

Default Primary Video

This feature supports multiple displays. The settings are AGP or PCI.

5-1-6 Peripheral Setup

On-board SCSI
The settings for this option are Enabled or Disabled. When set to
Enable this option enables the Adaptec 7895 BIOS on the P6DBS/P6SBS
motherboards or the Adaptec 7890 on the P6DBU/P6SBU motherboards.

Remote Power On
Microsoft's Memphis OS supports this feature which can wake-up the
system from SoftOff state through devices (such as an external modem)
that are connected to COM1 or COM2. The settings are Disabled or
Enabled.

CPU Current Temperature

The current CPU temperature is displayed in this option.

5-18
 Chapter 5: Running Setup

CPU Overheat Warning

The settings for this option are Enabled or Disabled. When set to
Enabled this option allows the user to set an overheat warning tempera-
ture.

CPU Overheat Warning Temperature

Use this option to set the CPU overheat warning temperature. The
settings are 25 °C through 75 °C in 1 °C intervals. Note: The Optimal
and Fail-Safe default settings are 55 °C.

H/W Monitor In0 (CPU 1)

H/W Monitor In1 (CPU 2)
H/W Monitor In2 (+3.3V)
H/W Monitor In3 (+5V)
H/W Monitor In4 (+12V)
H/W Monitor In5 (-12V)
H/W Monitor In6 (-5V)
CPU1 Fan
CPU2 Fan
Thermal Control Fan
The above features are for PC Health Monitoring. The motherboards with
W83781D have seven on-board voltage monitors for the CPU core, CPU I/
O, +3.3V, +5V, -5V, +12V, and -12V, and three fan status monitors.

On-Board FDC
This option enables the FDC (Floppy Drive Controller) on the motherboard.
The settings are Auto (AMIBIOS automatically determines if the floppy
controller should be enabled), Disabled, or Enabled.

On-Board Serial Port 1

This option specifies the base I/O port address of serial port 1. The
settings are Auto (AMIBIOS automatically determines the correct base I/O
port address), Disabled, 3F8h/COM1, 2F8h/COM2, 3E8h/COM3 or 2E8h/
COM4.

On-Board Serial Port 2

This option specifies the base I/O port address of serial port 2. The
settings are Auto (AMIBIOS automatically determines the correct base I/O
port address), Disabled, 3F8h/COM1, 2F8h/COM2, 3E8h/COM3 or 2E8h/
COM4.

5-19
BIOS User's Manual

Serial Port 2 Mode

The settings for this option are Normal, IrDA or ASK IR. When set to
IrDA, the IR Duplex Mode becomes available and can be set to either Half
or Full. When set to ASK IR, the IrDA Protocol becomes available and
can be set to 1.6 us or 3/16.

On-Board Parallel Port

This option specifies the base I/O port address of the parallel port on the
motherboard. The settings are Auto (AMIBIOS automatically determines
the correct base I/O port address), Disabled, 378, 278 or 3BC.

Parallel Port Mode

This option specifies the parallel port mode. The settings are Normal, Bi-
Dir, EPP or ECP. When set to Normal, the normal parallel port mode is
used. Use Bi-Dir to support bidirectional transfers. Use EPP (Enhanced
Parallel Port) to provide asymmetric bidirectional data transfer driven by
the host device. Use ECP (Extended Capabilities Port) to achieve data
transfer rates of up to 2.5 Mbps. ECP uses the DMA protocol and
provides symmetric bidirectional communication. Note: The Optimal
default setting for this option is ECP and the Fail-Safe setting is
Normal.

EPP Version
The settings are 1.7 or 1.9. Note: The Optimal and Fail-Safe default
settings are N/A.

Parallel Port IRQ

This option specifies the IRQ to be used by the parallel port. The settings
are Auto, 5 or 7.

Parallel Port DMA Channel

This option is only available if the setting of the parallel port mode option
is ECP. The settings are 0, 1, 2, 3, 5, 6 or 7. Note: This option is N/
A.

On-Board IDE
This option specifies the onboard IDE controller channels to be used. The
settings are Disabled, Primary, Secondary or Both.

5-20
 Chapter 5: Running Setup

5-2 Security Setup

5-2-1 Supervisor
User

The system can be configured so that all users must enter a password
every time the system boots or when the W INBIOS setup is executed.
You can set either a Supervisor password or a User password. If you
do not want to use a password, just press <Enter> when the password
prompt appears.

The password check option is enabled in the Advanced Setup by

choosing either Always or Setup. The password is stored in CMOS RAM.
You can enter a password by typing the password on the keyboard,
selecting each letter via the mouse, or selecting each letter via the pen
stylus. Pen access must be customized for each specific hardware
platform.

When you select Supervisor or User, AMIBIOS prompts for a password.

You must set the Supervisor password before you can set the User
password. Enter a 1-6 character password. The password does not
appear on the screen when typed. Retype the new password as
prompted and press <Enter>. Make sure you write it down. If you forget
it, you must drain CMOS RAM and reconfigure.

5-3 Utility Setup

5-3-1 Anti-Virus

When this icon is selected, AMIBIOS issues a warning when any program
(or virus) issues a disk format command or attempts to write to the boot
sector of the hard disk drive. The settings are Enabled or Disabled.

5-3-2 Language

Note: The Optimal and Fail-Safe default settings for this option
are English.

5-21
BIOS User's Manual

5-4 Default Setting

Every option in W inBIOS Setup contains two default settings: a Fail-Safe

default, and an Optimal default.

5-4-1 Optimal Default

The Optimal default settings provide optimum performance settings for all
devices and system features.

5-4-2 Fail-Safe Default

The Fail-Safe default settings consist of the safest set of parameters.

Use them if the system is behaving erratically. They should always work
but do not provide optimal system performance characteristics.

5-22
 Appendix A: BIOS Error Beep Codes

Appendix A
BIOS Error Beep Codes & Messages

During the POST (Power-On Self-Test) routines, which are performed

each time the system is powered on, errors may occur.

Non-fatal errors are those which, in most cases, allow the system to
continue the boot-up process. The error messages normally appear on
the screen.

Fatal errors are those which will not allow the system to continue the
boot-up procedure. If a fatal error occurs, you should consult with your
system manufacturer for possible repairs.

These fatal errors are usually communicated through a series of audible

beeps. The numbers on the fatal error list, on the following page,
correspond to the number of beeps for the corresponding error. All
errors listed, with the exception of #8, are fatal errors.
BIOS User’s Manual

Beeps Error message Description

1 Refresh Failure The memory refresh circuitry on the

motherboard is faulty.

2 Parity Error A parity error was detected in the base

memory (the first 64 KB block) of the
system.

3 Base 64 KB Memory Failure A memory failure occurred within the

first 64 KB of memory.

4 Timer Not Operational A memory failure was detected in the

first 64 KB of memory, or Timer 1 is
not functioning.

5 Processor Error The CPU on the system board

generated an error.

6 8042 - Gate A20 Failure The keyboard controller (8042) contains

the Gate A20 switch which allows the
CPU to operate in virtual mode. This
error means that the BIOS cannot
switch the CPU into protected mode.

7 Processor Exception The CPU on the motherboard generated

Interrupt Error an exception interrupt.

8 Display Memory Read/Write The system video adapter is either

Error missing or its memory is faulty.
Please Note: This is not a fatal error.

9 ROM Checksum Error The ROM checksum value does not

match the value encoded in the BIOS.

10 CMOS Shutdown Register The shutdown register for CMOS

Read/Write Error memory has failed.

Refer to the table on page A-3 for solutions to the error beep codes.

A-2
 Appendix A: BIOS Error Beep Codes

If it beeps... then ...

1, 2, 3 times reseat the DIMM memory. If the

system still beeps, replace the memory.

6 times reseat the keyboard controller chip. If it

still beeps, replace the keyboard
controller. If it still beeps, try a
different keyboard, or replace
the keyboard fuse, if the keyboard has one.

8 times there is a memory error on the

video adapter. Replace the video
adapter, or the RAM on the video
adapter.

9 times the BIOS ROM chip is bad.

The system probably needs a
new BIOS ROM chip.

4, 5, 7, the motherboard must be replaced.

or 10 times

A-3
BIOS User’s Manual

Error Message Information

8042 Gate -- A20 Gate A20 on the keyboard controller (8042)

Error is not working. Replace the 8042.

Address Line Short! Error in the address decoding circuitry on

the motherboard.

C: Drive Error Hard disk drive C: does not respond. Run

the Hard Disk Utility to correct this problem.
Also, check the C: hard disk type in Standard
Setup to make sure that the hard disk type is
correct.

C: Drive Failure Hard disk drive C: does not respond.

Replace the hard disk drive.

Cache Memory Bad Cache memory is defective. Replace it. Do

Not Enable Cache!

CH-2 Timer Error Most ISA computers include two times.

There is an error in time 2.

CMOS Battery State Low CMOS RAM is powered by a battery. The

battery power is low. Replace the battery.

CMOS Checksum Failure After CMOS RAM values are saved, a

checksum value is generated for error
checking. The previous value is different from
the current value. Run WINBIOS Setup or
AMIBIOS Setup.

CMOS System Option The values stored in CMOS RAM are either
Not Set corrupt or nonexistent. Run WINBIOS
Setup or AMIBIOS Setup.

CMOS Display Type The video type in CMOS RAM does not
Mismatch match the type detected by the BIOS. Run
WINBIOS Setup or AMIBIOS Setup.

CMOS Memory Size The amount of memory on the motherboard is

Mismatch different than the amount in CMOS RAM.
Run WINBIOS Setup or AMIBIOS
Setup.

A-4
 Appendix A: BIOS Error Beep Codes

Error Message Information

CMOS Time and Run Standard Setup to set the date and time
Date Not Set in CMOS RAM.

D: Drive Error Hard disk drive D: does not respond. Run

the Hard Disk Utility. Also check the D: hard
disk type in Standard Setup to make sure that
the hard disk drive type is correct.

D: Drive Failure Hard disk drive D: does not respond.

Replace the hard disk.

Diskette Boot Failure The boot disk in floppy drive A: is corrupt. It

cannot be used to boot the computer. Use
another boot disk and follow the screen
instructions.

Display Switch Some compters require a video switch on the

Not Proper motherboard be set to either color or
monochrome. Turn the computer off, set the
switch, then power on.

DMA Error Error in the DMA controller.

DMA #1 Error Error in the first DMA channel.

DMA #2 Error Error in the second DMA channel.

FDD Controller Failure The BIOS cannot communicate with the

floppy disk drive controller. Check all
appropriate connections after the computer is
powered down.

HDD Controller Failure The BIOS cannot communicate with the hard
disk drive controller. Check all appropriate
connections after the computer is powered
down.

INTR #1 Error Interrupt channel 1 failed POST.

INTR #2 Error Interrupt channel 2 failed POST.

A-5
BIOS User’s Manual

Error Message Information

Invalid Boot Diskette The BIOS can read the disk in floppy drive
A:, but cannot boot the computer. Use
another boot disk.

Keyboard Is Locked... The keyboard lock on the computer is

Unlock It engaged. The computer must be unlocked to
continue.

Keyboard Error There is a timing problem with the keyboard.

Set the Keyboard options in Standard Setup
to Not Installed to skip the keyboard post
routines.

KB/Interface Error There is an error in the keyboard connector.

No ROM BASIC Cannot find a bootable sector on either disk

drive A: or hard disk drive C:. The BIOS
calls INT 18h which generates this message.
Use a bootable disk.

Off Board Parity error in memory installed in an

Parity Error expansion slot. The format is:
OFF BOARD PARITY ERROR ADDR
(HEX) = (XXXX) XXXX is the hex
address where the error occurred. Run
AMIDiag to find and correct memory
problems.

On Board Parity error in motherboard memory. The

Parity Error format is:
ON BOARD PARITY ERROR ADDR
(HEX) = (XXXX) XXXX is the hex
address where the error occurred. Run
AMIDiag to find and correct memory
problems.

Parity Error???? Parity error in system memory at an unknown

address. Run AMIDiag to find and correct
memory problems.

A-6
 Appendix B: AMI BIOS POST Diagnostics Error Messages

Appendix B

AMI BIOS POST Diagnostic Error

Messages

This section describes the power-on self-tests (POST) port 80 codes for
the AMI BIOS.

Check
Point Description

00 Code copying to specific areas is done. Passing control

to INT 19h boot loader next.

03 NMI is Disabled. Next, checking for a soft reset or a

power-on condition.

05 The BIOS stack has been built. Next, disabling cache

memory.

06 Uncompressing the post code unit next.

07 Next, initializing the CPU init and the CPU data area.

08 The CMOS checksum calculation is done next.

0B Next, performing any required initialization before

keyboard BAT command is issued.

0C The keyboard controller I/B is free. Next, issuing the

BAT command to the keyboard controller.

0E The keyboard controller BAT command result has been

verified. Next, performing any necessary initialization
after the keyboard controller BAT command test.

0F The initialization after the keyboard controller BAT

command test is done. The keyboard command byte is
written next.

B-1
BIOS User’s Manual

Check
Point Description

10 The keyboard controller command byte is written.

Next, issuing the pin 23 and 24 blocking and unblocking
commands.

11 Next, checking if the <End or <Ins> keys were pressed

during power on. Initializing CMOS RAM if the
Initialize CMOS RAM in every boot AMIBIOS POST
option was set in AMIBCP or the <End> key was
pressed.

12 Next, disabling DMA controllers 1 and 2 and interrupt

controllers 1 and 2.

13 The video display has been disabled. Port B has been

initialized. Next, initializing the chipset.

14 The 8254 timer test will begin next.

19 The 8254 timer test is over. Starting the memory refresh

test next.

1A The memory refresh test line is toggling. Checking the

15 second on/off time next.

23 Reading the 8042 input port and disabling the

MEGAKEY Green PC feature next. Making the
BIOS code segment writable and performing any
necessary configuration before initializing the interrupt
vectors.

24 The configuration required before interrupt vector

initialization has completed. Interrupt vector initialization
is done. Clearing the password if the POST DIAG
switch is on.

25 Interrupt vector initialization is done. Clearing the

password if the POST DIAG Switch is on.

27 Any initialization before setting video mode will be

done next.

B-2
 Appendix B: AMI BIOS POST Diagnostics Error Messages

Check
Point Description

28 Initialization before setting the video mode is complete.

Configuring the monochrome mode and color mode
settings next.

2A Bus initialization system, static, output devices will be

done next, if present.

2B Passing control to the video ROM to perform any

required configuration before the video ROM test.

2C All necessary processing before passing control to the

video ROM is done. Looking for the video ROM next
and passing control to it.

2D The video ROM has returned control to BIOS POST.

Performing any required processing after the video
ROM had control.

2E Completed post-video ROM test processing. If the

EGA/VGA controller is not found, performing the
display memory read/write test next.

2F The EGA/VGA controller was not found. The display

memory read/write test is about to begin.

30 The display memory read/write test passed. Look for

retrace checking next.

31 The display memory read/write test or retrace checking

failed. Performing the alternate display memory
read/write test next.

32 The alternate display memory read/write test passed.

Looking for alternate display retrace checking next.

34 Video display checking is over. Setting the display

mode next.

37 The display mode is set. Displaying the power on

message next.

B-3
BIOS User’s Manual

Check
Point Description

38 Initializing the bus input, IPL, and general devices next, if

present.

39 Displaying bus initialization error messages.

3A The new cursor position has been read and saved.

Displaying the Hit <DEL> message next.

40 Preparing the descriptor tables next.

42 The descriptor tables are prepared. Entering protected

mode for the memory test next.

43 Entered protected mode. Enabling interrupts for

diagnostics mode next.

44 Interrupts enabled if the diagnostics switch is on.

Initializing data to check memory wraparound at 0:0 next.

45 Data initialized. Checking for memory wraparound at

0:0 and finding the total system memory size next.

46 The memory wraparound test has completed. The

memory size calculation has been completed. Writing
patterns to test memory next.

47 The memory pattern has been written to extended

memory. Writing patterns to the base 640 KB memory
next.

48 Patterns written in base memory. Determining the

amount of memory below 1 MB next.

49 The amount of memory below 1 MB has been found

and verified. Determining the amount of memory above
1 MB memory next.

4B The amount of memory above 1 MB has been found

and verified. Checking for a soft reset and clearing the
memory below 1 MB for the soft reset next. If this is a
power on situation, going to checkpoint 4Eh next.

B-4
 Appendix B: AMI BIOS POST Diagnostics Error Messages

Check
Point Description

4C The memory below 1 MB has been cleared via a soft

reset. Clearing the memory above 1 MB next.

4D The memory above 1 MB has been cleared via a soft

reset. Saving the memory size next. Going to checkpoint
52h next.

4E The memory test started, but not as the result of a soft

reset. Displaying the first 64 KB memory size next.

4F The memory size display has started. The display is

updated during the memory test. Performing the
sequential and random memory test next.

50 The memory below 1 MB has been tested and

initialized. Adjusting the displayed memory size for
relocation and shadowing next.

51 The memory size display was adjusted for relocation

and shadowing. Testing the memory above 1 MB next.

52 The memory above 1 MB has been tested and

initialized. Saving the memory size information next.

53 The memory size information and the CPU registers are

saved. Entering real mode next.

54 Shutdown was successful. The CPU is in real mode.

Disabling the Gate A20 line, parity, and the NMI next.

57 The A20 address line, parity, and the NMI are

disabled. Adjusting the memory size depending on
relocation and shadowing next.

58 The memory size was adjusted for relocation and

shadowing. Clearing the Hit <DEL> message next.

59 The Hit <DEL> message is cleared. The <WAIT>

message is displayed. Starting the DMA and interrupt
controller test next.

B-5
BIOS User’s Manual

Check
Point Description

60 The DMA page register test passed. Performing the

DMA Controller 1 base register test next.

62 The DMA controller 1 base register test passed.

Performing the DMA controller 2 base register test next.

65 The DMA controller 2 base register test passed.

Programming DMA controllers 1 and 2 next.

66 Completed programming DMA controllers 1 and 2.

Initializing the 8259 interrupt controller next.

7F Extended NMI source enabling is in progress.

80 The keyboard test has started. Clearing the output

buffer and checking for stuck keys. Issuing the
keyboard reset command next.

81 A keyboard reset error or stuck key was found. Issuing

the keyboard controller interface test command next.

82 The keyboard controller interface test completed.

Writing the command byte and initializing the circular
buffer next.

83 The command byte was written and global data

initialization has been completed. Checking for a
locked key next.

84 Locked key checking is over. Checking for a memory

size mismatch with CMOS RAM data next.

85 The memory size check is done. Displaying a soft error

and checking for a password or bypassing WINBIOS
Setup next.

86 The password was checked. Performing any required

programming before WINBIOS Setup next.

B-6
 Appendix B: AMI BIOS POST Diagnostics Error Messages

Check
Point Description

87 The programming before WINBIOS Setup has

been completed. Uncompressing the WINBIOS Setup
code and executing the AMIBIOS Setup or W INBIOS
Setup utility next.

88 Returned from WINBIOS Setup and cleared the screen.

Performing any necessary programming after WINBIOS
Setup next.

89 The programming after WINBIOS Setup has been

completed. Displaying the power-on screen message
next.

8B The first screen message has been displayed. The

<WAIT...> message is displayed. Performing the PS/2
mouse check and extended BIOS data area allocation
check next.

8C Programming the WINBIOS Setup options next.

8D The WINBIOS Setup options are programmed.

Resetting the hard disk controller next.

8F The hard disk controller has been reset. Configuring the

floppy drive controller next.

91 The floppy drive controller has been configured.

Configuring the hard disk drive controller next.

95 Initializing the bus option ROMs from C800 next.

96 Initializing before passing control to the adaptor ROM at

C800.

97 Initialization before the C800 adaptor ROM gains

control has been completed. The adaptor ROM check
is next.

98 The adaptor ROM had control and has now returned

control to BIOS POST. Performing any required
processing after the option ROM returned control.

B-7
BIOS User’s Manual

Check
Point Description

99 Any initialization required after the option ROM test has

been completed. Configuring the timer data area and
printer base address next.

9A Set the timer and printer base addresses. Setting the

RS-232 base address next.

9B Returned after setting the RS-232 base address.

Performing any required initialization before the
Coprocessor test next.

9C Required initialization before the Coprocessor test is

over. Initializing the Coprocessor next.

9D Coprocessor initialized. Performing any required

initialization after the Coprocessor test next.

9E Initialization after the Coprocessor test is complete.

Checking the extended keyboard, keyboard ID, and
Num Lock key next. Issuing the keyboard ID command
next.

A2 Displaying any soft errors next.

A3 The soft error display has completed. Setting the

keyboard typematic rate next.

A4 The keyboard typematic rate is set. Programming the

memory wait states next.

A5 Memory wait state programming is over. Clearing the

screen and enabling parity and the NMI next.

A7 NMI and parity enabled. Performing any initialization

required before passing control to the adaptor ROM at
E000 next.

A8 Initialization before passing control to the adaptor ROM

at E000h completed. Passing control to the adaptor
ROM at E000h next.

B-8
 Appendix B: AMI BIOS POST Diagnostics Error Messages

Check
Point Description

A9 Returned from adaptor ROM at E000h control.

Next, performing any initialization required after
the E000 option ROM had control.

AA Initialization after E000 option ROM control has

completed. Displaying the system configuration next.

AB Building the multiprocessor table, if necessary. POST

next.

B0 The system configuration is displayed.

AC Uncompressing the DMI data and initializing DMI.

B1 Copying any code to specific areas.

D0h The NMI is disabled. Power on delay is starting.

Next, the initialization cade checksum will be verified.

D1h Initializing the DMA controller. Performing the keyboard

controller BAT test. Starting memory refresh, and
entering 4 GB flat mode next.

D3h Starting memory sizing next.

D4h Returning to real mode. Executing any OEM patches

and setting the stack next.

D5h Passing control to the uncompressed code in shadow

RAM at E000:0000h. The initialization code is copied
to segment 0 and control will be transferred to segment
0.

D6h Control is in segment 0. Next, checking if

<Ctrl><Home>was pressed and verifying the system
BIOS checksum.

B-9
BIOS User’s Manual

If either <Ctrl><Home>was pressed or the system BIOS

checksum is bad, next the system will go to checkpoint code
E0h.

Otherwise, going to checkpoint code D7h.

B-10