Instruction Sets & Addressing

modes
 Instruction Sets
• There are various popular instruction sets that are
used in the industry and are of theoretical importance.
Each one has its own usage and advantages. Following
are the instruction set architectures:
• Reduced Instruction Set Computer (RISC)
• Complex Instruction Set Computer (CISC)
• Minimal instruction set computers (MISC)
• Very long instruction word (VLIW)
• Explicitly parallel instruction computing (EPIC)
• One instruction set computer (OISC)
• Zero instruction set computer (ZISC)
• Reduced Instruction Set Computer (RISC)
• Reduced Instruction Set Computer (RISC) is an instruction
set architecture (ISA) which has fewer cycles per instruction
(CPI) than a complex instruction set computer (CISC).
• RISC processors are also used in supercomputers such as
Summit, which, as of November 2018, is the world's fastest
supercomputer as ranked by the TOP500 project.
• Complex Instruction Set Computer (CISC)
• Complex Instruction Set Computer (CISC) is an instruction
set architecture (ISA) which has fewer instructions per
program than a Reduced instruction set computer (RISC).
• Minimal instruction set computers (MISC)
• Minimal instruction set computers (MISC) is a processor
architecture with a very small number of basic instruction
operations and corresponding opcodes.
• As a result of this is a smaller instruction set, a smaller and faster
instruction set decode unit, and faster operation of individual instructions.
The disadvantage is that smaller instruction set always have more
sequential dependencies, reducing instruction-level parallelism.
• Very long instruction word (VLIW)
• Very long instruction word (VLIW) is an instruction set
architectures designed to exploit instruction level parallelism (ILP).
• Central processing units (CPU, processor) mostly allow programs to specify
instructions to execute in sequence only, a VLIW processor allows
programs to explicitly specify instructions to execute in parallel. This
design is intended to allow higher performance without the complexity
inherent in some other designs.
• Explicitly parallel instruction computing (EPIC)
• Explicitly parallel instruction computing (EPIC) is an instruction set that
permits microprocessors to execute software instructions in parallel by
using the compiler, rather than complex on-die circuitry, to control
parallel instruction execution.
• This was intended to allow simple performance scaling without resorting
to higher clock frequencies
• One instruction set computer (OISC)
• One instruction set computer (OISC) is an abstract
machine that uses only one instruction obviating the
need for a machine language opcode.
• OISCs have been recommended as guides in teaching
computer architecture and have been used as
computational models in structural computing
research.
• Zero instruction set computer (ZISC)
• Zero instruction set computer (ZISC) is a computer
architecture based on pattern matching and absence of
(micro-)instructions in the classical sense.
• These chips are known for being thought of as
comparable to the neural networks being marketed for
the number of "synapses" and "neurons"
 Addressing Modes
• 1. Implied Addressing Mode-
•
• In this addressing mode,
• The definition of the instruction itself specify the operands implicitly.
• It is also called as implicit addressing mode.
•
• Examples-
•
• The instruction “Complement Accumulator” is an implied mode
instruction.
• In a stack organized computer, Zero Address Instructions are implied
mode instructions.
• (since operands are always implied to be present on the top of the stack)
• 2. Stack Addressing Mode-
•
• In this addressing mode,
• The operand is contained at the top of the stack.
•
• Example-
•
• ADD
• This instruction simply pops out two symbols contained at the top
of the stack.
• The addition of those two operands is performed.
• The result so obtained after addition is pushed again at the top of
the stack.
• 3. Immediate Addressing Mode-
•
• In this addressing mode,
• The operand is specified in the instruction explicitly.
• Instead of address field, an operand field is present that contains
the operand.
•

•
• Examples-

• ADD 10 will increment the value stored in the accumulator by 10.

• MOV R #20 initializes register R to a constant value 20.
• 4. Direct Addressing Mode-
•
• In this addressing mode,
• The address field of the instruction contains the effective address of the operand.
• Only one reference to memory is required to fetch the operand.
• It is also called as absolute addressing mode.
•
•

• Example-
•
• ADD X will increment the value stored in the accumulator by the value stored at memory location X.
• AC ← AC + [X]
• 5. Indirect Addressing Mode-
•
• In this addressing mode,
• The address field of the instruction specifies the address of memory location that contains the
effective address of the operand.
• Two references to memory are required to fetch the operand.
•

•
• Example-
•
• ADD X will increment the value stored in the accumulator by the value stored at memory location
specified by X.
• AC ← AC + [[X]]
• 6. Register Direct Addressing Mode-
•
• In this addressing mode,
• The operand is contained in a register set.
• The address field of the instruction refers to a CPU register that contains the operand.
• No reference to memory is required to fetch the operand.
•

•
• Example-
•
• ADD R will increment the value stored in the accumulator by the content of register R.
• AC ← AC + [R]
•
• NOTE-
•
• It is interesting to note-
• This addressing mode is similar to direct addressing mode.
• The only difference is address field of the instruction refers to a CPU register instead of main
memory.
• 7. Register Indirect Addressing Mode-
•
• In this addressing mode,
• The address field of the instruction refers to a CPU register that contains the effective address of
the operand.
• Only one reference to memory is required to fetch the operand.
•

•
• Example-
• ADD R will increment the value stored in the accumulator by the content of memory location
specified in register R.
• AC ← AC + [[R]]
•
• NOTE-
•
• It is interesting to note-
• This addressing mode is similar to indirect addressing mode.
• The only difference is address field of the instruction refers to a CPU register.
•
• 8. Relative Addressing Mode-
•
• In this addressing mode,
• Effective address of the operand is obtained by adding the content
of program counter with the address part of the instruction.
•

• NOTE-
• Program counter (PC) always contains the address of the next
instruction to be executed.
• After fetching the address of the instruction, the value of program
counter immediately increases.
• The value increases irrespective of whether the fetched
instruction has completely executed or not.
• 9. Indexed Addressing Mode-
•
• In this addressing mode,
• Effective address of the operand is obtained
by adding the content of index register with
the address part of the instruction.
• 10. Base Register Addressing Mode-
•
• In this addressing mode,
• Effective address of the operand is obtained
by adding the content of base register with
the address part of the instruction.
• 11. Auto-Increment Addressing Mode-
•
• This addressing mode is a special case of Register Indirect Addressing Mode where-
• In this addressing mode,
• After accessing the operand, the content of the register is automatically incremented by step size
‘d’.
• Step size ‘d’ depends on the size of operand accessed.
• Only one reference to memory is required to fetch the operand.
• Example-
•

•
• Assume operand size = 2 bytes.
• Here,
• After fetching the operand 6B, the instruction register RAUTO will be automatically incremented by
2.
• Then, updated value of RAUTO will be 3300 + 2 = 3302.
• At memory address 3302, the next operand will be found.
•
• NOTE-
•
• In auto-increment addressing mode,
• First, the operand value is fetched.
• Then, the instruction register RAUTO value is incremented by step size ‘d’.
• 12. Auto-Decrement Addressing Mode-
•
• This addressing mode is again a special case of Register Indirect Addressing Mode where-
•
•
• In this addressing mode,
• First, the content of the register is decremented by step size ‘d’.
• Step size ‘d’ depends on the size of operand accessed.
• After decrementing, the operand is read.
• Only one reference to memory is required to fetch the operand.

•
• Example-

• Assume operand size = 2 bytes.

• Here,
• First, the instruction register RAUTO will be decremented by 2.
• Then, updated value of RAUTO will be 3302 – 2 = 3300.
• At memory address 3300, the operand will be found.
•
• NOTE-
•
• In auto-decrement addressing mode,
• First, the instruction register RAUTO value is decremented by step size ‘d’.
• Then, the operand value is fetched.
•
 Application of addressing modes
• Direct Addressing Mode
• and
• Register Direct Addressing Mode
• To access static data
• To implement variables
• Indirect Addressing Mode
• and
• Register Indirect Addressing Mode
• To implement pointers because pointers are memory locations that store the
address of another variable
• To pass array as a parameter because array name is the base address and pointer is
needed to point the address
• Relative Addressing Mode
• For program relocation at run time i.e. for position independent code
• To change the normal sequence of execution of instructions
• For branch type instructions since it directly updates the program counter
• Relative Addressing Mode

• For program relocation at run time i.e. for position independent code
• To change the normal sequence of execution of instructions
• For branch type instructions since it directly updates the program counter

• Index Addressing Mode

• For array implementation or array addressing
• For records implementation

• Base Register Addressing Mode

• For writing relocatable code i.e. for relocation of program in memory even at run time
• For handling recursive procedures

• Auto-increment Addressing Mode

• and
• Auto-decrement Addressing Mode
• For implementing loops
• For stepping through arrays in a loop
• For implementing a stack as push and pop
Difference between CISC and RISC