Scribd
Upload
16 views

Verilog

The document provides an introduction to Verilog hardware description language (HDL). It covers topics like the evolution of HDLs, typical design flows, importance of HDLs, trends in Verilog, basic methodologies like modules and instances. It also discusses what a Verilog hardware schematic is and how it represents digital circuits using modules, inputs, outputs, and logic assignments.

Uploaded by

mayank kumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
16 views

Verilog

The document provides an introduction to Verilog hardware description language (HDL). It covers topics like the evolution of HDLs, typical design flows, importance of HDLs, trends in Verilog, basic methodologies like modules and instances. It also discusses what a Verilog hardware schematic is and how it represents digital circuits using modules, inputs, outputs, and logic assignments.

Uploaded by

mayank kumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 13

INTRODUCTION TO VERILOG

CLASS – 1

Rupesh Kumar T
Agenda:
• Why HDL’s & Evolution of HDL’s
• Typical design flow
• Importance of HDL’s
• Why Verilog
• Trends in Verilog
• Basic Methodologies
• Modules and Instances

Rupesh Kumar T
Why HDL’s ? & Evolution of HDL’s

Tech Evolution:
• SSI (Small Scale Integration)
• MSI (Medium Scale Integration)
• LSI (Large Scare Integration)
• VLSI (Very Large Scale Integration)

Software languages:
• FORTRAN, Pascal, and C

Rupesh Kumar T
Typical design flow :

Rupesh Kumar T
Importance of HDL’s

❖ Traditional schematic-based design is difficult


❖ No worry of fabrication technology (front end)
❖ Functional verification is easy, prevent bug early
❖ Gate-level schematics are almost incomprehensible for very
complex designs.

Rupesh Kumar T
Why verilogHDL :

✓ Easy to learn, easy to use, and C-type syntax


✓ Different Levels of abstractions (switch, gates, RTL and
behavioral)
✓ Most synthesis tool supports
✓ libraries for post logic synthesis
✓ The Programming Language Interface (PLI)

Rupesh Kumar T
Trends in Verilog :
• HDL at an RTL
• Verilog Keeps on updates (Verilog-95, 2001,
2005,2009)
• Supports verification methodologies
• Assertion checking techniques
• Support for automatic stimulus creation(test
bench)

Rupesh Kumar T
Basic Methodologies :

• Top-down method

• Bottom-up method

Rupesh Kumar T
What is a hardware schematic ?
1. A hardware schematic is represented using a hardware description language
(HDL), which is a text-based language for describing the behavior and
structure of digital circuits.
• A Verilog hardware schematic is a set of code that specifies how digital
components (such as gates and flip-flops) are interconnected to form a digital
circuit.

1. Module Declaration: In Verilog, you start by declaring a module. This is like a


container for your digital circuit.
•input wire a, input wire b: These lines declare input wires named a and b.
•output wire y: This line declares an output wire named y.

module MyCircuit (
input wire a,
input wire b,
output wire y
);

Rupesh Kumar T
Conti…

2. Logic Assignment:

• Inside the module, you describe the logical relationships between the inputs and
outputs. For example, an AND gate can be expressed as follows:

assign y = a & b;

This line means that the output y is the result of the logical
AND operation between inputs a and b.

3. End of Module:
You close the module definition.

endmodule

• So, in Verilog, a hardware schematic is essentially a textual representation that describes the
components, connections, and logic of a digital circuit.
• This Verilog code can then be synthesized to generate an actual hardware implementation, such as a
programmable logic device (PLD) or an application-specific integrated circuit (ASIC).
Rupesh Kumar T
Modules :

Modules:

module <module_name> (<module_terminal_list>);


...
<module internals>
...
...
endmodule

• MODELLING STYLES
a. data flow
b. behavioral
c. structural
d. Mixed modeling
e. Gate level
f. Switch level

Rupesh Kumar T
Component of simulation :

Rupesh Kumar T
THANK YOU🙏

Rupesh Kumar T

You might also like