CND 221

ADVANCED FULL CUSTOM VLSI DESIGN

LAB 06: Designing Memories and Array Structures

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Contents
OBJECTIVE: .............................................................................................................................. 3
INTRODUCTION: ..................................................................................................................... 3
SRAM: .......................................................................................................................................... 7
LAYOUT OF 6T SRAM: ........................................................................................................... 8
 SOME TIPS FOR LAYOUT: ...................................................................................................... 9
REQUIREMENTS: .................................................................................................................. 10

List of Figures
Figure 1: Memory array architecture. .......................................................................................... 5
Figure 2: Example on Folded memory array architecture. .......................................................... 6
Figure 3: 6T SRAM cell. ............................................................................................................. 7
Figure 4: Bit-line conditioning circuits. ....................................................................................... 8
Figure 5: 6T SRAM Column while read/write operation ............................................................ 8
Figure 6: N-well spacing Vs. Shared N-well. .............................................................................. 9
Figure 7: Layout of 6T SRAM cell .............................................................................................. 9

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OBJECTIVE:
In this lab, the primary objective is to design a 6T SRAM cell, a crucial building block for static
memory storage. Through hands-on design, simulation, and analysis, participants will gain a deep
understanding of designing a 6T memory cell.
INTRODUCTION:
Memory arrays have many types, each type has its applications according to its required specs.
The most important merit for the memory is its density, as any customer needs a larger memory
in a small chip which means that the memory density needs to be high. To achieve that the
memory cell needs to be small, so our goal is to minimize the size of the memory cell as much
as we can.

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Analogy for SRAM Analogy for DRAM

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In general, the cells of memory are arranged in an array form. The
array consists of 2n rows (word) and 2m columns (bits or memory
W
cells). In case of RAM, the memory takes the address which is n-
bits width and gives the data bits which is 2m bits width. The
memory array architecture consists of the following:
 Row Decoder (n:2n):
This is a one hot decoder, takes n-bits of address and gives 2n
signals, one of the 2n signals is high while the others are zeros.
It does that to activate only one word-line from the 2n word-
lines.
 Column Circuitry:
May contain amplifiers or buffers to sense the data (read or write
the data). The output bus of the column circuitry is bidirectional
as it can be read from or written to the memory through it.
 Memory Cell:
It stores only one bit.

To read or write from memory, then first apply the n-bit address
Figure 1: Memory array
that activates a certain word-line. The activated word-line activates architecture.
the cells in this line, these activated cells drive the bit-lines with the
bits stored in them which propagate to the column circuitry and pass through it.

A typical memory array may have thousands or millions of words of only 8-64 bits each, which
would lead to a tall, skinny layout that is hard to fit in the chip floorplan and slow because of the
long vertical wires. Therefore, the array is often folded into fewer rows of more columns by
putting multiple words in the single word-line instead of only one word (If n>>m  then fold by
2k into fewer rows of more columns). In this case, there is a need for a special column decoder
because the activation of a single word-line leads to accessing multiple words, so, there is a need
to choose one word from multiple words to pass through the port, and this is the mission of the
column decoder (the column decoder could be a multiplex not an actual decoder). The n-bits
address is divided into n-k bits that determine the word-line and k bits to determine the chosen
word from the multiple words. Then after folding, each row of the memory contains 2k words, so
the array is physically organized as 2n-k rows of 2m+k columns or bits.
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Larger memories are built in a hierarchical manner. They are generally built from multiple
smaller subarrays so that the word-lines and bit-lines remain reasonably short, fast, and low in
power dissipation.

Note:
 The memory has good regularity which eases its design process.
 The 2k are interleaved together, not arranged sequentially.

Bit 0 Bit 0 Bit 1 Bit 1 Bit 2 Bit 2 Bit 3 Bit 3

Word 1 and Word 2

bits are interleaved
together.

Figure 2: Example on Folded memory array architecture.

Example: let n = 4, m = 2, k = 2
This means that, the memory has 2n-k = 24-2 word-line (row) signal outputs from the row decoder
and each word-line has k = 2 words (input mux) where is each word has 2m = 22 bit (column
decoder/mux).

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SRAM:
SRAM, the most widely used form of on-chip memory. Static RAMs use a memory cell with
internal feedback that retains its value as long as power is applied. It has the following attractive
properties: Denser than flip-flops - Compatible with standard CMOS processes - Faster than
DRAM - Easier to use than DRAM. The SRAM consists of an array of memory cells along with
the row and column circuitry. This section examines the design and operation of the SRAM cell.

A SRAM cell needs to be able to read and write data and to hold the data as long as the power is
applied. An ordinary flip-flop could accomplish this requirement, but the size is QUITE
LARGE.

Figure 3: 6T SRAM cell.

Data stored in cross coupled inverter and the cell is accessible through the two NMOS pass
transistors as shown in Figure 3.

Operation:

Read Operation:

A pre-charge for bit-line and inverted bit-line must be occurred, When the word line raised
NMOS pass transistor is ON and if the value inside the cell is Zero the bit-line discharge it’s pre-
charged ONE and the value on the bit-line become Zero “The same value inside the storage cell”
so I succeed to read the value inside the cell, but if the value inside was ONE, the pre-charged
value on the bit-line stay the same as no charge difference between them.

Write Operation:

The driven data is on bit-line and inverted bit-line and when the word-line is raised, bit-line signal
pass through NMOS and force the value in the cell.

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Notes:

- The pre-charging occurred in Read Operation is essential as NMOS pass transistor provide
strong zero and weak one, so if the bit-line is not pre-charged we will get a weak one on it.

- Cross coupled inverter transistors should be strong enough to be disturbed a read (resistance
of NMOS transistor of inverter should be smaller than that of NMOS Pass transistor) and
they should be weak enough to be overpowered in writing
(resistance of PMOS transistor should be Larger than that
of NMOS Pass transistor).

- A PMOS transistor (Equalizer transistor) can be used as

shown in Figure 4 to make sure that bit-line and bit-line
inverse have the same voltage (approximately VDD),
this also decreases the charging time. Figure 4: Bit-line conditioning circuits.

- The inverters used in reading circuit are high skewed as their input is always falling so that
their output is always rising, as bit-line is always pre-charged so if the value stored is one it
will stay one and if the value stored is zero it will fall to zero.

- Read and Write circuits become more complex as shown in Figure 5, both read and write
circuits are implemented for each cell in SRAM.

- SRAM is faster than DRAM, but DRAM is denser than SRAM due to the large area of SRAM
cell in comparable to DRAM cell. There is always a tradeoff between the speed and the
density of the memories.

Figure 5: 6T SRAM Column while read/write operation

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 Some tips for layout:
 Make the n-well shared. This will give you a denser layout.

Figure 6: N-well spacing Vs. Shared N-well.

 Make diffusions shared to reduce the parasitic capacitances and also to save area.

 Make the bulk in the “top tap” if it is connected to VDD and “Bottom tap” if it is connected
to GND to make routing easier.

Figure 7 shows the final Layout of 6T SRAM Cell:

Figure 7: Layout of 6T SRAM cell

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REQUIREMENTS:
1. Comprehensive schematic diagrams illustrating the intricacies of the advanced 6T SRAM cell
design.

Answers:

2. Rigorous simulation results highlighting the stability and functionality of the designed 6T
SRAM cell.

Answers:

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Sources Values:

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3. Preform the layout of 6T SRAM considering factors such as area, stability, and access times.

Answers:

4. Apply the design verification steps DRC, LVS, and PEX.

5. Perform post layout simulation for performance, and stability check for 6T after applying the
parasitics.

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