Speedup
Speedup
Speedup
11.
12.
13.
14.limitations in applying Amdahl’s Law:
i. Gustafon’s Law: The proportion of the computations that are
sequential normally decreases as the problem size increases.
ii. Its proof focuses on the steps in a particular algorithm, and
does not consider that other algorithms with more parallelism
may exist
iii. Amdahl’s law applies only to ‘standard’ problems were
superlinearity can not occur
15.
Amdahl's Law Gustafson's Law
Amdahl’s Law focuses on fixed Gustafson’s Law considers variable
problem size problem size.
Amdahl’s Law emphasizes Gustafson’s Law emphasizes scaling
optimizing the serial portion up the workload.
Amdahl’s Law limits the speedup by Gustafson’s Law focuses on efficient
the non-parallelizable fraction utilization of parallel resources.
Underlines the need to optimize Stresses benefits from parallelism in
sequential portion. real-world, large-scale problems.
16.Math-01 :
17.Math-02 :
18.Math-03 :
2. Development Layer:
3. Three shared- memory multiprocessor models:
i. The uniform memory-access(UMA) model
ii. The nonuniform-memory-access(NUMA)model
iii. The cache-only memory architecture(COMA)model
4. Pipelining in Superscolor Processor:
2. The process resides The process resides More than one thread The process switches
in the main memory. in the same CPU. processed on a single from one to another CPU
CPU. as multiple processing
units are used.
3. It uses batch OS. It is time sharing as The tasks are always It carries multiple
The CPU is utilized the task assigned further divided into processors to execute the
completely while switches regularly. sub tasks. task.
execution.
11.
CISC RISC
1.It has a microprogramming unit. It has a hard-wired unit of programming.
2.The instruction set has various
The instruction set is reduced, and most of
different instructions that can be used for
these instructions are very primitive.
complex operations.
3.Performance is optimized with Performance is optimized which emphasis
emphasis on hardware. on software
4.Only single register set Multiple register sets are present
5.They are mostly less or not pipelined This type of processors are highly pipelined
CISC RISC
6.Execution time is very high Execution time is very less
7.Code expansion is not a problem. Code expansion may create a problem.
8.Decoding of instructions is complex. The decoding of instructions is simple.
9.It requires external memory for It doesn’t require external memory for
calculations calculations
10.Examples of CISC processors are the Common RISC microprocessors are ARC,
System/360, VAX, AMD, and Intel x86 Alpha, ARC, ARM, AVR, PA-RISC, and
CPUs. SPARC.
11.Instructions can take several clock
Single-cycle for each instruction
cycles
Heavy use of RAM (can cause bottlenecks
12.More efficient use of RAM than RISC
if RAM is limited)
13.Simple, standardized instructions Complex and variable-length instructions
14.A small number of fixed-length
A large number of instructions
instructions
15.Limited addressing modes Compound addressing modes
16.Important applications are Security Important applications are : Smartphones,
systems, Home automation. PDAs.