NTMD6N03R2

Power MOSFET
30 V, 6 A, Dual N−Channel SOIC−8

Features
• Designed for use in low voltage, high speed switching applications http://onsemi.com
• Ultra Low On−Resistance Provides
Higher Efficiency and Extends Battery Life VDSS RDS(ON) Typ ID Max
− RDS(on) = 0.024 W, VGS = 10 V (Typ)
30 V 24 mW @ VGS = 10 V 6.0 A
− RDS(on) = 0.030 W, VGS = 4.5 V (Typ)
• Miniature SOIC−8 Surface Mount Package Saves Board Space
• Diode is Characterized for Use in Bridge Circuits N−Channel
• Diode Exhibits High Speed, with Soft Recovery D D
• Pb−Free Package is Available

Applications
G G
• DC−DC Converters
• Computers
S S
• Printers
• Cellular and Cordless Phones MARKING DIAGRAM &
• Disk Drives and Tape Drives PIN ASSIGNMENT
D1 D1 D2 D2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 8 8
Rating Symbol Value Unit 1 E6N03
Drain−to−Source Voltage VDSS 30 Volts SOIC−8 AYWW G
CASE 751 G
Gate−to−Source Voltage − Continuous VGS "20 Volts STYLE 11
1
Drain Current
− Continuous @ TA = 25°C ID 6.0 Adc S1 G1 S2 G2
− Single Pulse (tp ≤ 10 ms) IDM 30 Apk
Total Power Dissipation PD Watts E6N03 = Specific Device Code
@ TA = 25°C (Note 1) 2.0 A = Assembly Location
@ TA = 25°C (Note 2) 1.29 Y = Year
WW = Work Week
Operating and Storage Temperature TJ, Tstg −55 to °C
Range +150 G = Pb−Free Package

Single Pulse Drain−to−Source Avalanche EAS 325 mJ (Note: Microdot may be in either location)
Energy − Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 5.0 Vdc,
VDS = 20 Vdc, Peak IL = 9.0 Apk, ORDERING INFORMATION
L = 10 mH, RG = 25 W)
Thermal Resistance Device Package Shipping†
RqJA °C/W
− Junction−to−Ambient (Note 1) 62.5
NTMD6N03R2 SOIC−8 2500/Tape & Reel
− Junction−to−Ambient (Note 2) 97
Maximum Lead Temperature for Soldering TL 260 °C NTMD6N03R2G SOIC−8 2500/Tape & Reel
Purposes for 10 seconds (Pb−Free)
Maximum ratings are those values beyond which device damage can occur. †For information on tape and reel specifications,
Maximum ratings applied to the device are individual stress limit values (not including part orientation and tape sizes, please
normal operating conditions) and are not valid simultaneously. If these limits are refer to our Tape and Reel Packaging Specification
exceeded, device functional operation is not implied, damage may occur and Brochure, BRD8011/D.
reliability may be affected.
1. When surface mounted to an FR4 board using 1″ pad size, t ≤ 10 s
2. When surface mounted to an FR4 board using 1″ pad size, t = steady state

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

February, 2006 − Rev. 2 NTMD6N03R2/D
 NTMD6N03R2

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 250 mA) 30 − −
Temperature Coefficient (Positive) − 30 − mV/°C

Zero Gate Voltage Drain Current IDSS mAdc

(VDS = 24 Vdc, VGS = 0 Vdc, TJ = 25°C) − − 1.0
(VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125°C) − − 20
Gate−Body Leakage Current IGSS nAdc
(VGS = ±20 Vdc, VDS = 0 Vdc) − − 100

ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS(th) Vdc
(VDS = VGS, ID = 250 mAdc) 1.0 1.8 2.5
Temperature Coefficient (Negative) − 4.6 − mV/°C

Static Drain−to−Source On−State Resistance RDS(on) W

(VGS = 10 Vdc, ID = 6 Adc) − 0.024 0.032
(VGS = 4.5 Vdc, ID = 3.9 Adc) − 0.030 0.040
Forward Transconductance gFS Mhos
(VDS = 15 Vdc, ID = 5.0 Adc) − 10 −

DYNAMIC CHARACTERISTICS
Input Capacitance Ciss − 680 950 pF
Output Capacitance (VDS = 24 Vdc, VGS = 0 Vdc, Coss − 210 300
f = 1.0 MHz)
Reverse Transfer Capacitance Crss − 70 135
SWITCHING CHARACTERISTICS (Notes 3 & 4)
Turn−On Delay Time td(on) − 9 18 ns
Rise Time (VDD = 15 Vdc, ID = 1 A, tr − 22 40
VGS = 10 V,
Turn−Off Delay Time RG = 6 W) td(off) − 45 80
Fall Time tf − 45 80
Turn−On Delay Time td(on) − 13 30 ns
Rise Time (VDD = 15 Vdc, ID = 1 A, tr − 27 50
VGS = 4.5 V,
Turn−Off Delay Time RG = 6 W) td(off) − 22 40
Fall Time tf − 34 70
Gate Charge QT − 19 30 nC
(VDS = 15 Vdc, Q1 − 2.4 −
VGS = 10 Vdc,
ID = 5 A) Q2 − 5.0 −
Q3 − 4.3 −
BODY−DRAIN DIODE RATINGS (Note 3)
Diode Forward On−Voltage (IS = 1.7 Adc, VGS = 0 V) VSD − 0.75 1.0 Vdc
(IS = 1.7 Adc, VGS = 0 V, TJ = 150°C) − 0.62 −
Reverse Recovery Time trr − 26 − ns
(IS = 5 A, VGS = 0 V,
ta − 11 −
dIS/dt = 100 A/ms)
tb − 15 −
Reverse Recovery Stored Charge QRR − 0.015 − mC
(IS = 5 A, dIS/dt = 100 A/ms, VGS = 0 V)
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.

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 NTMD6N03R2

TYPICAL MOSFET ELECTRICAL CHARACTERISTICS

12 12
10 V 3.4 V TJ = 25°C
VDS ≥ 10 V
6V 3.6 V
ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

10 10
4V 3.8 V 3.2 V
8 8

6 6
3V
TJ = 25°C
4 4
2.8 V
2 2 TJ = 125°C
VGS = 2.6 V TJ = −55°C
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 1 2 3 4 5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

0.05 0.05
VGS = 10 TJ = 25°C
0.045 0.045

0.04 0.04

0.035 T = 125°C 0.035

0.03 0.03 VGS = 4.5 V

0.025 0.025
T = 25°C
0.02 0.02 VGS = 10 V
T = −55°C
0.015 0.015
0.01 0.01
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current
and Temperature and Gate Voltage
RDS(on), DRAIN−TO−SOURCE RESISTANCE

1.8 10,000
VGS = 0 V
ID = 3 A
1.6
VGS = 10 V
IDSS, LEAKAGE (nA)

TJ = 150°C
1.4 1000
(NORMALIZED)

1.2
TJ = 125°C
1 100

0.8

0.6 10
−50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current

Temperature versus Voltage

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POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge a voltage corresponding to the off−state condition when
controlled. The lengths of various switching intervals (Dt) calculating td(on) and is read at a voltage corresponding to the
are determined by how fast the FET input capacitance can on−state when calculating td(off).
be charged by current from the generator. At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain−gate capacitance source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive
average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt
rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
t = Q/IG(AV)
complicates the mathematics. And finally, MOSFETs have
During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the
resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance
known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified.
times may be approximated by the following: The resistive switching time variation versus gate
tr = Q2 x RG/(VGG − VGSP) resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
tf = Q2 x RG/VGSP
the parasitics were not present, the slope of the curves would
where maintain a value of unity regardless of the switching speed.
VGG = the gate drive voltage, which varies from zero to VGG The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
RG = the gate drive resistance is believed readily achievable with board mounted
and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the
During the turn−on and turn−off delay times, gate current is data in the figure is taken with a resistive load, which
not constant. The simplest calculation uses appropriate approximates an optimally snubbed inductive load. Power
values from the capacitance curves in a standard equation for MOSFETs may be safely operated into an inductive load;
voltage change in an RC network. The equations are: however, snubbing reduces switching losses.
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1600
Ciss TJ = 25°C
1400

1200
C, CAPACITANCE (pF)

1000

800 Crss Ciss

600

400 Coss

200 Crss
VDS = 0 V VGS = 0 V
0
10 5 0 5 10 15 20 25
VGS VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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 NTMD6N03R2

10 30 1000

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
QT VDD = 15 V
ID = 6 A
td(off)
8 VGS = 10 V
VGS
20 100 tf

t, TIME (ns)
6
VDS tr
Q1 Q2
4
10 10 td(on)
ID = 6 A
2
TJ = 25°C
Q3
0 0 1
0 2 4 6 8 10 12 14 16 18 20 1 10 100
Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (W)
Figure 8. Gate−to−Source and Figure 9. Resistive Switching Time Variation
Drain−to−Source Voltage versus Total Charge versus Gate Resistance

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode high di/dts. The diode’s negative di/dt during ta is directly
are very important in systems using it as a freewheeling or controlled by the device clearing the stored charge.
commutating diode. Of particular interest are the reverse However, the positive di/dt during tb is an uncontrollable
recovery characteristics which play a major role in diode characteristic and is usually the culprit that induces
determining switching losses, radiated noise, EMI and RFI. current ringing. Therefore, when comparing diodes, the
System switching losses are largely due to the nature of ratio of tb/ta serves as a good indicator of recovery
the body diode itself. The body diode is a minority carrier abruptness and thus gives a comparative estimate of
device, therefore it has a finite reverse recovery time, trr, due probable noise generated. A ratio of 1 is considered ideal and
to the storage of minority carrier charge, QRR, as shown in values less than 0.5 are considered snappy.
the typical reverse recovery wave form of Figure 14. It is this Compared to ON Semiconductor standard cell density
stored charge that, when cleared from the diode, passes low voltage MOSFETs, high cell density MOSFET diodes
through a potential and defines an energy loss. Obviously, are faster (shorter trr), have less stored charge and a softer
repeatedly forcing the diode through reverse recovery reverse recovery characteristic. The softness advantage of
further increases switching losses. Therefore, one would the high cell density diode means they can be forced through
like a diode with short trr and low QRR specifications to reverse recovery at a higher di/dt than a standard cell
minimize these losses. MOSFET diode without increasing the current ringing or the
The abruptness of diode reverse recovery effects the noise generated. In addition, power dissipation incurred
amount of radiated noise, voltage spikes, and current from switching the diode will be less due to the shorter
ringing. The mechanisms at work are finite irremovable recovery time and lower switching losses.
circuit parasitic inductances and capacitances acted upon by
6
VGS = 0 V
IS, SOURCE CURRENT (AMPS)

5 TJ = 25°C

0
0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current

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 NTMD6N03R2

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define total power averaged over a complete switching cycle must
the maximum simultaneous drain−to−source voltage and not exceed (TJ(MAX) − TC)/(RmJC).
drain current that a transistor can handle safely when it is A power MOSFET designated E−FET can be safely used
forward biased. Curves are based upon maximum peak in switching circuits with unclamped inductive loads. For
junction temperature and a case temperature (TC) of 25°C. reliable operation, the stored energy from circuit inductance
Peak repetitive pulsed power limits are determined by using dissipated in the transistor while in avalanche must be less
the thermal response data in conjunction with the procedures than the rated limit and must be adjusted for operating
discussed in AN569, “Transient Thermal Resistance − conditions differing from those specified. Although industry
General Data and Its Use.” practice is to rate in terms of energy, avalanche energy
Switching between the off−state and the on−state may capability is not a constant. The energy rating decreases
traverse any load line provided neither rated peak current non−linearly with an increase of peak current in avalanche
(IDM) nor rated voltage (VDSS) is exceeded, and that the and peak junction temperature.
transition time (tr, tf) does not exceed 10 ms. In addition the

100 325

EAS, SINGLE PULSE DRAIN−TO−SOURCE

VGS = 12 V 300
SINGLE PULSE
ID, DRAIN CURRENT (AMPS)

275 ID = 6 A
TA = 25°C 1.0 ms
250

AVALANCHE ENERGY (mJ)

10
225
10 ms 200
175
1
150
dc 125
100
0.1 75
RDS(on) LIMIT
THERMAL LIMIT 50
PACKAGE LIMIT 25
0.01 0
0.1 1.0 10 100 25 50 75 100 125 150
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

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 NTMD6N03R2

TYPICAL ELECTRICAL CHARACTERISTICS

1.0
D = 0.5
Rthja(t), EFFECTIVE TRANSIENT

0.2
THERMAL RESISTANCE

0.1
0.1
0.05
0.02
0.0106 W 0.0431 W 0.1643 W 0.3507 W 0.4302 W
0.01 CHIP
0.01 JUNCTION 0.0253 F 0.1406 F 0.5064 F 2.9468 F 177.14 F

AMBIENT
SINGLE PULSE
0.001
1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

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 NTMD6N03R2

PACKAGE DIMENSIONS

SOIC−8 NB
CASE 751−07
ISSUE AG NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45 _ A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
SOLDERING FOOTPRINT* 3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
1.52 8. DRAIN 1
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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