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FST 16211

The document describes a 24-bit bus switch chip. It provides details on the chip's features, pinouts, logic diagram, truth table and electrical specifications. The chip allows high-speed switching between two 24-bit ports and has low on resistance and propagation delay.

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0% found this document useful (0 votes)
42 views8 pages

FST 16211

The document describes a 24-bit bus switch chip. It provides details on the chip's features, pinouts, logic diagram, truth table and electrical specifications. The chip allows high-speed switching between two 24-bit ports and has low on resistance and propagation delay.

Uploaded by

puh1967
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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FST16211 24-Bit Bus Switch

July 1997
Revised August 2000

FST16211
24-Bit Bus Switch
General Description Features
The Fairchild Switch FST16211 provides 24-bits of high- ■ 4Ω switch connection between two ports
speed CMOS TTL-compatible bus switching. The low on ■ Minimal propagation delay through the switch
resistance of the switch allows inputs to be connected to
■ Low lCC
outputs without adding propagation delay or generating
additional ground bounce noise. ■ Zero bounce in flow-through mode
The device is organized as a 12-bit or 24-bit bus switch. ■ Control inputs compatible with TTL level
When OE1 is LOW, the switch is ON and Port 1A is con- ■ Also packaged in plastic Fine Pitch Ball Grid Array
nected to Port 1B. When OE2 is LOW, Port 2A is connected (FBGA)
to Port 2B. When OE1/2 is HIGH, a high impedance state
exists between the A and B Ports.

Ordering Code:
Order Number Package Number Package Description
FST16211GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide
(Note 1) Preliminary [TAPE and REEL]
FST16211MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
FST16211MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 1: BGA package available in Tape and Reel only.

Logic Diagram

© 2000 Fairchild Semiconductor Corporation DS500037 www.fairchildsemi.com


FST16211
Connection Diagrams Pin Descriptions
Pin Assignment for SSOP and TSSOP Pin Name Description
OE1, OE2 Bus Switch Enables
1A, 2A Bus A
1B, 2B Bus B

FBGA Pin Assignments


1 2 3 4 5 6
A 1A2 1A1 NC OE2 1B1 1B2
B 1A4 1A3 1A7 OE1 1B3 1B4
C 1A6 1A5 GND 1B7 1B5 1B6
D 1A10 1A9 1A8 1B8 1B9 1B10
E 1A12 1A11 2A1 2B1 1B11 1B12
F 2A4 2A3 2A2 2B2 2B3 2B4
G 2A6 2A5 VCC GND 2B5 2B6
H 2A8 2A7 2A11 2B11 2B7 2B8
J 2A10 2A9 2A12 2B12 2B9 2B10

Truth Table
Inputs Inputs/Outputs
OE1 OE2 1A, 1B 2A, 2B
L L 1A = 1B 2A = 2B
L H 1A = 1B Z
Pin Assignment for FBGA H L Z 2A = 2B
H H Z Z

TOP VIEW

www.fairchildsemi.com 2
FST16211
Absolute Maximum Ratings(Note 2) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V Conditions (Note 5)
DC Switch Voltage (VS) (Note 3) −0.5V to +7.0V Power Supply Operating (VCC) 4.0V to 5.5V
DC Input Voltage (VIN) (Note 4) −0.5V to +7.0V Input Voltage (VIN) 0V to 5.5V
DC Input Diode Current (lIK) VIN<0V −50mA Output Voltage (VOUT) 0V to 5.5V
DC Output (IOUT) Sink Current 128mA Input Rise and Fall Time (tr, tf)
DC VCC/GND Current (ICC/IGND) +/− 100mA Switch Control Input 0nS/V to 5nS/V
Storage Temperature Range (TSTG) −65°C to +150 °C Switch I/O 0nS/V to DC
Free Air Operating Temperature (TA) -40 °C to +85 °C
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 3: VS is the voltage observed/applied at either A or B Ports across the
switch.
Note 4: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 5: Unused control inputs must be held HIGH or LOW. They may not
float.

DC Electrical Characteristics
TA = −40 °C to +85 °C
VCC
Symbol Parameter Min Typ Max Units Conditions
(V)
(Note 6)
VIK Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA
VIH HIGH Level Input Voltage 4.0–5.5 2.0 V
VIL LOW Level Input Voltage 4.0–5.5 0.8 V
II Input Leakage Current 5.5 ±1.0 µA 0 ≤ VIN ≤ 5.5V
0 10 µA VIN = 5.5V
IOZ OFF-STATE Leakage Current 5.5 ±1.0 µA 0 ≤ A, B ≤ VCC
RON Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64mA
(Note 7) 4.5 4 7 Ω VIN = 0V, IIN = 30mA
4.5 8 12 Ω VIN = 2.4V, IIN = 15mA
4.0 11 20 Ω VIN = 2.4V, IIN = 15mA
ICC Quiescent Supply Current 5.5 3 µA VIN = VCC or GND, IOUT = 0
∆ ICC Increase in ICC per Input 5.5 2.5 mA One input at 3.4V
Other inputs at VCC or GND
Note 6: Typical values are at VCC = 5.0V and TA = +25°C
Note 7: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.

3 www.fairchildsemi.com
FST16211
AC Electrical Characteristics
TA = −40 °C to +85 °C,
CL = 50pF, RU = RD = 500Ω Figure
Symbol Parameter Units Conditions
VCC = 4.5 – 5.5V VCC = 4.0V No.

Min Max Min Max


tPHL,tPLH Prop Delay Bus to Bus (Note 8) 0.25 0.25 ns VI = OPEN Figures
1, 2
tPZH, tPZL Output Enable Time 1.5 6.0 6.5 ns VI = 7V for tPZL Figures
1, 2
VI = OPEN for tPZH
tPHZ, tPLZ Output Disable Time 1.5 7.0 7.2 ns VI = 7V for tPLZ Figures
1, 2
VI = OPEN for tPHZ
Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).

Capacitance (Note 9)
Symbol Parameter Typ Max Units Conditions
CIN Control Pin Input Capacitance 3 pF VCC = 5.0V

CI/O Input/Output Capacitance 6 pF VCC, OE = 5.0V


Note 9: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.

AC Loading and Waveforms

Note: Input driven by 50 Ω source terminated in 50 Ω


Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz, tW = 500 ns

FIGURE 1. AC Test Circuit

FIGURE 2. AC Waveforms

www.fairchildsemi.com 4
FST16211
Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide
Package Number BGA54A
Preliminary

5 www.fairchildsemi.com
FST16211
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A

www.fairchildsemi.com 6
FST16211
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56

Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.

7 www.fairchildsemi.com
FST16211 24-Bit Bus Switch

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

8 www.fairchildsemi.com

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