Embedded System
Embedded System
3.4. Monitoring
1. Almost all ES products coming under the medical domain are with monitoring functions only.
2. Medical devices usually determine the state of some variables using sensors then display it.
3. In medical devices They cannot impose control over variables.
4. Example: Electrocardiogram (ECG), digital multimeters, logic analyzers, digital CRO.
3.5. Control
1. Embedded systems with control functionalities impose control over some variables according
to the changes in input variables. A system with control functionality contains both sensors
and actuators.
2. The air conditioner system used in our home to control the room temperature to a specified
limit is a typical example of embedded system for control purpose.
Keyboards, push button switches, etc. are examples for common user interface
input devices whereas LEDs, liquid crystal displays, piezoelectric buzzers, etc. are
examples for common user interface output devices for a typical embedded system.
7. CORE OF EMBEDDED SYSTEM
Embedded systems are domain and application specific and are built around a
central core. The core of the embedded system falls into any one of the following
categories:
IMPORTANT TABLES
Microprocessor Microcontroller
A silicon chip representing a central A microcontroller is a highly integrated chip that
processing unit (CPU), which can contains a CPU, scratchpad RAM, special and
perform arithmetic as well as logical general-purpose register arrays, on chip
operations according to a predefined set ROM/FLASH memory for program storage, timer
of instructions and interrupt control units and dedicated I/O ports
It is a dependent unit. It requires the It is a self-contained unit, and it doesn’t require
combination of other chips like timers, external interrupt controller, timer, UART, etc. for its
program and data memory chips, functioning
interrupt controllers, etc. for functioning
Most of the time general purpose in Mostly application-oriented or domain-specific
design and operation
Doesn’t contain a built in I/O port. The Most of the processors contain multiple built-in I/O
I/O port functionality needs to be ports which can be operated as a single 8 or 16- or
implemented with the help of external 32-bit port or as individual port pins
programmable peripheral interface
chips like 8255
Targeted for high end market where Targeted for embedded market where performance
performance is important is not so critical (At present this demarcation is
invalid)
Limited power saving options compared Includes lot of power saving features compared to
to Microcontroller microprocessor
RISC CISC
Lesser number of instructions Greater number of Instructions
Instruction pipelining and Generally, no instruction pipelining feature
increased execution speed
Orthogonal instruction set Non-orthogonal instruction set (All instructions are not
(Allows each instruction to allowed to operate on any register and use any addressing
operate on any register and use mode. It is instruction-specific)
any addressing
Operations are performed on Operations are performed on registers or memory
registers only; the only memory depending on the instruction
operations are load and store
Many registers are available Limited number of general-purpose registers
Programmer needs to write Instructions are like macros in C language. A programmer
more code to execute a task can achieve the desired functionality with a single
since the instructions are simpler instruction which in turn provides the effect of using more
ones simpler single instructions in RISC
Single, fixed length instructions Variable length instructions
Less silicon usage and pin count More silicon usage since more additional decoder logic is
required to implement the complex instruction decoding.
With Harvard Architecture Can be Harvard or Von-Neumann Architecture
3) Why RISC?
• Instructions are of the same size, that is, 32 bits.
• Simple but powerful instructions
• Instructions are executed in one cycle.
• Only the load and store instructions access memory
These features are fundamental to the RISC design philosophy, which prioritizes simplicity,
efficiency, and performance. ARM processors, based on RISC principles, leverage these
features to deliver high-performance computing solutions across a wide range
of applications.
4) Naming ARM
5) Popular ARM architectures
- ARM7TDMI
o 3 pipeline stages (fetch/decode/execute)
o High code density/low power consumption
o One of the most used ARM-version (for low-end systems)
o All ARM cores after ARM7TDMI include TDMI even if they do not include TDMI in
their labels.
- ARM9TDMI
o Compatible with ARM7
o 5 stages (fetch/decode/execute/memory/write)
o Separate instruction and data cache
- ARM11
7) Advanced Features
- Thumb: A new 16-bit instruction set called ‘Thumb’ was made available. The logic of
having this less powerful instruction set is that all applications do not need the full power
of 32-bit ARM instructions.
- MMU and MPU: These are two aspects related to memory. One is the ‘memory
management unit’ and the other is the ‘memory protection unit’.
- Cache: The first ARM processor with a cache was ARM3. It had an on-chip cache of 4 KB.
ARM 7 had a cache of 8 KB which was improved in ways other than just the size. Current
ARM processors have a cache as a standard component.
- Debug interface: There is an on-chip unit for testing called the JTAG interface. JTAG stands
for ‘Joint Test Action Group’ and defines a set of standards for testing the functionality of
hardware.
- Fast multiplier: Even though ARM is a RISC processor, many features in it do not conform
exactly to the RISC philosophy. Having dedicated hardware for complex operations is one
such deviation. Multiplication is a complex operation, and for fast multiplication, there
may be a fast multiplier unit.
- Enhanced instructions: Most advanced embedded systems require DSP operations, and
for that, a DSP unit with complex arithmetic operations, may be made available on the
chip.
- Vector floating point unit: This implies hardware support for floating point computation.
8) The Features of ARM Which Makes It ‘Special’
- Data bus width, the processor has a 32-bit data bus width,
- Low power
- Multiple register instructions
- Pipelining:
o Pipelining is a fundamental idea in computer architecture, for increasing the speed
of operation.
o The idea is to get many activities to be done in tandem, by dividing the whole
instruction processing stage into substages. The basic task that any processor does
is ‘fetch, decode and execute’. In the simplest form of pipelining (3 stages), all
three stages are active all the time.
9) ARM Architecture
- Operating Modes:
i) User: Unprivileged mode under which most tasks
run
ii) FIQ (Fast Interrupt Request): Entered on a high-
priority (fast) interrupt request
iii) IRQ (Interrupt Request): Entered on a low-priority
interrupt request
iv) Supervisor: Entered on reset and when a software
interrupt instruction (SWI) is executed
v) Abort: Used to handle memory access violations
vi) Undef: Used to handle undefined instructions
vii) System: Privileged mode using the same registers
as user mode
- Register Set:
ARM has 37 registers each of which is 32 bits long. They are listed as follows:
i) 1 dedicated program counter (PC)
o Store the address of the instruction to be executed.
o The last 2-bits of pc are undefined.
ii) 1 dedicated current program status register (CPSR)
o The CPSR (Current Program Status Register) is a very important register, and there
is only one such register for the processor.
o The CPSR contains information about the current state of the processor.
o It has bits that specify the mode, control bits to enable/disable interrupts, and
specifies whether the Thumb or ARM mode is currently in use.