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Dataflow Modelling

The document discusses dataflow modeling in Verilog. It explains the basic concepts like continuous assignments, implicit declarations, different types of delays that can be specified. It also provides examples of modeling combinational logic like an adder, decoder, mux using dataflow style.

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chikku0211
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17 views

Dataflow Modelling

The document discusses dataflow modeling in Verilog. It explains the basic concepts like continuous assignments, implicit declarations, different types of delays that can be specified. It also provides examples of modeling combinational logic like an adder, decoder, mux using dataflow style.

Uploaded by

chikku0211
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Dataflow Modeling

Why Dataflow ?
Any digital system
• Interconnecting registers
• Combinational logic circuits

Dataflow modeling style is mainly used to describe


combinational circuits.

The basic mechanism used is the continuous


assignment.
‘assign’ statement
The assign statement is used to make continuous assignment in the dataflow
modeling.
assign out = in1 + in2; // in1 + in2 is evaluated and then assigned to out.
Note:
• The LHS of assign statement must always be a scalar or vector net or a
concatenation. It cannot be a register.
‘assign’ statement
Note:

• Continuous statements are always active statements - The RHS


expression is evaluated whenever one of its operands changes. The
result is assigned to the LHS.

• Registers or nets or function calls can come in the RHS of the


assignment.

• Delays can be specified.


Basic Statements
Continuous assignments Variations

• Net declaration assignments


• Implicit net declarations
Implicit Continuous Assignment
• There can be only one implicit declaration assignment per net because a
net is declared only once.
Implicit net declaration
• If a signal name is used to the left of the continuous assignment, an
implicit net declaration will be inferred for that signal name.
• If the net is connected to a module port, the width of the inferred net is
equal to the width of the module port.
Continuous Assignments
Syntax
assign [delay] net1_lvalue = expr1;
assign
..., [delay] net2_lvalue = expr2;

assign [delay] netn_lvalue = exprn;

assign [delay] net1_lvalue = expr1,


[delay] net2_lvalue = expr2,
...,
[delay] netn_lvalue = exprn;
Expressions
Expression = Operators and Operands

• Operators
• Operands
Operators
Bitwise operators
Logical operators

Logical operators: If any operand bi


is x or z, it is equivalent to x
(ambiguous condition) and is
normally treated by simulators as a
false condition.
Case Equalities
Relational operators

• Relational operators are greater-than (>), less-than (<), greater-than-or-equal-to


(>=), and less-than-or-equal-to (<=).
• If relational operators are used in an expression, the expression returns a logical
value of 1 if the expression is true and 0 if the expression is false.
• If there are any unknown or z bits in the operands, the expression takes a value x.
Reduction operators
Concatenation operator

Replication operator
Conditional operators
Operands
• constants
• parameters
•• variables
nets (reg, integer, time, real, realtime)
• bit-select
part-sel
•
• function calls
• array element
Three Ways of Specifying Delays
Regular assignment delay
Implicit continuous assignment delay
Net declaration delay
Regular Assignment Delays
The inertial delay model is defaulted

wire in1, in2, out;


assign #10 out = in1 & in2;

If in1 or in2 changes value again before 10time units when the result
propagates to out, the values of in1 and in2 at the time of recomputation
are considered. This property is called inertial delay. It is useful in order
to ignore input glitches whose duration is less than the port delay.

Inertial delays also apply to gate delays.


Regular Assignment Delays
Implicit Continuous Assignment Delays
Can use an implicit continuous assignment to specify both a delay
and an assignment on the net.
Net Declaration Delays
A delay can be specified on a net when it is declared without
putting a continuous assignment on the net. If a delay is specified
on a net out, then any value change applied to the net out is
delayed accordingly.

Net declaration delays can also be used in gate-level modeling


Net Declaration Delays
Associate a delay value with a net declaration
// net delays
wire #10 out;
assign out = in1 & in2;
// regular assignment delay
wire out;
assign #10 out = in1 & in2;
module df (in1, in2, out1,out2,
out3,out1d,out2d, out3d);
input in1, in2;
output out1, out2, out3; module df_tb;
output out1d, out2d, out3d; reg in1, in2;
wire out1, out2, out3;
assign out1 = in1 & in2; wire out1d, out2d, out3d;

wire w2 = in1 & in2; df uut (in1, in2, out1,out2,


assign out2 = w2; out3,out1d,out2d, out3d);

assign w3 = in1 & in2; initial


assign out3 = w3; begin

assign #10 out1d = in1 & in2; in1 = 1’b0; in2 = 1’b0;
#10 in1 = 1’b0; in2 = 1’b0;
//Implicit Continuous Assignment Delays #10 in1 = 1’b0; in2 = 1’b0;
wire #10 w3d = in1 & in2; #10 in1 = 1’b0; in2 = 1’b0;
assign out3d = w3d;
end
wire #10 w2d; //net declaration delay
assign w2d = in1 & in2; endmodule
assign out2d = w2d;
Assignment
1) Write a verilog dataflow code for the logic diagram and verify the result

2) 4 Bit Carry Look Ahead Adder


3) Decoder 3:8
4) 4:1 Mux
5) Code Converters
1) Binary to Gray(3 bit)
2) Gray to Binary(3 bit)

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