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Ehb322e 2016 Spring Final

The document discusses digital electronic circuits and provides examples of CMOS logic circuits and their analysis. It includes questions about CMOS inverters, NAND gates, dynamic logic circuits, ROM implementations, and characteristics of different memory technologies.

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m.esadakras
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15 views2 pages

Ehb322e 2016 Spring Final

The document discusses digital electronic circuits and provides examples of CMOS logic circuits and their analysis. It includes questions about CMOS inverters, NAND gates, dynamic logic circuits, ROM implementations, and characteristics of different memory technologies.

Uploaded by

m.esadakras
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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25.05.

2016
DIGITAL ELECTRONIC CIRCUITS
Final Exam
Closed notes and books.
Duration: 120 minutes.

1. For a CMOS process, VDD= 5 V, nCox=60 A/V2, pCox=20 A/V2, VTN=0.6 V, VTP= -0.6 V, Lmin=
0.35 m are given.
a) Sketch the standard CMOS circuit which realizes the function Z=(AB+C)’+(D+E+F)’.
b) Calculate WP /WN ratio for all transistors so that τPLH /τPHL=3 for the worst case conditions (MN=MP=M
since VTN= -VTP ).
c) Using the ratio found in b), find the switching threshold VTH if all inputs switch simultaneously.
d) Sketch the circuit that realizes the same function using pseudo-NMOS logic. Calculate VOL by using
the ratio found in b). Justify the results.

2. Consider a circuit shown below. Suppose that all NMOS transistors are identical and all PMOS
transistors are identical. Equivalent resistor for an NMOS transistor: RN= 4kΩ. Equivalent resistor for a
PMOS transistor: RP= 12kΩ. Suppose that each circuit node (including outputs) has a capacitance value of
1pF.
a) Derive a Boolean expression for the output Cout in terms of the inputs X, Y, and Cin.
b) If X=1→0, Y=1, and Cin=1, calculate the propagation delay (tPLH or tPHL) at the output.

3.
a) Implement logic functions Y=[ABC+D(E+F)]’ and Z=G’Y’ using a dynamic 2-level circuits.
b) Implement the functions in a) using domino logic and sketch them.
c) For input assignments of ABCDEFG=1111111, explain how the implemented circuit in a) works when
CLK=0 and CLK=1.

4. W0
A0 A0 A1 Y0 Y1 Y2 Y3
2-to-4 LINE W1 NMOS
0 0 0 0 0 1
DECODER W2 NAND
A1 0 1 1 1 0 1
W3 MEMORY
1 0 0 0 1 1
1 1 0 1 1 0

Y0 Y1 Y2 Y3
Suppose that the above structure is a pseudo-NMOS NAND type read-only-memory (ROM) with 4 word-
lines W0-W3 and 4 bit-lines Y0-Y3. Sketch circuit implementations of the decoder and the memory.

5. Answer the following questions shortly.


a) Explain the storage capacity of dynamic memories.
b) State the differences between EPROM and E2PROM.
c) State the differences between RAM and E 2PROM.
d) State the problem if an NMOS pass transistor logic circuit drives a static CMOS circuit/gate.
e) Why is the supply voltage decreased with the emerge of new technologies?

N
VDD  VT P  VT N
P
Vth 
N
1
P
CL 1  2VT N 3V  4VT N 
TPHL    ln DD 
 N VDD  VT N  VDD  VT N VDD 
CL 1   2VTP 3V  4VTP 
TPLH    ln DD 
 P VDD  VTP  VDD  VTP VDD 

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