Ho Chi Minh City University of Technology

FACULTY OF COMPUTER SCIENCE & ENGINEERING

Laboratory Manual
Digital Systems
Experiment 4

Ho Chi Minh City, 11/2020

 Digital Systems – Lab 4

1. INTRODUCTION

1.1 Goals:
 Learn to build and use binary arithmetic circuits.
 Understand the design procedure of Asynchronous Counter.
 Design and implement basic Arithmetic circuits and Asynchronous Counters.

1.2 Equipment and apparatus:

 Digital System KIT
 Lab tools: VOM, Oscilloscope
 74-Series Integrated Circuits (IC): new type!! 7483

1.3 References:
 Digital Systems: Principles and Applications (11th Edition) – Ronald J. Tocci, Neal S.
Widmer, Gregory L. Moss, 2010.
 Lecture Slides/Videos – Assoc. Prof. Dr. Tran Ngoc Thinh.

1.4 Pre-laboratory:
 Read this experiment carefully to become familiar with the procedural steps in this
experiment.

1.5 Safety First

 You are dealing with live power. Be mindful of the current and voltage you are supplying
to the circuit. No drinks on the working surface!

1.6 Submit your reports:

 Complete all exercises in Section 2.3. Show all of your work step-by-step.
 Capture and include images about your implemented circuits in Logisim, KIT, and Tools
 Submit report to BKeL by deadline.

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2. EXPERIMENTAL PROCEDURE:

2.1 Binary Arithmetic Circuits – Adder

Adder is a combinational circuit that is used for many applications in digital electronics like
address decoding, table index calculation, etc. Typically, the main function of adders is to add
binary numbers or other formats (e.g. BCD) together, thereby producing sum bits (denoted by
S) and carry bits (denoted by C) as the output. There are two basic types of Adder circuits:
Half adder and Full adder.
2.1.1 The Half Adder
Half adder is a combinational arithmetic circuit that adds two 1-bit numbers and produces a
sum bit (S) and a carry bit (C) as the output. The truth table, schematic representation and
logic circuit of a half adder are shown in the figure below.

Figure 1: The Half Adder

One major disadvantage of the Half Adder circuit when used as a binary adder, is that there is
no provision for a “Carry-in” from the previous circuit when adding together multiple data
bits. To overcome this problem, we use a Full Adder type binary adder circuit.
2.1.2 The Full Adder
Full adder is a combinational arithmetic circuit that performs an addition operation on three
1-bit binary numbers and generates a sum bit (S) and a carry bit (C) as the output. (The main
difference between the Full Adder and the Half Adder is that a full adder has a Carry-in

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 Digital Systems – Lab 4

input). The truth table, schematic representation and logic circuit of a full adder are shown in
the figure below.

Figure 2: The Full Adder

In many ways, the full adder can be thought of as two half adders connected together, with
the first half adder passing its carry to the second half adder as shown in Figure 3.

Figure 3: Full Adder from the Half Adders

2.1.3 n-bit Binary Adder

If we wanted to add together two n-bit numbers, then n number of 1-bit full adders need to be
connected or “cascaded” together to produce what is known as a Ripple Carry Adder.

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 Digital Systems – Lab 4

Figure 4: Full Adder from the Half Adders

Figure 4 shows a 4-bit Ripple Carry Adder. Suppose we want to “add” together two 4-bit
numbers, the two outputs of the first full adder will provide the first place digit sum (S) of the
addition plus a carry-out bit that acts as the carry-in digit of the next binary adder.

IC 7483
4-bit full adder circuits are available as standard IC packages in the form of the TTL 4-bit
binary adder 74LS83 which can add together two 4-bit binary numbers and generate a SUM
and a CARRY output as shown.

Figure 5: Logic Symbol and Pin diagram of IC 7483

Be Careful: In IC 7483, PIN 5 is the VCC and PIN 12 is the GND!

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 Digital Systems – Lab 4

2.2 Counter
Counters are very widely used in almost all computers and other digital electronic systems.
A counter is a sequential logic circuit that goes through a prescribed sequence of states upon
the application of input pulses. For example,
 The circuit that moves through the states 0, 1, 2, 3, 4, 5, 6 (then gets back to 0) is called a counter
 The circuit that constantly moves through the following same order of state transfers 1, 0, 2, 5, 7
then gets back to 1 is also a counter (it is often accepted that a counter restarts when it reaches the
final number).

A Binary Counter is a hardware circuit that is made out of a series of flip-flops. It goes through
2N (N is the number of flip-flops in the series) states.

Modulus Counters (MOD counters), are defined based on the number of states that the
counter will sequence through before getting back to its original value. For example,
 A 2-bit counter that counts from 002 to 112 in binary, that is 0 to 3 in decimal, has a modulus
value of 4 ( 00 → 1 → 10 → 11, and return back to 00 ) so would therefore be called a modulo-4,
or mod-4, counter.

Two major types of counters: Asynchronous Counters and Synchronous Counters.

Figure 6: Example of Asynchronous Counter

Figure 7: Example of Synchronous Counter

In this experiment, we will study on how to design and implement an asynchronous counter.

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2.2.1 Asynchronous Counter (Ripple Counter)

The counter in which external clock is only given to the first Flip-flop & the succeeding Flip-
flops are clocked by the output of the preceding flip-flop is called asynchronous counter or
ripple counter. Figure 6 shows an example of Asynchronous Counter.
There are some types of asynchronous counter:
 Up counters  Decade counter
 Down counters  Ring counter
 Up-down counters  Johnson counter

Step to design an asynchronous counter:

1. Determine the type of asynchronous counter based on the counting sequence:

E.g., Up counter, Down counter, Up/Down counter, etc.
Full sequence counter or modulus counter

Determine the type of Flip-Flop and clock trigger

E.g., D Flip-flop, J-K Flip-flop, T Flip-flop, etc.
Positive Edge Trigger or Negative Edge Trigger

2. Determine the number of Flip-flops needed to support the number of states in the
counting sequence.
An asynchronous counter with n flip-flops can count 2𝑛 − 1 possible states.
2𝑛 − 1 ≥ 𝑡ℎ𝑒 # 𝑜𝑓 𝑠𝑡𝑎𝑡𝑒𝑠
E.g. to design a MOD-6 counter of which the total number of state is 6 (0002  1012 and getting
back to 0002), we have to design a circuit with at least 3 FFs

3. Determine the reset state if we intend to build a modulus counter

E.g., In the MOD-6 counter, once the counter reaches the count 5 (1012), we want it to go back to
0 (0002) instead of continuing on to 6 (1102). Therefore, we need to design a combinational circuit
to reset back to 0002 after a count of 1012, and 1102 is now determined as the reset state.

We can decode this output state of 1102 (6) to give us a signal to clear (CLR) the counter back to
zero with the help of AND gates and NOT gates.

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4. Design the asynchronous counter circuit

Based on the type of counter, flip-flop and clock trigger, we have some common design rules:
- Asynchronous counters often use Flip-flops connected in Toggle mode.
- Clock pulses are fed into the CLK input of the first Flip-flop, while the CLK input of the next
flip-flop are triggered by the output of the preceding flip-flop.
- Assume that output sequence of the counter is retrieved from the Q signal of FFs

Negative Edge Triggered FFs Positive Edge Triggered FFs:

Connect Q signal of the previous Connect Q’ signal of the previous to

Up
to the CLK signal of the next the CLK signal of the next
Counter
Connect Q’ output of the previous Connect Q output of the previous to
Down
to the CLK input of the next the CLK input of the next
Counter

- Connect the output of reset circuit to the CLR or PRE signal of FFs

Figure 7: The MOD-6 Asynchronous Up Counter using PGT D Flip-flop

2.3 Exercise

2.3.1 Design and simulate a Full Adder built from Half Adders in Logisim.
2.3.2 Design, simulate and implement a 4-bit Ripple Carry Adder using IC 7483
2.3.3 Design, simulate and implement a MOD-10 Asynchronous UP Counter using J-K Flip-
flops (IC 7473).

Homework: (To prepare for the next experiment)

2.3.4 What is the difference between asynchronous and synchronous counter?

2.3.5 What is the procedure to design a synchronous counter?