AD9576

Dual PLL,
Asynchronous Clock Generator

Data Sheet AD9576
FEATURES FUNCTIONAL BLOCK DIAGRAM
Single, low phase noise, fully integrated VCO/fractional-N
PLL core SPI/I2C STATUS
VCO range: 2375 MHz to 2725 MHz OPTIONAL
AND PPRx
CONTROL
MONITOR
Integrated loop filter (requires a single external capacitor) REF2

GENERAL- DIV OUT10
2 differential, XTAL, or single-ended reference inputs
MUX
REF2 PURPOSE
PLL OUT9
Reference monitoring capability DIV
OUT8
Automatic redundant XTAL switchover
OUT0
Minimal transient, smooth switching OUT1
OPTIONAL DIV
Typical RMS jitter REF0
OUT2
OUT3
<0.3 ps (12 kHz to 20 MHz), integer-N translations
AND MONITOR
FRACTIONAL-N
SWITCHOVER
REF0 VCO OUT4
<0.5 ps (12 kHz to 20 MHz), fractional-N translations DIV DIV
OUT5
PLL
OPTIONAL
Input frequency REF1 OUT6
VCO
8 kHz, 1.544 MHz, 2.048 MHz, and 10 MHz to 325 MHz DIV
DIV
OUT7
REF1
Preset frequency translations via pin strapping (PPRx)
13993-001
AD9576
Using a 25 MHz input reference
24.576 MHz, 25 MHz, 33.33 MHz, 50 MHz, 70.656 MHz, Figure 1.
100 MHz, 125 MHz, 148.5 MHz, 156.25 MHz,
161.1328 MHz, 312.5 MHz, 322.2656 MHz, 625 MHz, GENERAL DESCRIPTION
or 644.5313 MHz The AD9576 provides a multiple output clock generator
Using a 19.44 MHz input reference function comprising two dedicated phase-locked loop (PLL)
50 MHz, 100 MHz, 125 MHz, 156.25 MHz, 161.1328 MHz, cores with flexible frequency translation capability, optimized to
or 644.5313 MHz serve as a robust source of asynchronous clocks for an entire
Using a 30.72 MHz input reference system, providing extended operating life within frequency
25 MHz, 50 MHz, 100 MHz, 125 MHz, or 156.25 MHz tolerance through monitoring of and automatic switchover
Single, general-purpose, fully integrated VCO/integer-N between redundant crystal (XTAL) inputs with minimized
PLL core switching, induced transients. The fractional-N PLL design is
VCO range: 750 MHz to 825 MHz based on the Analog Devices, Inc., proven portfolio of high
Integrated loop filter performance, low jitter frequency synthesizers to maximize
Independent, duplicate reference input or operation from network performance, whereas the integer-N PLL provides
the fractional-N PLL active reference input general-purpose clocks for use as CPU and field-programmable
Input frequency: 25 MHz gate array (FPGA) reference clocks.
Preset frequency translations via pin strapping (PPRx)
The AD9576 uses pin strapping to select among a multitude of
25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 100 MHz,
power-on ready configurations for its 11 output clocks, which
133.33 MHz, 200 MHz, or 400 MHz
require only the connection of external pull-up or pull-down
Up to 3 copies of reference clock output
resistors to the appropriate pin program reader pins (PPRx).
11 pairs of configurable differential outputs
These pins provide control of the internal dividers for establishing
Output drive formats
the desired frequency translations, clock output functionality,
3 outputs: HSTL, LVDS, HCSL, 1.8 V CMOS, 2.5 V/3.3 V CMOS
and input reference functionality. These parameters can also be
8 outputs: HSTL, LVDS, or 1.8 V CMOS
manually configured through a serial port interface (SPI).
2.5 V or 3.3 V single-supply operation
The AD9576 is packaged in a 64-lead, 9 mm × 9 mm LFCSP,
APPLICATIONS requiring only a single 2.5 V or 3.3 V supply. The operating
Ethernet line cards, switches, and routers temperature range is −40°C to +85°C.
Baseband units
SATA and PCI express Each OUTx output is differential and contains two pins: OUTx
Low jitter, low phase noise clock generation and OUTx. For simplicity, the term OUTx refers to the
Asynchronous clock generation functional output block containing these two pins.
Rev. A Document Feedback

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AD9576 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 PLL0 Integer-N/Fractional-N PLL ........................................... 29
Applications ....................................................................................... 1 PLL1 Integer-N PLL ................................................................... 35
Functional Block Diagram .............................................................. 1 Output Distribution ................................................................... 36
General Description ......................................................................... 1 PPRx Pins .................................................................................... 38
Revision History ............................................................................... 3 Power-On Reset (POR) ............................................................. 41
Specifications..................................................................................... 4 Serial Control Port ......................................................................... 42
Conditions ..................................................................................... 4 SPI/I²C Port Selection................................................................ 42
Supply Current Specifications..................................................... 4 SPI Serial Port Operation .......................................................... 42
Power Dissipation Specifications ............................................... 5 I2C Serial Port Operation .......................................................... 44
Reference Inputs ........................................................................... 6 Control Register Map ..................................................................... 48
Reference Switchover Output Disturbance Specifications...... 6 Control Register Descriptions ...................................................... 51
PLL0 Characteristics .................................................................... 7 Serial Port Configuration Registers (Register 0x000 to
PLL1 Characteristics .................................................................... 7 Register 0x00F) ........................................................................... 51
Clock Distribution Outputs Specifications ............................... 7 Status Indicator Registers (Register 0x020 to Register 0x021) .. 52
Output Alignment and Startup Specifications ....................... 10 Chip Mode Register (Register 0x040) ..................................... 52
PLL0 Channels Absolute Clock Jitter Specifications ............. 11 Reference Input Configuration Registers (Register 0x080 to
Register 0x081) ........................................................................... 53
PLL1 and Bypass Channel Absolute Clock Jitter
Specifications .............................................................................. 13 Reference Switchover Registers (Register 0x082 to
Register 0x083) ........................................................................... 54
OUT8 to OUT10 Channel Cycle to Cycle Clock Jitter
Specifications .............................................................................. 13 PLL0 Configuration Registers (Register 0x100 to
Register 0x111) ........................................................................... 55
Logic Input Pins Characteristics—REF_SEL, RESET, SPx,
PLL0 VCO Dividers Registers (Register 0x120 to
PPRx ............................................................................................. 14
Register 0x122) ........................................................................... 57
Status Output Pins Characteristics—LD_0, LD_1, REF_SW,
PLL0 Distribution Registers (Register 0x140 to
REF_STATUS, REF_ACT ......................................................... 14
Register 0x14D) .......................................................................... 58
Serial Control Port Specifications ............................................ 15
PLL1 Configuration Registers (Register 0x200 to
Absolute Maximum Ratings.......................................................... 17 Register 0x202) ........................................................................... 60
Thermal Resistance .................................................................... 17 PLL1 Distribution Registers (Register 0x240 to
ESD Caution ................................................................................ 17 Register 0x246) ........................................................................... 60
Pin Configuration and Function Descriptions ........................... 18 Applications Information .............................................................. 63
Typical Performance Characteristics ........................................... 22 Interfacing to CMOS Clock Outputs ....................................... 63
Phase Noise and Voltage Waveforms ....................................... 22 Interfacing to LVDS and HSTL Clock Outputs ..................... 63
Reference Switching Frequency and Phase Disturbance ...... 24 Interfacing to HCSL Clock Outputs ........................................ 63
Terminology .................................................................................... 25 Power Supply............................................................................... 64
Theory of Operation ...................................................................... 26 Power and Grounding Considerations and Power Supply
Rejection ...................................................................................... 64
Overview...................................................................................... 26
Outline Dimensions ....................................................................... 65
Reference Inputs ......................................................................... 26
Ordering Guide .......................................................................... 65
Reference Monitor ...................................................................... 27
Reference Switching ................................................................... 28
Rev. A | Page 2 of 65
Data Sheet AD9576
REVISION HISTORY
9/2018—Rev. 0 to Rev. A
Change to Table 47, Address 0x103, Bits[5:3], Reset Column.....55
Updated Outline Dimensions ........................................................65
7/2016—Revision 0: Initial Version
AD9576 Data Sheet
SPECIFICATIONS
Typical values are given for VDD_x = 2.5 V, TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD_x
and TA (−40°C to +85°C) range.
VDD_x and VDD_x refer to the following pins, and to the voltage on any of the following pins, respectively: VDD_REFMON, VDD_REF0,
VDD_REF1, VDD_IO, VDD_PLL0, VDD_VCO0, VDD_M0, VDD_M1, VDD_OUT67, VDD_OUT45, VDD_OUT23, VDD_OUT01,
VDD_OUT89, VDD_OUT10, VDD_VCO1, VDD_PLL1, and VDD_REF2.
Note that throughout this data sheet, multifunction pins, such as SCLK/SCL, are referred to either by the entire pin name or by a single
function of the pin, for example, SCLK, when only that function is relevant.
CONDITIONS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY Applies to all VDD_x pins; 2.5 V and 3.3 V nominal supplies are supported on all
VOLTAGE specifications, unless otherwise noted
(VDD_x)
2.38 2.63 V 2.5 V ± 5%
2.97 3.63 V 3.3 V ± 10%
SUPPLY CURRENT SPECIFICATIONS

Table 2.
SUPPLIES OTHER THAN CLOCK All blocks running (excludes clock distribution section); REF0
OUTPUT DRIVERS (differential) and REF1 (differential) at 300 MHz; PLL0 locked at
2500 MHz with a 100 MHz phase frequency detector (PFD) rate;
Divider M0 set to 2 and Divider M1 disabled; REF2 (XTAL) at
25 MHz, configured as PLL1 input; PLL1 locked to 800 MHz with
input doubler enabled
VDD_REFMON and VDD_REFx 35.6 39.2 mA Cumulative current draw from all listed supply pins
(Pin 4, Pin 9, Pin 10, and
Pin 64)
VDD_IO and VDD_PLL0 (Pin 16 26.5 29.5 mA Cumulative current draw from all listed supply pins
and Pin 18)
VDD_VCO0 (Pin 21) 33.8 36.9 mA
VDD_Mx (Pin 23 and Pin 25) 81.0 88.7 mA Cumulative current draw from all listed supply pins
VDD_VCO1 (Pin 60) 19.2 21.8 mA
VDD_PLL1 (Pin 61) 20.4 23.7 mA
SUPPLY CURRENT FOR EACH Output driver supplies power both the output driver and output
CLOCK DISTRIBUTION SUPPLY divider
High Speed Transceiver Logic
(HSTL)
VDD_OUT67 (Pin 29) 59.8 69.7 mA Output at 1250 MHz
VDD_OUT01(Pin 46) 36.4 42.6 mA Output at 625 MHz
Low Voltage Differential
Signaling (LVDS)
VDD_OUT01(Pin 46) 20.8 23.6 mA Output at 625 MHz
Data Sheet AD9576
1.8 V CMOS All outputs at 100 MHz with a 10 pF load
VDD_OUT67 (Pin 29) 27.2 34.7 mA
VDD_OUT45 (Pin 35) 27.2 34.7 mA
VDD_OUT23 (Pin 41) 28.2 31.7 mA
VDD_OUT01(Pin 46) 17.4 21.9 mA
VDD_OUT89 (Pin 52) 32.7 42.5 mA
VDD_OUT10 (Pin 57) 21.4 26.8 mA
2.5 V CMOS VDD_x set to 2.5 V, output at 100 MHz with a 10 pF load; not
available on OUT0 to OUT7
VDD_OUT89 (Pin 52) 38.5 48.8 mA
VDD_OUT10 (Pin 57) 24.4 30.1 mA
3.3 V CMOS VDD_x set to 3.3 V, all outputs at 100 MHz with a 10 pF load; not
available on OUT0 to OUT7
VDD_OUT89 (Pin 52) 48.5 60.4 mA
VDD_OUT10 (Pin 57) 29.1 36.2 mA
High Speed Current Sinking All outputs at 400 MHz; not available on OUT0 to OUT7
Logic (HCSL)
VDD_OUT89 (Pin 52) 30.7 41.4 mA
VDD_OUT10 (Pin 57) 20.8 26.6 mA
POWER DISSIPATION SPECIFICATIONS

Table 3.
POWER DISSIPATION All supplies set to 2.5 V nominal; specifications do not include power
dissipated by external terminations
Typical Configuration 1 680 1168 mW Asynchronous operation; PPR0 = State 0, PPR1 = State 0, PPR2 = State 3,
PPR3 = State 3; REF 0 and REF1 = 25 MHz XTAL, doubler enabled; OUT10 =
25 MHz CMOS; OUT0 to OUT3 = 100 MHz LVDS; OUT4 to OUT5 = 312.5 MHz
LVDS, OUT6 to OUT7 = 156.25 MHz LVDS, OUT8 to OUT9 = 125 MHz LVDS
Typical Configuration 2 619 974 mW Synchronous operation; REF0 (differential) at 100 MHz, REF1 disabled, and
REF2 (XTAL) at 25 MHz; PLL1 disabled and PLL0 locked at 2500 MHz using R
divider of 2 and PLL0 feedback divider (N0) set to 50; M0 and M1 set to
divide by 2; Output 0 set to 625 MHz HSTL; Output 1 to Output 3 disabled;
Output 4 to Output 7 set to 125 MHz LVDS; Output 8 to Output 9 set to
156.25 MHz LVDS
All Blocks Running 979 1520 mW All blocks running; REF0 (differential) and REF1 (differential) at 300 MHz;
PLL0 locked at 2500 MHz with a 100 MHz PFD rate; M0 set to 2 and enabled to
Q0, Q1, and Q2; OUT0 to OUT3 = 625 MHz LVDS; OUT4 to OUT 7 = 1250 MHz
LVDS; REF2 (XTAL) at 25 MHz, configured as PLL1 input; PLL1 locked to
800 MHz with input doubler enabled; Divider Q3 and Divider Q4 set to 2 and
OUT8 to OUT10 = 400 MHz, HCSL
Minimal Power 145 179 mW PPR0 = State 0, PPR1 = State 0, PPR2 = State 0, PPR3 = State 0
Configuration
INCREMENTAL POWER Typical configuration; values show the change in power due to the indicated
DISSIPATION operation
Input Reference On/Off Applies to one reference clock input at 25 MHz
Single-Ended 2.5 10 mW
Differential 27.5 33.7 mW
Output Driver On/Off
LVDS at 156.25 MHz 47.6 66.1 mW
HSTL at 156.25 MHz 51.3 80.8 mW
1.8 V CMOS at 64.6 74.1 mW A single 1.8 V CMOS output with a 10 pF load
100 MHz
2.5 V CMOS at 88.4 102.5 mW A single 2.5 V CMOS output with a 10 pF load
100 MHz
AD9576 Data Sheet
REFERENCE INPUTS
Table 4.
DIFFERENTIAL INPUT MODE
Input Frequency 325 MHz
Input Sensitivity 100 mV p-p
Minimum Input Slew Rate 100 V/µs Minimum limit imposed for jitter performance (when using
a sinusoidal source)
Minimum Pulse Width 1.38 ns Applies to both low and high pulses
Common-Mode Internally Generated 1.24 V
Bias Voltage
Common-Mode Voltage Tolerance 0.83 1.675 V The acceptable common-mode range for a 200 mV p-p,
dc-coupled input signal
Differential Input Capacitance 2 pF
Differential Input Resistance 4.3 kΩ
SINGLE-ENDED INPUT CMOS MODE
Input Frequency 200 MHz
Minimum Pulse Width 2 ns Applies to both low and high pulses
Hysteresis 240 mV
Input Leakage 2 nA
Input Capacitance 2 pF
Input Voltage
High 1.93 V
Low 1.04 V
CRYSTAL RESONATOR MODE Fundamental mode quartz resonator
Input Frequency
Reference of PLL0 or Buffered 19.44 30.72 MHz
Output
Reference of PLL1 25 MHz REF2
Effective Series Resistance (ESR) 80 Ω
REFERENCE SWITCHOVER OUTPUT DISTURBANCE SPECIFICATIONS

Table 5.
INSTANTANEOUS FREQUENCY (dθ/dt) 350 ppm Applies only to PLL0 outputs; 1 ppm frequency offset
DISTURBANCE DUE TO REFERENCE peak between the REF0 and REF1 channels; 400 kHz loop
SWITCHOVER bandwidth; smooth switchover enabled
INSTANTANEOUS PHASE DISTURBANCE 220 ps Applies only to the active reference of PLL0; smooth
DUE TO REFERENCE SWITCHOVER switchover enabled
Data Sheet AD9576
PLL0 CHARACTERISTICS
Table 6.
REFERENCE INPUT PATH
Input Frequency
Divider 325 MHz
Doubler 145 MHz
PHASE FREQUENCY DETECTOR (PFD)
Frequency Range
Integer Mode 290 MHz
Fractional Mode 9.4 170 MHz
Lock Detect Window ±16 ppm
INPUT FREQUENCY OF FEEDBACK DIVIDERS
N0 2725 MHz
N0A 156 MHz
QZD 1250 MHz
VOLTAGE CONTROLLED OSCILLATOR (VCO)
Frequency Range 2375 2725 MHz
Gain 64 MHz/V
VCO DIVIDER (M0 AND M1) OUTPUT FREQUENCY 1250 MHz
PLL1 CHARACTERISTICS
Table 7.
REFERENCE INPUT PATH
Input Frequency
Divider 25 MHz
Doubler 25 MHz
PFD FREQUENCY
Lock Detector Window 2 UI
VCO
Gain 750 MHz/V
CLOCK DISTRIBUTION OUTPUTS SPECIFICATIONS

Rise and fall time measurement thresholds are 20% and 80% of the nominal low and high amplitude of the waveform.
Table 8.
HSTL (OUT0 TO OUT7) 100 Ω termination (differential)
Output Frequency
OUT0 to OUT3 1000 MHz
Output Rise Time, tRL 108 136 163 ps Measured differentially; output at 100 MHz
Output Fall Time, tFL 108 136 161 ps Measured differentially; output at 100 MHz
Duty Cycle 45 55 %
Differential Output Voltage Swing 861 1080 1374 mV Magnitude of voltage across pins; output
driver static
Common-Mode Output Voltage 840 940 1034 mV Output driver static
AD9576 Data Sheet
LVDS (OUT0 TO OUT7) 100 Ω termination (differential)
Output Frequency
Duty Cycle 45 55 %
Differential Output Voltage, VOD 276 375 490 mV Magnitude of voltage across pins; output
driver static
Delta VOD 22 mV
Output Offset Voltage, VOS 1.18 1.275 1.36 V
Delta VOS 26 mV
Short-Circuit Current (ISA, ISB) 25 mA Output shorted to GND; value represents the
magnitude of current draw
1.8 V CMOS (OUT0 TO OUT7) CLOAD = 10 pF
Output Frequency 200 MHz
Output Rise Time, tRC 0.84 1.19 1.54 ns Output at 25 MHz
Output Fall Time, tFC 1.04 1.25 1.49 ns Output at 25 MHz
Duty Cycle 45 55 %
Output Voltage
High (VOH) 1.74 V ILOAD = −1 mA
Low (VOL) 0.065 V ILOAD = 1 mA
HSTL (OUT8 TO OUT10) 100 Ω termination (differential)
Duty Cycle 45 55 % Assumes 50% reference input duty cycle
driver static
LVDS (OUT8 TO OUT10) 100 Ω termination (differential)
Differential Output Voltage, VOD 276 375 490 mV Magnitude of voltage across pins; output
driver static
ΔVOD 22 mV
Output Offset Voltage, VOS 1.18 1.275 1.36 V
ΔVOS 26 mV
Short-Circuit Current (ISA, ISB) 25 mA Output shorted to GND; value represents the
magnitude of current draw
1.8 V CMOS (OUT8 TO OUT10) CLOAD = 10 pF
Output Rise Time, tRC 0.49 1.41 ns Output at 25 MHz
Output Fall Time, tFC 0.59 1.24 ns Output at 25 MHz
Output Voltage
High (VOH) 1.74 V ILOAD = −1 mA
Data Sheet AD9576
FULL SWING CMOS (OUT8 TO OUT10) CLOAD = 10 pF
Output Rise Time, tRC 0.50 1.38 ns Output at 25 MHz
Output Fall Time, tFC 0.57 1.19 ns Output at 25 MHz
Output Voltage
High (VOH) VDD_x − 0.33 V ILOAD = −10 mA
HCSL (OUT8 to OUT10) 50 Ω from each output pin to GND
Output Frequency 800
driver static
Timing Diagrams
SINGLE-ENDED
80%
CMOS
10pF LOAD
20%
13993-002
tRC tFC
Figure 2. CMOS Timing, Single-Ended, 10 pF Load
DIFFERENTIAL
80%
LVDS/HSTL/HCSL
20%
13993-003
tRL tFL
Figure 3. LVDS, HSTL, and HCSL Timing, Differential
AD9576 Data Sheet
OUTPUT ALIGNMENT AND STARTUP SPECIFICATIONS
The indicated times assume the voltage applied to all power supply pins is within specification and stable.
Table 9.
ZERO DELAY Timing delay between input clock edge on REF0 or REF1 to any
corresponding OUTx clock edge; R divider and doubler are bypassed
OUT0 to OUT7 3.44 3.87 ns
OUT8 to OUT9 3.82 4.28 ns
OUTPUT TO OUTPUT SKEW Deviation between rising edges of outputs of a similar logic type; frequency
source to distribution is the output of the M0 divider; all output drivers are
configured to the same logic type, unless otherwise noted; all output
frequencies are 25 MHz
Between Outputs that
Share a Single Qx Divider
LVDS
OUT1, OUT2, and −36 +29 ps Relative to OUT0
OUT3
OUT5 −13 +30 ps Relative to OUT4
HSTL
OUT1, OUT2, and −33 +30 ps Relative to OUT0
OUT3
Between OUT0 to OUT9
LVDS
OUT4 −141 −8 ps Relative to OUT0
OUT8 229 440 ps Relative to OUT0
HSTL
OUT4 −149 −12 ps Relative to OUT0
OUT8 271 487 ps Relative to OUT0
PROPAGATION DELAY 3.88 4.47 ns Rising edge on REF2 input to OUT8 to OUT10; 25 MHz reference input clock,
PLL1 bypassed, and Qx dividers set to 1
OUTPUT READY TIME 25 MHz reference input clocks, input doublers disabled
PLL0 8 ms Time interval from RESET pin = Logic 1 to LD_0 pin = Logic 1 (PLL0 lock
detection)
PLL1 455 µs Time interval from RESET pin = Logic 1 to LD_1 pin = Logic 1 (PLL1 lock
detection)
Data Sheet AD9576
PLL0 CHANNELS ABSOLUTE CLOCK JITTER SPECIFICATIONS
Reference input frequency source is a 25 MHz Taitien XTAL, and frequency multiplier (×2) at PLL input enabled, unless otherwise noted.
Table 10.
HSTL INTEGRATED RMS JITTER
Jitter Integration Bandwidth = 10 kHz to 10 MHz
Integer-N Translations
100 MHz Output 0.233 ps
156.25 MHz Output 0.218 ps
Fractional-N Translations
644.53125 MHz Output 0.313 ps
644.53125 MHz Output 0.314 ps
Jitter Integration Bandwidth = 1.875 MHz to 20 MHz
644.53125 MHz Output 0.096 ps
LVDS INTEGRATED RMS JITTER
644.53125 MHz Output 0.313 ps
AD9576 Data Sheet
644.53125 MHz Output 0.314 ps
644.53125 MHz Output 0.095 ps
HCSL INTEGRATED RMS JITTER OUT8 and OUT9 only
Data Sheet AD9576
PLL1 AND BYPASS CHANNEL ABSOLUTE CLOCK JITTER SPECIFICATIONS
Table 11.
HSTL INTEGRATED RMS JITTER
25 MHz Output 0.125 ps Source = 25 MHz Taitien XTAL; jitter integration bandwidth =
12 kHz to 5 MHz
100 MHz Output 1.605 ps Source = PLL1; Qx divider = 8; jitter integration bandwidth =
12 kHz to 20 MHz
12 kHz to 20 MHz
HCSL INTEGRATED RMS JITTER
12 kHz to 5 MHz
12 kHz to 20 MHz
12 kHz to 20 MHz
LVDS INTEGRATED RMS JITTER
12 kHz to 5 MHz
12 kHz to 20 MHz
12 kHz to 20 MHz
2.5 V CMOS INTEGRATED RMS JITTER
12 kHz to 5 MHz
12 kHz to 20 MHz
12 kHz to 20 MHz
OUT8 TO OUT10 CHANNEL CYCLE TO CYCLE CLOCK JITTER SPECIFICATIONS

Frequency multiplier (×2) at PLL input enabled. Cycle to cycle jitter magnitude varies with respect to the clock edge (rising or falling).
Table 12 indicates jitter for the worst edge (rising or falling). The better edge typically offers a factor of 2 improvement over the tabulated jitter.
Table 12.
LVDS CYCLE TO CYCLE JITTER Peak-to-peak jitter, 10,000 cycles
1.8 V CMOS CYCLE TO CYCLE JITTER Peak-to-peak jitter, 10,000 cycles
3.3 V CMOS CYCLE TO CYCLE JITTER Peak-to-peak jitter, 10,000 cycles
33.3 MHz Output 83 ps
AD9576 Data Sheet
LOGIC INPUT PINS CHARACTERISTICS—REF_SEL, RESET, SPx, PPRx
Table 13.
INPUT STATIC CHARACTERISTICS
REF_SEL Pin Internal 30 kΩ pull-down resistor
Logic 1 Voltage (VIH) 2.11 V
Logic 0 Voltage (VIL) 1.0 V
Logic 1 Current (IIH) 195 µA VIH = VDD_x; value represents the magnitude
of current draw
Logic 0 Current (IIL) 0.25 µA VIL = GND; value represents the magnitude
of current draw
RESET Pin Internal 30 kΩ pull-up resistor
Logic 1 Voltage (VIH) 1.9 V
Logic 1 Current (IIH) 0.04 µA VIH = VDD_x; value represents the magnitude
of current draw
Logic 0 Current (IIL) 260 µA VIL = GND; value represents the magnitude
of current draw
SPx Pins
Logic 1 Voltage (VIH) VDD_x − 0.5 V
Logic 1 Current (IIH) 95 µA VIH = VDD_x; value represents the magnitude
of current draw
Logic 0 Current (IIL) 0.04 µA VIL = GND; value represents the magnitude
of current draw
RESET TIMING
Pule Width Low 1.25 ns
RESET Inactive to Start of 1.25 ns
Register Programming
PPR0 TO PPR3 PINS EXTERNAL Maximum resistor tolerance = 10%
TERMINATION
State 0 820 Ω Pull-down to GND
State 4 820 Ω Pull-up to VDD_x
STATUS OUTPUT PINS CHARACTERISTICS—LD_0, LD_1, REF_SW, REF_STATUS, REF_ACT

Table 14.
OUTPUT CHARACTERISTICS ILOAD = 1 mA (source or sink)
Logic 1 Voltage VDD_x − 0.1 V
Logic 0 Voltage 0.03 V
Data Sheet AD9576
SERIAL CONTROL PORT SPECIFICATIONS
Serial Port Interface (SPI) Mode
Table 15.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CS (INPUT) Input pin
Input Voltage
Logic 1 VDD_x − 0.3 V
Logic 0 0.71 V
Input Current
Logic 1 −0.2 nA
Logic 0 −0.3 nA
SCLK (INPUT) IN SPI MODE
Input Voltage
Logic 0 0.71 V
Input Current
Logic 1 −0.7 nA
Logic 0 −0.6 nA
SDIO (INPUT) Pin is bidirectional
Input Voltage
Logic 0 0.71 V
Input Current
Logic 1 0.7 nA
Logic 0 −0.8 nA
SDIO (OUTPUT) Pin is bidirectional
Output Voltage
Logic 0 0.05 V
TIMING
Clock Rate (SCLK, 1/tSCLK) 50 MHz
Pulse Width High tHIGH 4 ns
Pulse Width Low tLOW 2.2 ns
SDIO to SCLK Setup tDS 2.5 ns
SCLK to SDIO Hold tDH 2.7 ns
SCLK to Valid SDIO and SDO tDV 6.44 ns
CS to SCLK Setup tS 0 ns
CS to SCLK Hold tC 0 ns
CS Minimum Pulse Width High tPWH 2.7 ns
AD9576 Data Sheet
I2C Mode
Table 16.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SDA, SCL VOLTAGE When inputting data
Input Logic 1 0.7 × VDD_x V
Input Logic 0 0.3 × VDD_x V
Input Current −10 +10 µA Input voltage between 0.1 × VDD_x and
0.9 × VDD_x
Hysteresis of Schmitt Trigger Inputs 0.015 × VDD_x V
SDA When outputting data
Output Logic 0 Voltage at 3 mA Sink 0.2 V
Current
Output Fall Time from VIHMIN to VILMAX 20 + 0.1 CB1 250 ns Bus capacitance from 10 pF to 400 pF
TIMING All I2C timing values are referred to VIHMIN
(0.3 × VDD) and VILMAX levels (0.7 × VDD)
Clock Rate (SCL, fI2C) 400 kHz
Bus Free Time Between a Stop and tBUF 1.3 µs
Start Condition
Setup Time for a Repeated Start tSU; STA 0.6 µs
Condition
Hold Time (Repeated) Start Condition tHD; STA 0.6 µs After this period, the first clock pulse is
generated
Setup Time for a Stop Condition tSU; STO 0.6 µs
Low Period of the SCL Clock tLOW 1.3 µs
High Period of the SCL Clock tHIGH 0.6 µs
SCL, SDA Rise Time tR 20 + 0.1 CB1 300 ns
SCL, SDA Fall Time tF 20 + 0.1 CB1 300 ns
Data Setup Time tSU; DAT 100 ns
Data Hold Time tHD; DAT 0 ns
Capacitive Load for Each Bus Line CB1 400 pF
1
CB is the capacitance of one bus line in picofarads (pF).
Data Sheet AD9576
ABSOLUTE MAXIMUM RATINGS

Table 17. THERMAL RESISTANCE
Parameter Rating Thermal performance is directly linked to printed circuit board
VDD_x to GND −0.3 V to +3.6 V (PCB) design and operating environment. Careful attention to
Junction Temperature1 150°C PCB thermal design is required.
Storage Temperature Range −65°C to +150°C
Table 18. Thermal Resistance
1
See Table 18 for θJA.
Package Type θJA Unit
Stresses at or above those listed under Absolute Maximum CP-64-171 22.7 °C/W
Ratings may cause permanent damage to the product. This is a 1
Thermal impedance is based on a 4-layer board in still air in accordance with
stress rating only; functional operation of the product at these a JEDEC JESD51-7 plus JEDEC JESD51-5 2S2P test board and in accordance with
or any other conditions above those indicated in the operational JEDEC JESD51-2 (still air).
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability. ESD CAUTION
AD9576 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF_STATUS
VDD_OUT10
VDD_OUT89
VDD_VCO1
VDD_REF2
VDD_PLL1
RESET
OUT10
OUT10
OUT9
OUT9
OUT8
OUT8
PPR3
LD_1
SP0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
REF2 1 48 OUT0
REF2 2 47 OUT0
REF_SEL 3 46 VDD_OUT01
VDD_REFMON 4 45 OUT1
REF_ACT 5 44 OUT1
REF_SW 6 43 OUT2
REF0 7 42 OUT2
AD9576
REF0 8 TOP VIEW 41 VDD_OUT23
VDD_REF0 9 (Not to Scale) 40 OUT3
VDD_REF1 10 39 OUT3
REF1 11 38 GND
REF1 12 37 OUT4
CS 13 36 OUT4
SCLK/SCL 14 35 VDD_OUT45
SDIO/SDA 15 34 OUT5
VDD_IO 16 33 OUT5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LDO_BYP
LF
LD_0
VDD_PLL0
SP1
PPR0
PPR1
OUT7
OUT7
OUT6
OUT6
PPR2
VDD_VCO0
VDD_M0
VDD_M1
VDD_OUT67
NOTES
1. THE EXPOSED PAD IS A GROUND CONNECTION ON THE CHIP THAT
MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO
13993-004
ENSURE PROPER FUNCTIONALITY, HEAT DISSIPATION, NOISE,
AND MECHANICA L STRENGTH BENEFITS.
Figure 4. Pin Configuration
Table 19. Pin Function Descriptions

Input/
Pin No. Mnemonic Output Pin Type Description
1 REF2 Input Configurable Complimentary Reference Clock Input 2. This pin is the complimentary
clock input signal to the input on Pin 2 (REF2). When REF2 is configured as 2.5 V/3.3 V,
dc-coupled, single-ended LVCMOS, leave this pin floating. When REF2 is
configured as 1.8 V, ac-coupled, single-ended LVCMOS, this pin must be ac
grounded via a 100 nF capacitor.
2 REF2 Input Configurable Reference Clock Input 2. This clock can serve as the stable clock input to the
clock input reference monitor, as well as an input to PLL1. Its format can be configured
as 2.5 V/3.3 V, dc-coupled, single-ended LVCMOS, or 1.8 V, ac-coupled, single-
ended LVCMOS, differential input (with a complimentary signal on REF2,
Pin 1, or as an XTAL input. The receiver format is power-on configurable via
PPR0 (Pin 24) and is independently configurable via the serial port.
3 REF_SEL Input 2.5 V/3.3 V CMOS Reference Clock Select. This pin selects the output clock of the reference
control selection mux, which can be either Reference Clock Input 0 or Reference Clock
Input 1 (Logic 0 or Logic 1, respectively). For this pin to function, automatic
reference switching and soft REF_SEL must be disabled (Register 0x082,
Bits[2:1] = 00). This pin has an internal 30 kΩ pull-down resistor.
4 VDD_REFMON Input Power 2.5 V or 3.3 V Power Supply.
5 REF_ACT Output 2.5 V/3.3 V CMOS Currently Selected, Active Reference Indicator. This status signal represents
the output of the reference selector mux. Logic 0 means that REF0 is the
currently selected reference, Logic 1 means that REF1 is the currently
selected reference. This pin is on the VDD_REFMON power domain.
6 REF_SW Output 2.5 V/3.3 V CMOS Reference Switchover Status Indicator. Logic 0 = normal operation, Logic 1
means reference switch in progress. This pin is on the VDD_REFMON power
domain.
Data Sheet AD9576
Input/
7 REF0 Input Configurable Reference Clock Input 0. This clock is an input to the reference selection
clock input mux. The clock format can be configured as 2.5 V/3.3 V, dc-coupled, single-
ended LVCMOS, or 1.8 V, ac-coupled, single-ended LVCMOS, differential
input (with a complimentary signal on REF0, Pin 8), or as an XTAL input. The
receiver format is power-on configurable via PPR0 (Pin 24) and is independently
configurable via the serial port.
8 REF0 Input Configurable Complimentary Reference Clock Input 0. Complimentary signal to the input
clock input on Pin 7 (REF0). When REF0 is configured as 2.5 V/3.3 V, dc-coupled, single-
ended LVCMOS, leave this pin floating. When REF0 is configured as 1.8 V,
ac-coupled, single-ended LVCMOS, this pin must be ac grounded via a
100 nF capacitor.
9 VDD_REF0 Input Power 2.5 V or 3.3 V Power Supply. Configure this supply to set the full swing
CMOS logic high level of Reference Input 0, REF0.
11 REF1 Input Configurable Complimentary Reference Clock Input 1. Complimentary signal to the input
clock input on Pin 12 (REF1). When REF1 is configured as 2.5 V/3.3 V, dc-coupled, single-
ended LVCMOS, leave this pin floating. When REF1 is configured as 1.8 V,
ac-coupled, single-ended LVCMOS, this pin must be ac grounded via a
100 nF capacitor.
12 REF1 Input Configurable Reference Clock Input 1. This clock is an input to the reference selection
clock output mux. The clock format can be configured as 2.5 V/3.3 V, dc-coupled, single-
ended LVCMOS, or 1.8 V, ac-coupled, single-ended LVCMOS, differential
input (with a complimentary signal on REF1, Pin 11), or as an XTAL input.
The receiver format is power-on configurable via PPR0 (Pin 24) and is
independently configurable via the serial port.
13 CS Input 2.5 V/3.3 V CMOS Chip Select for SPI Serial Communication (Active Low Input). When
programming the device in SPI mode, this pin must be held low, as shown
in Figure 32. The logic high level of this pin is determined by VDD_IO.
14 SCLK/SCL Input 2.5 V/3.3 V CMOS Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). This
pin is the data clock for serial programming. The logic high level of this pin
is determined by the VDD_IO pin.
15 SDIO/SDA Input/ 2.5 V/3.3 V CMOS Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO)
output or I2C Mode (SDA). The logic high level of this pin is determined by VDD_IO.
16 VDD_IO Input Power 2.5 V or 3.3 V Power Supply. Configure this pin to set the logic high level of
the serial port interface.
17 LD_0 Output 2.5 V/3.3 V CMOS PLL0 Lock Detector Status. Logic 0 means unlocked; Logic 1 means locked.
18 VDD_PLL0 Input Power 2.5 V or 3.3 V Power Supply.
19 LF Input Analog Loop Filter. Connect a 4.7 nF capacitor from this pin to LDO_BYP (Pin 20).
20 LDO_BYP Input Analog LDO Bypass. Connect a 470 nF capacitor from this pin to ground.
21 VDD_VCO0 Input Power 2.5 V or 3.3 V Power Supply.
22, 49 SP1, SP0 Input/ Control Serial Port Configuration Pins. These pins are latched at power-up and upon
output release from reset to configure the serial port as well as to determine
whether a PPR load is to occur. See Table 35 for a complete decode of
configurations. These pins use three-state logic: high, low, and floating.
23 VDD_M0 Input Power 2.5 V or 3.3 V Power Supply.
24 PPR0 Input Control Pin Program Reader 0. Connect a resistor to this pin to configure the
reference clock input formats and the PLL1 input source.
25 VDD_M1 Input Power 2.5 V or 3.3 V Power Supply.
26 PPR1 Input Control Pin Program Reader 1. Connect a resistor to this pin to configure the OUT10
frequency, input source, and logic format.
27 OUT7 Output HSTL, LVDS, 1.8 V Clock Output 7. The power-on format is determined via PPR2 (Pin 32) and
CMOS PPR3 (Pin 56). This pin is independently configurable via the serial port.
28 OUT7 Output HSTL, LVDS, 1.8 V Complimentary Clock Output 7. This pin is the complimentary signal to the
CMOS output on Pin 27 (OUT7).
29 VDD_OUT67 Input Power 2.5 V or 3.3 V Power Supply.
AD9576 Data Sheet
Input/
32, 56 PPR2, PPR3 Input Control Pin Program Reader 2 and Pin Program Reader 3. Connect a resistor to
these pins to configure the REF0/REF1 input frequency and OUT0 to OUT9.
38 GND Input Ground Power Supply Common Ground.
50 OUT8 Output 2.5 V/3.3 V CMOS, Clock Output 8. When configured as 2.5 V/3.3 V CMOS, the logic high level
1.8 V CMOS, HSTL, is determined by VDD_OUT89. The power-on format is determined via
LVDS, HCSL PPR2 (Pin 32) and PPR3 (Pin 56). This pin is independently configurable via
the serial port.
51 OUT8 Output 2.5 V/3.3 V CMOS, Complimentary Clock Output 8. This pin is the complimentary signal to the
1.8 V CMOS, HSTL, output on Pin 50 (OUT8).
LVDS, HCSL
52 VDD_OUT89 Input Power 2.5 V or 3.3 V Power Supply. Configure this supply to set the full swing
CMOS logic high level of Output 8 and Output 9.
53 OUT9 Output 2.5 V/3.3 V CMOS, Complimentary Clock Output 9. This pin is the complimentary signal to the
1.8 V CMOS, HSTL, output on Pin 54 (OUT9).
LVDS, HCSL
54 OUT9 Output 2.5 V/3.3 V CMOS, Clock Output 9. When configured as 2.5 V/3.3 V CMOS, the logic high level
1.8 V CMOS, HSTL, is determined by VDD_OUT89. The power-on format is determined via
LVDS, HCSL PPR2 (Pin 32) and PPR3 (Pin 56). This pin is independently configurable via
the serial port.
55 REF_STATUS Output 2.5 V/3.3 V CMOS Reference Status Indicator. When the reference monitor is enabled, this pin
indicates if the output of the reference selection mux is determined to be
within the configured tolerance setting. Logic 0 means the reference is within
tolerance; Logic 1 means the reference is outside of tolerance. When the
reference monitor is disabled, this pin indicates the loss of reference (LOR)
status for the requested reference.
57 VDD_OUT10 Input Power 2.5 V or 3.3 V Power Supply. Configure this supply to set the full swing
CMOS logic high level of Output 10. This pin also serves as the PPRx power
supply.
Data Sheet AD9576
Input/
58 OUT10 Output 2.5 V/3.3 V CMOS, Clock Output 10. When configured as 2.5 V/3.3 V CMOS, the logic high level is
1.8 V CMOS, HSTL, determined by VDD_OUT10. The power-on format is determined via PPR1
LVDS, HCSL (Pin 26). This pin is independently configurable via the serial port.
59 OUT10 Output 2.5 V/3.3 V CMOS, Complimentary Clock Output 10. This pin is the complimentary signal to
1.8 V CMOS, HSTL, the output on Pin 58 (OUT10).
LVDS, HCSL
60 VDD_VCO1 Input Power 2.5 V or 3.3 V Power Supply.
61 VDD_PLL1 Input Power 2.5 V or 3.3 V Power Supply.
62 LD_1 Output 2.5 V/3.3 V CMOS PLL1 Lock Detector Status. Logic 0 means unlocked; Logic 1 means locked.
63 RESET Input Control Reset. Logic 0 initializes the device to its default state (see the PPRx Pins
section for details). This pin has an internal 30 kΩ pull-up resistor.
EPAD Input Ground Exposed Pad. The exposed pad is a ground connection on the chip that
must be soldered to the analog ground of the PCB to ensure proper
functionality, heat dissipation, noise, and mechanical strength benefits.
AD9576 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS

PHASE NOISE AND VOLTAGE WAVEFORMS
VDD_x = nominal, TA = 25°C. The only enabled output channels are those indicated in the figure captions. The phase noise plots (see Figure 5 to
Figure 9) show the Taitien XO A0145-L-006-3 (noted as XO in the figures) phase noise normalized to the output frequency. The voltage
waveform plots (see Figure 10 to Figure 16) embody ac coupling to the measurement instrument.
AD9576 AD9576
XO XO
PHASE NOISE (dBc/Hz)

13993-005
13993-008
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M
FREQUENCY OFFSET (Hz) FREQUENCY OFFSET (Hz)
Figure 5. Phase Noise (OUT0)—fOUT0 = 644.53125 MHz (HSTL), Fractional Figure 8. Phase Noise (OUT2)—fOUT2 = 156.25 MHz (HSTL)
AD9576 AD9576
XO XO

13993-006
13993-009
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
FREQUENCY OFFSET (Hz) FREQUENCY OFFSET (Hz)
Figure 6. Phase Noise (OUT3)—fOUT3 = 100 MHz (HSTL), fOUT4 = 125 MHz (HSTL) Figure 9. Phase Noise (OUT3)—fOUT3 = 125 MHz (HSTL), fOUT4 = 100 MHz (HSTL)
AD9576 156.25MHz
312.5MHz
XO
OUTPUT VOLTAGE (V)
13993-010
13993-007
100 1k 10k 100k 1M 10M 0 5 10 15 20 25

FREQUENCY OFFSET (Hz) TIME (ns)
Figure 7. Phase Noise (OUT4)—fOUT4 = 312.5 MHz (LVDS) Figure 10. OUT0 Output Waveform, HSTL (156.25 MHz, 312.5 MHz)
Data Sheet AD9576
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)
100MHz
400MHz
13993-014
13993-011
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25
TIME (ns) TIME (ns)
Figure 11. OUT8 Output Waveform, HCSL (100 MHz, 400 MHz) Figure 14. OUT0 Output Waveform, LVDS ( 312.5 MHz)
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)
13993-012
13993-015
0 10 20 30 40 50 60 0 20 40 60 80 100 120 140 160
TIME (ns) TIME (ns)
Figure 12. OUT8 Output Waveform, 1.8 V CMOS (66.67 MHz), 10 pF Load Figure 15. OUT8 Output Waveform, 3.3 V CMOS (25 MHz), 10 pF Load
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
13993-016
13993-013
0 5 10 15 20 25 30 0 5 10 15 20 25 30
TIME (ns) TIME (ns)
Figure 13. OUT8 Output Waveform, LVDS (133.3 MHz) Figure 16. OUT8 Output Waveform, 3.3 V CMOS (133.3 MHz), 10 pF Load
AD9576 Data Sheet
REFERENCE SWITCHING FREQUENCY AND PHASE DISTURBANCE
VDD_x = nominal, TA = 25°C. The only enabled output channels are those indicated in the figure captions. The reference switchover phase
disturbance plots, Figure 17, Figure 18, and Figure 19, each show a collection of output phase variations due to approximately 250 reference
switching events between two references with a frequency offset of approximately 2 ppm. Each reference switch event (initiated by
toggling the REF_SEL pin) occurs at a random phase offset between the two references. The plots demonstrate the tightly controlled
phase disturbance at the output as a result of the reference switching logic seeking the optimal moment to switch references.
FREQUENCY DEVIATION (Hz)
RELATIVE PHASE (Degrees)

13993-017
13993-019
0 1 2 3 4 5 6 0 1 2 3 4 5 6
TIME (μs) TIME (μs)
Figure 17. Reference Smooth Switchover Frequency Disturbance for OUT0 at Figure 19. Reference Smooth Switchover Phase Disturbance for OUT8 at
156.25 MHz (PPR0 = 3, PPR1 = 0, PPR2 = 0, PPR3 = 3) 25 MHz (PPR0 = 3, PPR1 = 0, PPR2 = 0, PPR3 = 3)
9.0
6.5
RELATIVE PHASE (Degrees)
4.0
1.5
–1.0
–3.5
–6.0
13993-018
0 1 2 3 4 5 6
TIME (μs)
Figure 18. Reference Smooth Switchover Phase Disturbance for OUT0 at

156.25 MHz (PPR0 = 3, PPR1 = 0, PPR2 = 0, PPR3 = 3)
Data Sheet AD9576
TERMINOLOGY
Phase Jitter Time Jitter
An ideal sine wave has a continuous and even progression of Phase noise is a frequency domain phenomenon. In the time
phase with time from 0° to 360° for each cycle. Actual signals, domain, the same effect is exhibited as time jitter. When observing
however, display a certain amount of variation from ideal phase a sine wave, the time of successive zero crossings is seen to vary.
progression over time. This phenomenon is called phase jitter. In a square wave, the time jitter is seen as a displacement of the
Although many causes can contribute to phase jitter, one major edges from their ideal (regular) times of occurrence. In both
cause is random noise, which is character-ized statistically as cases, the variations in timing from the ideal are the time jitter.
Gaussian (normal) in distribution. Because these variations are random in nature, the time jitter is
This phase jitter leads to the energy of the sine wave spreading specified in units of seconds root mean square (rms) or 1 Σ of the
out in the frequency domain, producing a continuous power Gaussian distribution.
spectrum. This power spectrum is usually reported as a series of Additive Phase Noise
values whose units are dBc/Hz at a given offset in frequency from Additive phase noise is the amount of phase noise that is
the sine wave (carrier). The value is a ratio (expressed in dB) of attributable to the device or subsystem being measured. The
the power contained within a 1 Hz bandwidth with respect to phase noise of any external oscillators or clock sources is sub-
the power at the carrier frequency. For each measurement, the tracted, which makes it possible to predict the degree to which
offset from the carrier frequency is also given. the device impacts the total system phase noise when used in
Phase Noise conjunction with the various oscillators and clock sources, each
When the total power contained within some interval of offset of which contributes its own phase noise to the total. In many
frequencies (for example, 12 kHz to 20 MHz) is integrated, it is cases, the phase noise of one element dominates the system
called the integrated phase noise over that frequency offset interval, phase noise.
and it can be readily related to the time jitter due to the phase Additive Time Jitter
noise within that offset frequency interval. Additive time jitter is the amount of time jitter that is attributable
Phase noise has a detrimental effect on error rate performance to the device or subsystem being measured. The time jitter of
by increasing eye closure at the transmitter output and reducing any external oscillators or clock sources is subtracted, which
the jitter tolerance/sensitivity of the receiver. makes it possible to predict the degree to which the device
impacts the total system time jitter when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own time jitter to the total. In many cases, the
time jitter of the external oscillators and clock sources dominates
the system time jitter.
AD9576 Data Sheet
THEORY OF OPERATION
1.8V CMOS
AD9576 10
2.5V/3.3V CMOS
HCSL
÷Q4 LVDS
HSTL
÷N1 9 1.8V CMOS

2.5V/3.3V CMOS
HCSL
÷Q3 LVDS
8 HSTL
PFD
×2 CHARGE VCO1
PUMP
LPF
REF2 ÷R1 0
PLL1
INTEGER-N 1 1.8V CMOS
REF_STATUS REF0/REF1 ÷Q0 LVDS
MONITOR PLL0 HSTL
FRACTIONAL-N ÷QZD 2
REF_SEL ÷N0A
REF0/REF1 3
REF_ACT SWITCHOVER
÷N0
REF_SW
÷M0 4
1.8V CMOS
÷Q0 LVDS
REF0 HSTL
5
PFD
×2 CHARGE VCO0
PUMP
LPF
÷M1
÷R0
REF1
6
1.8V CMOS
÷Q1 LVDS
HSTL
CONTROL 7
INTERFACE PPRx LOGIC
13993-020
(I2C/SPI)
Figure 20. Detailed Functional Block Diagram
OVERVIEW The AD9576 provides up to 11 output channel clocks (OUT0 to

Figure 20 shows a block diagram of the AD9576. The AD9576 OUT10). OUT0 to OUT7 are driven by PLL0 exclusively and
is a 2.5 V or 3.3 V single-supply, pin programmable, power-on are comprised of three subgroups of outputs (OUT0 to OUT3,
ready, dual-channel clock that is fully configurable via a serial OUT4 and OUT5, and OUT6 and OUT7). Each output within a
port interface (SPI). The two parallel channels consist of a high subgroup is individually configurable, but generates the same
performance, fractional-N PLL (PLL0) and a general-purpose, output frequency. These outputs support LVDS, HSTL, or 1.8 V
integer-N PLL (PLL1). LVCMOS output formats.
There are a total of three reference inputs (REF0 to REF2) on OUT8 and OUT9 have three potential sources: the output of the
the AD9576. Each input receiver provides differential or single- PLL1 reference selection mux directly, the output of PLL0, or
ended input configurations. REF0 and REF1 drive the reference the output of PLL1. These outputs are individually configurable,
switchover multiplexer (mux). The output of this reference switch- but must share the same source and, therefore, the same output
over mux drives the input of PLL0 and an input to the PLL1 frequency. OUT10 is driven by either the output of the PLL1
reference selection mux. REF2 drives the alternate input of the reference selection mux directly or the output of PLL1. These
PLL1 reference selection mux and serves as monitor clock to three outputs support LVDS, HSTL, HCSL, 1.8 V CMOS, and
the on-board reference monitor, which monitors the reference 2.5 V/3.3 V CMOS (the swing is determined by the supply
switchover mux output clock frequency. REF2 supports frequencies level) output formats.
of 8 kHz, 10 MHz, 19.44 MHz, 25 MHz, and 38.88 MHz, while REFERENCE INPUTS
REF0 and REF1 support 8 kHz, 1.544 MHz, 2.048 MHz, and The AD9576 features a flexible PLL reference input circuit
10 MHz to 325 MHz. However, the PLL1 phase and PFD input that provides three operating modes: single-ended input, fully
rate is limited to 25 MHz or 50 MHz, so only a subset of allowable differential input, or external crystal input. The operating
reference input frequencies are valid for use as an input to PLL1. mode of the REF0, REF1, and REF2 input receivers are
selected and controlled by the scanned state of the PPR0 pin
or by Register 0x080 and Register 0x081 (see Table 45).
Register 0x080 and Register 0x081 allow fully independent
control of the operating mode selection for each reference input.
Data Sheet AD9576
In single-ended CMOS buffer mode, a 2.5 V or 3.3 V clock bits (Register 0x021, Bits[5:4]) and the REF_STATUS pin. To
source is connected directly to the positive reference input pin enable the reference monitor, the user must set the enable reference
(for example, REF0). Note that, in single-ended mode, it is best monitor bit (Register 0x083, Bit 7) to Logic 1. Note that the
to connect a 0.1 µF capacitor from the negative input pin (for frequency accuracy of the inactive reference channel is not
example, REF0) to GND. The CMOS swing of the reference monitored.
input is dependent on VDD_x of said reference input supply and
Table 20. Reference Monitor Error Window
does not exceed VDD_x. The single-ended CMOS receivers are
powered down when their individual power-down bits are set in Frequency Error
Threshold (ppm) Register 0x083, Bits[1:0] Value
Register 0x080 and Register 0x081, or when operating in
±10 00
differential or external crystal input mode.
±25 01
In differential mode, a differential clock driver is connected to ±50 10
the two reference input pins (for example, REF0 and REF0). ±100 11
Note that, in differential operating mode, the reference input Reference monitoring is only supported for two input frequencies,
pins are internally self biased to allow ac coupling. That is, a 19.44 MHz and 25 MHz. The user must specify which frequency is
0.1 µF capacitor is connected in series from each output of the to be monitored by configuring the monitored frequency bit
external differential clock driver to the corresponding reference (Register 0x083, Bit 5). A Logic 0 value indicates that the PLL0
input pin. This mode also supports a single-ended, 1.8 V CMOS input frequency is 25 MHz, whereas a Logic 1 indicates a frequency
clock source by connecting the source to the positive reference of 19.44 MHz. The reference monitor frequency reference, REF2,
input pins (for example, REF0) with the negative reference can be one of five frequencies selectable via two bit fields, as
input pin (for example, REF0) connected to GND via a 0.1 µF shown in Table 21.
capacitor. The differential input receivers are powered down
when their individual power-down bits are set in Register 0x080 Table 21. REF2 Monitor Frequency Decode
and Register 0x081, or when operating in single-ended CMOS Register 0x083, Register 0x083,
or external crystal input mode. REF2 Input Frequency Bit 4 Value Bits[3:2] Value
8 kHz 1 Not applicable
External crystal mode is comparable to differential mode,
10 MHz 0 00
except a fundamental mode AT cut crystal is connected across
19.44 MHz 0 01
the two reference input pins (REF0 and REF0, for example) and
25 MHz 0 10
is powered by an internal maintaining amplifier. The external
38.88 MHz 0 11
crystal receivers are powered down via the individual power down
bits in Register 0x080 and Register 0x081, or when operating in After comparing the calculated input frequency ppm error to
single-ended or differential input mode. The REF0 and REF1 the user specified threshold window, the resulting frequency
external crystal receivers are also powered down if they are not accuracy is reported on the reference status bits (Register 0x021.
the currently active/requested reference clock for PLL0. Bits[5:4]) and on the REF_STATUS pin. The values of the reference
status bits and the respective significance are listed in Table 22.
The reference input format bits, REF0 format (Register 0x080,
The status indicated on the REF_STATUS pin is the logical OR
Bits[1:0]), REF1 format (Register 0x080, Bits[5:4]), and REF2
of the reference status bits.
format (Register 0x081, Bits[1:0]) must be set correctly for the
applied input. These bits are set to 00 for 2.5 V and 3.3 V CMOS Table 22. Reference Frequency Monitor Status Decode
inputs, 01 for differential inputs and 1.8 V CMOS inputs, and Frequency Status Register 0x021, Bits[5:4] Value
10 for XTAL inputs. Setting the reference input format bits Valid 00
incorrectly for the applied input may cause undesired results. The Slow 01
input frequency range for the reference inputs is specified in Fast 10
Table 4. Indeterminate Fault 11
REFERENCE MONITOR The REF_STATUS pin similarly reports whether the frequency
The AD9576 reference monitor function provides the user a of the active input is within the user specified threshold window. A
means to validate the frequency accuracy of the PLL0 active Logic 0 on this pin indicates the selected input reference frequency
reference (REF0 or REF1) in real time. When enabled, the is within the tolerance threshold specified by the user, whereas a
reference monitor uses REF2 as the frequency reference to Logic 1 indicates the selected input reference frequency is outside
continuously test the frequency accuracy of the active reference. the tolerance threshold specified by the user. Note that the
The measured frequency error of the PLL0 active input reference is REF_STATUS pin only specifies whether the selected input
compared to a user programmable frequency error threshold. reference frequency is within the user specified tolerance threshold.
The result is reported as being either within or outside the user If more detailed information regarding the manifestation of the
specified threshold (see Table 20) on both the reference status error is required, refer to the reference status bits.
AD9576 Data Sheet
In addition to the frequency monitoring function, the reference clock is designated by the state of REF_SEL when the enable
monitor also checks for the presence of a clock signal at the REF0, XTAL redundancy switchover bit is set to Logic 1.
REF1, and REF2 inputs. The absence of a clock signal results in In manual reference switchover mode, the user manually
an internal LOR indication for that particular clock input. A changes the input reference by toggling the state of either the
Logic 1 LOR status indicates that the reference is not present,or soft reference select bit (Register 0x082, Bit 0) or the REF_SEL pin
that the frequency is below approximately 1 MHz. A Logic 0 status (Pin 3). The control method of manual reference switchover is
indicates that reference input is detected and the frequency is determined by the state of the enable soft reference select bit
greater than 1 MHz. When REF2 is configured as an 8 kHz (Register 0x082, Bit 1), as shown in Table 24.
reference to be used with the reference monitor, the REF2 LOR
circuitry uses the PLL0 active reference to qualify the presence Table 24. PLL0 Active Reference Selection Source Decode
and accuracy of the REF2 input clock. Table 23 defines the PLL0 Active Reference Selection Register 0x082, Bit 1
REF2 LOR conditions for all valid operating modes. Source Value
REF_SEL (Pin 3) 0
Table 23. REF2 LOR Status Decode Register 0x082, Bit 0 1
REF2 Input REF0/REF1 Reg. 0x021, REF2 LOR
Frequency Frequency Bit 2 Value Condition When the REF_SEL pin controls manual reference switchover, a
8 kHz 25 MHz 0 >6.1 kHz logic signal is supplied to the pin to specify the desired input
1 < 6.1 kHz reference. A Logic 0 on the REF_SEL pin informs the internal
19.44 MHz 0 >4.7 kHz reference switching logic to make REF0 the active reference
1 <4.7 kHz input, whereas a Logic 1 makes REF1 the active reference.
10 MHz, 19.44 MHz, Not 0 >1 MHz When the soft reference select bit controls manual reference
25 MHz, or 38.88 MHz applicable 1 <1 MHz switchover, setting this bit to a Logic 0 selects REF0 as the active
reference input, whereas setting this bit to a Logic 1 selects REF1
A LOR condition for a given reference is reported on its respective as the active input reference. Note that, with manual switching
status bit in Register 0x021 (see Table 43). Furthermore, when enabled, the frequency monitoring function of the reference
reference frequency monitoring is disabled, the REF_STATUS pin monitor (see the Reference Monitor section) may still be used,
logic state indicates the LOR status for the PLL0 requested but it does not trigger a reference switchover for PLL0.
reference input.
Both manual and XTAL redundancy reference switchover
REFERENCE SWITCHING modes provide the option of using the smooth switchover
The AD9576 provides both manual switchover as well as a function. The smooth switchover function is enabled by setting
single-shot, automatic XTAL redundancy switchover capability. the disable smooth switchover bit (Register 0x082, Bit 3) to
The reference switchover mode is specified through the enable Logic 0. The smooth switchover function waits for a minimal
XTAL redundancy switchover bit (Register 0x082, Bit 2). By phase offset to occur between the REF0 and REF1 reference
default, this bit is Logic 0 and manual reference switching is inputs, prior to physically switching to the newly requested
enabled. Setting this bit to a Logic 1 enables automatic XTAL reference. This functionality ensures a minimal frequency and
redundancy switchover. phase disturbance on the output clocks associated with the PLL
Automatic XTAL redundancy switchover mode can only be due to a reference switchover event. Correct operation of the
used when the following three conditions are met: smooth switchover function requires the input references be
asynchronous and that a LOR fault condition does not occur on
• REF0/REF1 are external crystal inputs (Register 0x080, either reference input while the switch is being made. When the
Bits[5:4] and Register 0x080, Bits[1:0] are both set to 10). smooth switchover function is disabled (Register 0x082, Bit 3 = 1),
• The reference monitoring function is enabled the switch to the new active reference is instantaneous and the
(Register 0x083, Bit 7 is set to 1). frequency disturbance on the output clocks during reference
• The REF_SEL pin is held at a static logic state. switchover may increase.
The XTAL redundancy switchover is a single use operation per The reference switching logic provides information about
device reset, switching from the initial input reference (for example, which reference channel is the currently active reference, via the
REF0) to the alternate input reference (for example, REF1). When REF_ACT pin (Pin 5) and the active reference bit (Register 0x021,
the reference monitor determines the selected input frequency Bit 3). The REF_ACT pin and the active reference bit are both
accuracy is outside of the specified error window, the alternate Logic 0 when REF0 is the active reference, and are both Logic 1
input is automatically selected as the new active reference input. when REF1 is the active reference. Additionally, the reference
Upon completion of the automatic XTAL redundancy switchover, switching logic indicates when the device is in the process of
the newly selected alternate reference (for example, REF1) performing a smooth reference switchover via the REF_SW pin
continues to be the input reference source for PLL0, regardless (Pin 6). The REF_SW pin assumes a Logic 1 state when REF_SEL
of the accuracy of the frequency. The initial input reference changes states and returns to a Logic 0 state when the device
Data Sheet AD9576
completes the reference switchover process. In manual smooth PLL0 Reference Frequency Scaling
reference switchover mode, confirm that the device has completed The frequency of the active input reference (REF0 or REF1) is
the requested switch to the desired reference (REF_SW pin = scalable via the PLL0 doubler enable bit (Register 0x101, Bit 3)
Logic 0) before initiating a subsequent change of reference request. and the R0 divider ratio bits (Register 0x105, Bits[5:0]). This
Changing the state of the REF_SEL pin or the soft reference allows the user to scale the input reference frequency to satisfy
select bit before the internal state machine completes the previous the input range of the PFD. When the PLL0 doubler enable bit
smooth reference switching process does not result in a is set to Logic 1, the input frequency to the PFD of PLL0, fPFD0, is
subsequent reference switch. twice the active reference input frequency. When the PLL0
Because the smooth reference switchover function waits for a doubler enable bit is set to Logic 0, fPFD0 is a function of the active
minimal phase offset between references prior to making a reference frequency scaled by the R0 divider ratio bits.
switch, if either of the reference inputs are removed completely
fPFD0 = f REF
and a switchover request is initiated, the internal smooth R0
switching state machine stalls and the device is unable to switch where:
references, thereby retaining the currently active reference. If fREF is the frequency of the active reference, REF0 or REF1.
the current active reference fails, the device loses lock, thereby R0 is the value of the R0 divider ratio bits.
necessitating a device reset. If the requested reference fails, the
device retains the currently active reference, but switches to the When the PLL0 doubler enable bit is set to Logic 1, the
requested reference if it becomes available. Note that, as long as frequency appearing at the input to the PFD of PLL0, fPFD0, is
a reference remains absent, the state machine remains stalled. the active reference frequency multiplied by a factor of two.
Only a device reset makes the state machine disregard the initial fPFD0 = fREF × 2
request to switch references.
where fREF is the frequency of the active reference, REF0 or REF1.
PLL0 INTEGER-N/FRACTIONAL-N PLL Note that, when the ×2 frequency multiplier is in use, the active
PLL0 is a fractional-N PLL capable of operating in integer reference signal must have a duty cycle close to 50%. Otherwise,
mode. It consists of seven functional elements: a reference spurious artifacts (harmonics) may propagate through the
frequency prescalar, a PFD, a charge pump, a loop filter, a VCO, signal path and appear at the output of PLL0.
feedback dividers, and an optional, third-order, Σ-Δ modulator PLL0 Loop Configurations
(SDM) that allows fractional divide ratios. PLL0 provides two
PLL0 is capable of three different loop configurations. Loop 0 is the
independent reference clock input signals. The device supports
differential, single-ended, and XTAL operation for both reference fractional translation path, Loop 1 accommodates low frequency
clocks. PLL0 provides 10 outputs, segregated into four groups. reference inputs, and Loop 2 is a zero delay feedback path. The
PLL0 loop configuration is selected by programming the PLL0
Each group has a dedicated channel divider allowing the device
loop mode bits (Register 0x101, Bits[2:1]) as shown in Table 25.
to produce four different output frequencies simultaneously.
Note that PLL0 is capable of several different loop configurations, Table 25. PLL0 Loop Configuration Decode
with each described in the following sections. Figure 21 shows Register 0x101,
the functional block diagram of PLL0. PLL0 Loop Configuration Bits[2:1] Value
PLL0
Loop 0: Fractional-N/Integer-N 00
FRAC-N/ Loop 1: Low PFD Frequency 01
INT-N ÷QZD
÷N0A Loop 2: Zero Delay 10

÷N0 Reserved 11
÷M0
ACTIVE
PFD
×2 CHARGE VCO0
REF PUMP
13993-021
÷R0 ÷M1
Figure 21. PLL0 Functional Block Diagram
AD9576 Data Sheet
Loop Configuration 0—Fractional-N/Integer-N The resulting values to be used as the operating N0 fraction and
N0 modulus values are as follows:
LF LDO_BYP
N0 fraction = scalar × 73 = 69,042 × 73 = 5,040,066
DISTRIBUTION
REF0 REF. OUT0
REF1
INPUT
1.8V LOOP ÷M0,
N0 modulus = scalar × 243 = 69,042 × 243 = 16,777,206
PFD
CP FILTER VCO
M1
REF_SEL The overall frequency translation equation for Loop 0 is
OUT9
÷N0
 N0 fraction 
 N0  
13993-022
f REF  N0 modulus
AD9576: PLL0 SDM
Figure 22. PLL0 Loop Configuration 0 fOUT = 

R0 MZ  QY
The Loop 0 configuration is the only configuration that supports a
where:
fractional-N translation in addition to integer-N translations.
fOUT is the frequency at the output driver, OUTx (OUT0 through
This configuration uses a single feedback divider, N0, with an
OUT9).
integrated Σ-Δ modulator.
fREF is the frequency of the active reference (REF0 or REF1).
The VCO0 frequency is a function of the PFD input frequency MZ is the VCO divider (M0 or M1) that is the input source of QY.
(see the PLL0 Reference Frequency Scaling section) and the QY is the channel divider (Q0, Q1, Q2, or Q3) associated with
values programmed into the registers associated with N0, N0 OUTx.
fraction, and N0 modulus. R0 is the divider value used to scale the input reference
  frequency and is an element of the following set: {½, 1, 2 … 63}.
N0 fraction
f VCO0  f PFD0   N0   Note the value of ½ is the result of selecting the ×2 reference
 N0 modulus 
  multiplier (see the PLL0 Reference Frequency Scaling section).
where: N0 is an element of the set: {NMIN, NMIN + 1, …NMAX} where
fVCO0 is the frequency of the VCO. NMIN, NMAX are 12 and 255, respectively, for integer-N operation
fPFD0 is the frequency at the input to the PFD. and NMIN, NMAX are 15 and 252, respectively, for fractional-N
N0 is an element of the following set: {NMIN, NMIN + 1, …, 255}, operation.
where NMIN = 12 for integer-N operation and NMIN = 15 for N0 fraction is an element of the set: {0, 1, …, 16,777,214}.
fractional-N operation. N0 modulus is an element of the set: {1, 2, …, 16,777,215} with
N0 fraction is an element of the following set: {0, 1, …, the constraint N0 fraction < N0 modulus.
16,777,214}. MZ is the divide value of the VCO divider and is an element of
N0 modulus is an element of the following set, but with the the set: {2, 3, …, 11}.
constraint of N0 fraction < N0 modulus: {1, 2, …, 16,777,215}. QY is the divide value of the channel divider and is an element
Programming the N0 SDM power-down bit (Register 0x101, Bit 0) of the set: {1, 2, …, 64}.
to Logic 1 disables the SDM, making N0 fraction functionally Loop Configuration 1—Low PFD Frequency
equivalent to a value of 0, and PLL0 can only be configured as
LF LDO_BYP
an integer-N PLL. This is also the case if N0 fraction is program-
DISTRIBUTION
med to 0; however, the SDM circuitry is not placed into a low REF0 REF. OUT0
power state. Integer-N operation yields the best performance in REF1 INPUT
1.8V LOOP ÷M0,
PFD
CP FILTER VCO M1
terms of phase noise, spurs, and jitter. REF_SEL
OUT9
÷N0A ÷N0
To obtain the best performance in fractional-N operation,
13993-023
configure the N0 modulus value to the largest possible value as

AD9576: PLL0
allowed by the fractional translation being synthesized. For
Figure 23. PLL0 Loop Configuration 1
example, if a 19.44 MHz input is being translated to a 625 MHz
output, the required VCO operating frequency is 2500 MHz. The Loop 1 configuration is an integer-N configuration that
Using the input doubler, this requires an N divider value of 64 + uses a cascade of two feedback dividers, N0 and N0A, to operate at
73/243. To make the modulus as large as possible, both the much lower PFD frequencies. In this configuration, the charge
modulus and fraction values must be multiplied by the same pump current is internally set to a value of 1024 μA, an internal
scaling value. The scaling value is calculated as follows: switch shorts RZERO in the integrated loop filter and automatically
sets the integrated pole capacitor (CPOLE2) to 100 pF. This
 224  1 
Scalar = floor   = floor  16,777,215  = 69,042 particular internal loop filter configuration provides the flexibility
modulus   243  to set the response zero and the first pole frequency of the loop
 
filter (via an external R-C network) to accommodate a low PFD
rate. Note that Loop 1 configures PLL0 as an integer-N PLL
only. Therefore, to ensure proper device operation, the N0 SDM
Data Sheet AD9576
power-down bit must be set to Logic 1, or the N0 fraction value Loop Configuration 2—Zero Delay
must be set to 0.
LF LDO_BYP
The VCO0 frequency is a function of the PFD input frequency
DISTRIBUTION
REF0 REF.
(see the PLL0 Reference Frequency Scaling section) and the values INPUT
OUT0
REF1 1.8V LOOP
PFD
programmed into the registers associated with N0 and N0A. CP FILTER VCO ÷M0
REF_SEL
OUT9
fVCO0 = fPFD0 × N0 × N0A ÷QZD
13993-024
The divider value of N0 is set by programming the N0 divider
AD9576: PLL0
integer value bits to a value between 12 and 255. N0A is a 12-bit
divider that is set by programming the N0A Divider Ratio[11:0] Figure 24. PLL0 Loop Configuration 2
bits (Register 0x10E, Bits[7:0] and Register 0x10F, Bits[3:0]) as In the Loop 2 configuration, the total feedback division ratio is
shown in Table 26. a cascade of the VCO divider, M0, and the channel divider, QZD.
The channel divider, QZD, operates identically to any other
Table 26. N0A Divider Ratio Decode
channel divider configured with M0 as an input clock source;
N0A Divider Ratio[11:0] Value Divider Operation
however, the output of the divider is not routed to an output
0 to 3 Invalid setting
driver, but rather to the PLL0 PFD feedback clock input. This
4 to 4095 Divide by this value
feedback scheme, along with QZD being synchronized with the
The overall frequency translation equation for Loop 1 is as follows: other channel dividers (see the Synchronization section) allows
the loop to establish a minimal delay between the rising edges
f REF (N0 × N0A ) of the reference input and the output clocks. See the PLL0 VCO
fOUT = ×
R0 M Z × QY Calibration section for information concerning the impact of
where: the QZD synchronization on the VCO0 calibration procedure.
fOUT is the frequency at the output driver, OUTx (OUT0 through The VCO0 frequency is a function of the PFD input frequency
OUT9). (see the PLL0 Reference Frequency Scaling section) and the values
fREF is the frequency of the active reference (REF0 or REF1). programmed into the registers associated with M0 and QZD.
MZ is the VCO divider (M0 or M1) that is the input source of QY. fVCO0 = fPFD0 × (M0 × QZD)
QY is the channel divider (Q0, Q1, Q2, or Q3) associated with
OUTx. M0 is described in detail in the PLL0 VCO Dividers (M0 and
M1) section and QZD is described in detail in the Channel
R0 is the divider value used to scale the input reference Dividers section.
frequency and is an element of the following set: {½, 1, 2 … 63}.
Note that the value of ½ is the result of selecting the ×2 reference The overall frequency translation equation for Loop 2 is as follows:
multiplier (see the PLL0 Reference Frequency Scaling section). f REF M0 × QZD
fOUT = ×
N0 is an element of the following set: {12, 13 … 255}. R0 M Z × QY
N0A is an element of the following set: {4, 5 … 4095}. where:
MZ is the divide value of the VCO divider and is an element of fOUT is the frequency at the input to the channel dividers, OUTx
the following set: {2, 3 … 11}. (OUT0 through OUT9).
fREF is the frequency of the active reference (REF0 or REF1).
QY is the divide value of the channel divider and is an element QZD is the zero delay feedback divider.
of the following set: {1, 2 … 64}. MZ is the VCO divider (M0 or M1) that is the input source of QY.
QY is the channel divider (Q0, Q1, Q2, or Q3) associated with
OUTx.
R0 is the divider value used to scale the input reference
frequency and is an element of the following set: {½, 1, 2, …,
63}. Note that the value of ½ is the result of selecting the ×2
reference multiplier (see the PLL0 Reference Frequency Scaling
section).
M0 and MZ are divide values of the VCO dividers and are
elements of the following set: {2, 3, …, 11}.
QZD and QY are divide values of the channel divider and are
elements of the following set: {1, 2, …, 64}.
AD9576 Data Sheet
For deterministic phase alignment through a reference However, the maximum value for N0 is 255. Therefore, to
switchover event, configure the output frequency of QZD (and, calibrate the VCO, use Loop Mode 1, which requires N0 = 50
therefore, the PLL0 PFD frequency) such that it is equal to the and N0A = 8. See the PLL0 VCO Calibration section for
greatest common denominator (GCD) of all channel divider detailed information about calibrating in Loop Mode 2 when
output frequencies on the PLL0 synchronization domain and the M0 × QZD > 255.
reference input. Note that using smooth switchover minimizes the phase offset
In the following example, between reference inputs for a reference switchover event.
Therefore, the use of smooth switching allows deterministic
• fIN = 25 MHz
phase alignment to be maintained through a switchover event
• fOUT0_TO_OUT3 = 125 MHz
without the need for the reference input divider.
• fOUT4_TO_OUT5 = 312.5 MHz
• fOUT6_TO_OUT7 = 625 MHz PLL0 Phase Frequency Detector (PFD) and Charge Pump
• fOUT8_TO_OUT10 = 25 MHz from the PLL0 active reference input. The PFD determines the phase difference between the edges of
• fPFD0 = GCD (25, 125, 312.5, 625) = 12.5 MHz the reference divider output and the feedback divider output.
• fVCO0 = 625 MHz × 4 = 2500 MHz The maximum operating frequency of the PFD depends on the
operating mode of the PLL (see Table 6).
Therefore, R0 = 2 and M0 × QZD = 2500/12.5 = 200. This
requires the following conditions: The circuit provides two pulse-width modulated output signals:
up and down. These up/down pulses drive the charge pump
• M0 ≥ 4 = ceil(200/64) circuit. The instantaneous phase error determines the amount
• M0 = 4 of charge delivered from the charge pump to the loop filter. The
• QZD = 50 closed-loop of the PLL typically drives the frequency and phase
• Q0 = 5 difference between the two PFD input signals toward zero.
• Q1 = 2 The 1.8 V charge pump current is user-programmable in
• Q1 source = M0 increments of 4 µA up to 1.02 mA via the PLL0 charge pump
• Q2 = 1 current bits (Register 0x102, Bits[7:0]). The charge pump
• Q2 source = M0 current is determined by multiplying the bit field value of the
• N0 = 200 PLL0 charge pump current bits by 4 µA. For example, the
default setting of 0x8D produces a charge pump current of
In the following example,
141 × 4 µA = 564 µA.
• fIN = 25 MHz
PLL0 Loop Filter
• fOUT0_TO_OUT3 = 156.25 MHz
The loop filter affects the dynamic characteristics of a PLL (for
example, lock time and stability). The AD9576 provides both
internal and external partially integrated loop filter capabilities
• fOUT8_TO_OUT10 = 25 MHz from the PLL0 active reference input
for VCO0. The loop filter used is specified by the PLL0 loop
• fPFD0 = GCD (25, 125, 156.25, 625) = 6.25 MHz filter bypass bit (Register 0x104, Bit 0). Setting this bit to Logic 0
• fVCO0 = 625 MHz × 4 = 2500 MHz uses the internal loop filter, whereas Logic 1 uses an external
Therefore, R0 = 4 and M0 × QZD = 2500/6.25 = 400. This loop filter for VCO0. For both the external and internal loop
requires M0 ≥ 7 = ceil(400/64). M1 must be used to generate all filter, the value of CPOLE2 is fixed internally to 16 pF.
the required frequencies in this configuration, resulting in the Operating VCO0 with the internal loop filter requires a
following settings: single 4.7 nF external capacitor connected between the LF and
• M0 = 8 LDO_BYP pins. The other loop filter components are internal
• QZD = 50 and can be programmed through the PLL0 loop filter bits
(Register 0x103, Bits[7:0]). Note PLL0 uses a static charge
• Q0 = 2
pump current; therefore, the nominal bandwidth of 400 kHz
• M1 = 4
varies slightly as the feedback divide ratio deviates from a value
• Q1 = 5
of 50.
• Q1 source = M1
• Q2 = 1 When VCO0 uses the external loop filter, the value of
RPOLE2 is internal and set by the PLL0 loop filter RPOLE2 bits
• Q2 source = M1
(Register 0x103, Bits[7:6]). The remaining components, RZERO,
• N0 = 400
CZERO, and CPOLE1 are external to the AD9576 and are configured
by the user.
Data Sheet AD9576
AD9576 The dual VCO dividers provide flexibility for the output
LF 660Ω INTERNAL
19 frequencies. VCO Divider M0 drives the Q0, Q1, Q2, Q3, and
15kΩ QZD channel output drivers, whereas VCO Divider M1 only
3.9nF 16pF drives the Q1 and Q2 channel dividers.
120nF The VCO dividers, M0 and M1, have a synchronous reset function
LDO_BYP
13993-025
20 that must be exercised after power-up or a change in divide
value to guarantee proper operation. Under normal operation,
Figure 25. 8 kHz PFD PLL0 External Loop Filter there is no need for the user to reset the M0 or M1 dividers
When using an 8 kHz PFD rate, an external loop filter must be manually because they are automatically reset by the VCO0
used. Figure 25 shows the recommended external loop filter design calibration process. However, when the user wants to change
for an 8 kHz PFD rate. With a VCO0 frequency of 2500 MHz the M0 or M1 divider value after the VCO0 calibration, the user
and a charge pump current of 888 μA (Register 0x102, Bits[7:0] = must either reissue a VCO0 calibration (see the PLL0 VCO
0xDE), the loop filter has a bandwidth of 520 Hz with 70° of Calibration section) or manually reset the VCO dividers by
phase margin. executing the following sequence:
PLL0 Internal VCO 1. Force a reset on the M0 VCO divider. Set Register 0x120,
PLL0 incorporates a low phase noise LC tank VCO0. This VCO Bit 0 = 1.
has 256 frequency bands spanning from 2.375 GHz to 2.75 GHz. 2. Force a reset on the M1 VCO divider. Set Register 0x120,
A VCO calibration is required to select the appropriate operating Bit 4 = 1.
frequency band for the programmed divider configuration (see 3. Issue an input/output (I/O) update. Write Register 0x00F =
the PLL0 VCO Calibration section). 0x01.
4. Clear the M0 VCO divider reset state. Set Register 0x120,
VCO0 has an integrated low dropout (LDO) linear voltage Bit 0 = 0.
regulator that isolates VCO0 from possible external supply 5. Clear the M1 VCO divider reset state. Set Register 0x120,
voltage variations. The regulated LDO voltage appears at the Bit 4 = 0.
LDO_BYP pin. To ensure stability, connect a 0.47 μF chip 6. Issue an I/O update. Write Register 0x00F = 0x01.
monolithic ceramic capacitor between this pin and ground.
Note that, if only a single VCO divider value is changed, only
Note that using the LDO_BYP pin to power an external circuit
that divider must be reset. However, resetting both dividers
may degrade VCO0 performance.
simultaneously ensures synchronization between the respective
PLL0 VCO Dividers (M0 and M1) downstream dividers.
The internal VCO of PLL0 operates in the 2.5 GHz range, which is PLL0 VCO Calibration
too high to clock the output channel dividers directly. The AD9576
The AD9576 on-chip VCO0 must be calibrated to ensure
has two independent VCO dividers, M0 and M1, used to scale
proper operation over process and temperature. Calibration
down the internal VCO frequency to an acceptable range for
centers the VCO0 control voltage at the VCO0 frequency
the output channel dividers. Both the M0 and M1 dividers are
established after PLL0 locks, allowing VCO0 a sufficient
programmable over the range of 2 to 11 using the M0 divide
operating range to maintain lock over extremes of temperature
ratio and M1 divider ratio bits, Register 0x121, Bits[3:0] and
and voltage.
Register 0x121, Bits[7:4], respectively. The values of these bits
and their corresponding functions are shown in Table 27. The VCO calibration routine works by comparing the VCO
feedback clock to the reference input clock. This requires that a
Table 27. VCO Divider Ratio Decode valid reference input clock is present at the time of calibration.
M0 or M1 Divider Ratio Bit Field Value Divider Operation Therefore, the LOR status indicator of the PLL0 active reference
0 to 1 Power down input is used to gate the VCO calibration operation so that it
2 to 11 Divide by this value waits for the presence of a reference input clock. Note that, in
12 to 15 Power down Loop Mode 1, the REF0/REF1 frequency may be lower than the
detection threshold of the LOR status indicator, causing the
LOR status to remain Logic 1 even with a fully valid reference.
In this case, the VCO calibration cannot be gated by the PLL0
active reference input LOR status. Therefore, the LOR gating of
the calibration is removed when operating in Loop Mode 1 with
a total feedback divide value equal to or greater than a value of
divide by 512. When these conditions are met, the calibration
still waits for the presence of a reference input clock, but no
assessment of the frequency accuracy of the signal is made prior
to the execution of the calibration.
AD9576 Data Sheet
When a PPR load is executed on power-up, an automatic Loop Mode 2 Calibration Considerations
calibration sequence is issued following the completion of the When using the PLL0 Loop 2 feedback configuration, the
load. Otherwise, a manual VCO0 calibration must be initiated VCO0 calibration requires special treatment because the M0
via the PLL0 calibration bit (Register 0x100, Bit 3). Setting the and QZD dividers stop during VCO0 calibration (a result of the
PLL0 calibration bit to Logic 1 initiates a calibration of VCO0. automatic synchronization function imposed during calibration),
The PLL0 calibration bit is not a self clearing bit. Therefore, which prevents the calibration circuitry from receiving the
the bit must be reset to Logic 0 before a subsequent manual required feedback clock edges. Therefore, the calibration
calibration can be initiated. The PLL0 calibration in progress controller detects that Loop 2 is in effect and automatically
bit (Register 0x020, Bit 2) indicates when a VCO0 calibration is switches to the Loop 0 configuration to perform the VCO0
occurring. A Logic 1 reported on the PLL0 calibration in progress calibration sequence. Upon completion of the calibration
bit indicates a VCO0 calibration is active, whereas a Logic 0 sequence, the calibration controller automatically restores the
indicates normal PLL0 operation. Loop 2 configuration. Because the calibration controller uses
After a successful calibration, the VCO operates in a condition the Loop 0 configuration, the N0 divider is necessarily in the
with optimal margin to maintain lock in operation across the feedback path during the calibration sequence. Therefore, the
entire specified temperature range, which includes margin for a user must program the value of the N0 divider before initiating
deviation in the reference input clock carrier up to ±200 ppm. a calibration sequence in the Loop 2 configuration, where
However, if the active reference clock frequency exceeds this N0 = M0 × QZD
limit, or if the user alters the nominal VCO operating frequency
by reconfiguring the reference scaling section or feedback divider, That is, N0 must match the product of the M0 divider and the
the ability for the PLL to maintain lock over temperature may be QZD channel divider. The N0 divider is programmed via the N0
compromised. If this occurs, an additional VCO calibration is divider integer value bits (Register 0x107, Bits[7:0]).
necessary. To accomplish this, write the following register If M0 × QZD > 255, the N0 feedback divider alone is not large
sequence: enough to be used during calibration. To properly calibrate
1. Clear the VCO0 calibration bit. Write Register 0x100, VCO0, manually force the AD9576 to operate in Loop 1 during
Bit 3 = 0. calibration and, following the completion of the calibration,
2. Issue an I/O update. Write Register 0x00F = 0x01. manually force the AD9576 back to Loop 2. Perform these
3. Initiate a manual VCO0 calibration. Write Register 0x100, actions using the following sequence:
Bit 3 = 1. 5. Clear the VCO0 calibration bit. Write Register 0x100,
4. Issue an I/O update. Write Register 0x00F = 0x01. Bit 3 = 0.
6. Set Loop Mode 1. Write Register 0x101, Bits[2:1] = 1.
Note that, during the first VCO0 calibration sequence after a
7. Issue an I/O update. Write Register 0x00F = 0x01.
PLL0 reset or chip level reset, the calibration controller holds
8. Initiate a manual VCO0 calibration. Write Register 0x100,
the distribution section in sync mode (the channel dividers are
Bit 3 = 1.
held in reset and the output drivers are static) until the calibration
terminates. Therefore, no output signals appear until the VCO0
10. Wait for the calibration to complete, the poll until
calibration sequence terminates, as indicated by a Logic 1 to
Register 0x020, Bit 2 = 0.
Logic 0 transition of the PLL0 calibration in progress bit
11. Set Loop Mode 2. Write Register 0x101, Bits[2:1] = 2.
(Register 0x020, Bit 2).
The VCO0 calibration process requires approximately 98,500
cycles of the PFD to complete. Therefore, the calibration time Note that, in this case, the calibration feedback path consists of
(tVCO_CAL) depends on the input frequency to the PFD (fPFD) as the cascade of the N0 and N0A dividers. Therefore, the user
follows: must program the N0 and N0A dividers such that
N0 × N0A = M0 × QZD
9.85 × 10 4
tVCO_CAL =
f PFD
Data Sheet AD9576
PLL0 Lock Detect Note that, when the ×2 frequency multiplier is in use, the active
The PLL0 lock detector is a frequency detector that evaluates reference signal must have a duty cycle close to 50%. Otherwise,
the frequency difference between the feedback and reference spurious artifacts (harmonics) may propagate through the signal
inputs to the PFD. A lock condition is indicated when the path and appear at the output of PLL1.
average difference between the feedback and reference inputs is PLL1 Loop Configuration
less than a magnitude of 16 ppm. The PLL0 lock detect process The VCO1 frequency is a function of the PFD1 input frequency
requires approximately 65,500 cycles of the PFD to complete. and the values programmed into the registers associated with
Therefore, the lock detect time (tLDET) depends on the input the N1 feedback divider.
frequency to the PFD (fPFD) as follows:
fVCO1 = fPFD1 × N1
6.5  104
tLDET = The divider value of N1 is set by programming the N1 divider
f PFD ratio bits (Register 0x201, Bits[7:0]) to a value between 4 and 255.
PLL1 INTEGER-N PLL The overall frequency translation is as follows:
PLL1 is a fully integrated integer-N PLL consisting of six f REF N1
functional elements: a reference frequency prescalar, a PFD, a fOUT = 
R1 Qx
charge pump, an internal loop filter, a VCO, and a feedback divider.
PLL1 allows two independent reference clock input signals. PLL1 where:
provides up to three outputs segregated into two groups. Each fOUT is the frequency at the output driver, OUTx (OUT8, OUT9,
group has a dedicated channel divider allowing the device to or OUT10).
produce two different output frequencies simultaneously. Figure 26 fREF is the frequency of the active reference (REF0, REF1, or REF2).
shows the functional block diagram of PLL1. Qx is the channel divider (Q3 or Q4) associated with OUTx.
PLL1 R1 is the divider value used to scale the input reference frequency
INTEGER-N
÷N1
and is an element of the following set: {½, 1, 1.5, 2, 3, 4, 6, 8}.
Note the value of ½ is the result of selecting the ×2 reference
multiplier (see the PLL1 Reference Frequency Scaling section).
REF2
PFD
×2 CHARGE VCO1
PLL0 ACTIVE PUMP
LPF
N1 is an element of the following set: {4, 5, …, 255}.
REFERENCE
13993-026
÷R1
Qx is the divide value of the channel divider and is an element
of the following set: {1, 2, …, 64}.
Figure 26. PLL1 Block Diagram
PLL1 PFD, Charge Pump, and Loop Filter
PLL1 Reference Frequency Scaling
The PFD determines the phase difference between the edges of
The frequency of the active input reference (REF0, REF1, or the reference divider output and the feedback divider output.
REF2) is scalable via the PLL1 doubler enable bit (Register 0x202, The circuit provides two pulse-width modulated output signals:
Bit 0) and the R1 divider ratio bits (Register 0x202, Bits[3:1]). This up and down. These up/down pulses drive the charge pump
scaling allows the user to scale the input reference frequency to circuit. The instantaneous phase error determines the amount
satisfy the input range of the PFD. When the PLL1 doubler of charge delivered from the charge pump to the loop filter. The
enable bit is set to Logic 0, the frequency appearing at the input closed-loop of the PLL typically drives the frequency and phase
to the PFD, fPFD1, is a function of the active reference frequency difference between the two PFD input signals towards zero.
scaled by the reference input divider.
The loop filter affects the dynamic characteristics of a PLL (for
fREF example, lock time and stability). PLL1 has a fully integrated
fPFD1 =
R1 internal loop filter that establishes the loop dynamics for a PFD
where: frequency between 10 MHz and 50 MHz. The charge pump
fREF is the frequency of the active reference (REF0, REF1, or current and loop filter components are automatically adjusted
REF2). based on the programmed N1 feedback divide value to
R1 is the value of the R1 reference input divider value. maintain a nearly constant loop bandwidth over a range of
feedback dividers values. Table 28 shows the PLL1 closed-loop
When the PLL1 doubler enable bit is set to Logic 1, the frequency
bandwidth as a function of the N1 divide value.
appearing at the input to the PFD, fPFD1, is the active reference
frequency multiplied by a factor of 2. Table 28. PLL1 Closed-Loop Bandwidth
N1 Divide Value Nominal Closed Loop Bandwidth (MHz)
fPFD1 = fREF × 2
4 to 23 3.5
where fREF is the frequency of the active reference (REF0, REF1, 24 to 47 1.75
or REF2). 48 to 255 1
AD9576 Data Sheet
PLL1 Internal VCO of the input clock period. For Output Group 0, if the M0 output
The PLL1 internal VCO has a frequency range of 750 MHz to clock is 625 MHz, the LSB of this bit field corresponds to 800 ps
825 MHz and a nominal gain of 750 MHz/V, allowing the PLL to of phase delay and an initial phase offset value of 23 delays the
support ±3.125% clock margining for an 800 MHz VCO first edge of the Q0 divider output by 18.4 ns relative to an
frequency and a 25 MHz PFD frequency by updating the initial phase offset value of 0. To guarantee the initial phase
feedback divider on-the-fly. offset of the Qx channel divider, a synchronization command
must be executed on Qx after the corresponding Qx initial
PLL1 Lock Detect phase bit field is programmed by the user. Refer to the
The PLL1 lock detect is a phase detector that evaluates the Synchronization section for additional information regarding
phase difference between the feedback and reference inputs to this process.
PFD1. The lock detector operates at the PFD rate, which is
Each channel divider can be independently powered down
fVCO1 using the respective power-down bits. These bits are the Q0 PD
fPFD1 =
N1 (Register 0x140, Bit 6), Q1 PD (Register 0x146, Bit 6), Q2 PD
(Register 0x14A, Bit 6), Q3 PD (Register 0x240, Bit 6), and Q4
A lock condition is indicated when the phase error between the
PD (Register 0x244, Bit 6) bits in the serial register. When the
feedback and reference inputs to PFD1 is less than 3.25 ns.
channel divider power-down bit is set to Logic 1, the respective
Typically, a lock condition for PLL1 is declared 420 µs after the
channel divider powers down, whereas Logic 0 powers up the
release of RESET, assuming a valid input clock is available. channel divider for normal operation.
OUTPUT DISTRIBUTION Input Sources
The output distribution is segmented into five groups of outputs The Q0 and QZD channel dividers are driven solely by the M0
(Output Group 0, Output Group 1, Output Group 2, Output VCO divider output clock. The Q1 and Q2 channel dividers can
Group 3, and Output Group 4) with each group having several be driven by the output clock from either VCO divider, M0 or
output drivers that share a channel divider. The output groups, M1. The user must select which VCO divider is driving the Q1
corresponding channel dividers, output drivers, and input clock and Q2 channel dividers using the Qx source bits (Register 0x147,
source(s) are shown in Table 29. Bit 6 for the Q1 source and Register 0x14B, Bit 6 for the Q2 source).
Table 29. Distribution Output Groups Programming either Qx source bit to Logic 0 selects the M0 output
clock as the input clock for the channel divider, whereas Logic 1
Output Channel Output Frequency
Group Divider Driver(s) Source(s) selects the M1 output clock as the channel divider input clock.
0 Q0 OUT0, OUT1, PLL0 (M0) The Q3 channel divider can be driven by the output clock from
OUT2, OUT3 the M0 VCO divider or the output of PLL1, fVCO1. The user must
1 Q1 OUT4, OUT5 PLL0 (M0 and M1) select which input is driving the Q3 channel divider using the
2 Q2 OUT6, OUT7 PLL0 (M0 and M1) Q3 source bit (Register 0x241, Bit 6). Programming this bit to
3 Q3 OUT8, OUT9 PLL0 (M0), PLL1 Logic 0 selects the PLL1 output as the Q3 input, whereas a
output, PLL1 Logic 1 selects the M0 output as the Q3 input.
reference
4 Q4 OUT10 PLL1 output, PLL1 The Q4 channel divider is driven solely by the output of PLL1, fVCO1.
reference Synchronization
Channel Dividers Each channel divider has a sync input that allows the divider to
There are a total of six, 6-bit integer channel dividers: Q0, Q1, be placed into a known phase, determined by its initial phase bit
Q2, Q3, Q4, and QZD. The divider ratio is programmable using field. When the sync input is Logic 1, the divider is held in reset,
the Qx divider ratio bits, Register 0x140, Bits[5:0], Register 0x146, which establishes the initial phase of the divider. When the sync
Bits[5:0], Register 0x14A, Bits[5:0], Register 0x240, Bits[5:0], input is logic low, the divider is in normal operation. Coordinating
Register 0x244, Bits[5:0], and Register 0x110, Bits[5:0] for Q0, the Logic 1 to Logic 0 transition of the sync input of multiple
Q1, Q2, Q3, Q4, and QZD, respectively. Each channel divider can channel dividers to occur simultaneously results in a deterministic
operate in divide ratios of 1 to 64. The default divide ratio for initial phase alignment between the outputs of said dividers.
each channel divider is divide by 4, with the exception of QZD, Provided the set of synchronized dividers share a common input
which has a default value of 1. clock, the initial phase alignment is repeated at a rate equal to
the GCD between all channel divider outputs.
The initial phase offset for each channel divider is programmable
through the Qx initial phase bit fields: Register 0x141, Bits[5:0],
Register 0x147, Bits[5:0], Register 0x14B, Bits[5:0], Register 0x241,
Bits[5:0], Register 0x245, Bits[5:0], and Register 0x110, Bits[5:0]
for Q0, Q1, Q2, Q3, Q4, and QZD, respectively. The bit fields
each have a programming range of 0 to 63 in units of half cycles
Data Sheet AD9576
As an example, assume the Q0 output is 50 MHz and the Q1 To manually synchronize a sync domain, the user must
output is 100 MHz. The outputs have a GCD equal to 50 MHz; program the associated manual sync bit to a Logic 1 followed by
therefore, the initial phase relationship between the Q0 and Q1 a Logic 0. The following example shows the required sequence
channel divider outputs repeats every 20 ns (for example, at a for the PLL0 synchronization domain:
50 MHz rate). 13. Set the PLL0 sync bit. Write Register 0x100, Bit 2 = 1.
Consider another example: assume that the Q0 output is 50 MHz, 14. Issue an I/O update. Write Register 0x00F = 0x01.
the Q1 output is 100 MHz, and the Q2 output is 125 MHz. The 15. Clear the PLL0 sync bit. Write Register 0x100, Bit 2 = 0.
outputs have a GCD equal to 25 MHz; therefore, the initial 16. Issue an I/O update. Write Register 0x00F = 0x01.
phase relationship between the Q0, Q1, and Q2 channel divider
Note that the M0 and M1 sync domains (and therefore the PLL0
outputs repeats every 40 ns (for example, at a 25 MHz rate).
sync domain) have mask sync bits (see the Register 0x122
Four synchronization domains exist to facilitate the synch- description in Table 48). Setting a channel divider mask sync bit
ronization of multiple channel dividers. A single synchronization for a particular sync domain precludes said sync domain from
domain is a grouping of channel dividers in which the sync affecting the operation of that channel divider. For example, if
inputs of each channel divider are tied to a common control bit. the Q1, Q2, and Q3 source bits are all programmed to Logic 0,
The channel dividers are grouped based on their selected input the M0 sync domain includes the Q0, Q1, Q2, and QZD channel
source, and the four domains are as follows: dividers, the M1 sync domain does not include channel dividers,
• M0 sync domain. This domain includes all channel dividers and the PLL1 sync domain includes the Q3 and Q4 channel
that are configured to use the M0 VCO divider as the input dividers. Programming the M0 mask sync Q2 (Register 0x122,
clock source. Bit 2) to Logic 1 results in the Q2 channel divider being unaffected
• M1 sync domain. This domain includes all channel dividers by a M0 or PLL0 sync command. Programming the M1 mask
that are configured to use the M1 VCO divider as the input sync Q2 (Register 0x122, Bit 6) to Logic 1 has no functional
clock source. impact because Q2 is not a part of the M1 sync domain in this
• PLL0 sync domain. This domain includes consists of the configuration.
aggregate of the M0 and M1 sync domains. Output Driver Sources
• PLL1 sync domain. This domain includes includes all The output drivers in Output Group 0, Output Group 1, and
channel dividers that are configured to use the PLL1 Output Group 2 (see Table 29) are driven by the outputs of their
output as the input clock source respective channel divider. For example, OUT4 and OUT5 in
Each sync domain has an associated manual sync bit— Output Group 1 are driven by the output of the Q1 channel
Register 0x120, Bit 2, Register 0x120, Bit 6, Register 0x100, divider.
Bit 2, and Register 0x200, Bit 2 for the M0, M1, PLL0, and PLL1 Output Group 3 or Output Group 4 can be driven by the output
sync domains, respectively. Each manual sync bit allows user of their respective channel divider or by the PLL1 active input
control of the divider sync inputs, but there are also automatically reference. The user must select which source is driving the outputs
generated signals that are logically OR’ed with the manual sync in Output Group 3 and Output Group 4. For Output Group 3,
bits of the individual sync domains. The actions that generate this is accomplished by programming the OUT89 source bit
these automatically generated sync signals are described as (Register 0x241, Bit 7). Programming this bit to Logic 0 selects
follows, for the sync domains they affect: the Q3 output as the input for the OUT8/OUT9 output drivers,
whereas a Logic 1 selects the PLL1 active input reference as the
• M0 sync domain. Deassertion of the M0 reset bit
input to the output drivers. Note that, if the PLL1 active input
(Register 0x120, Bit 0) and deassertion of the M0 power-down
reference is selected as the source to an output group and the
bit (Register 0x120, Bit 1).
PLL1 active input reference is configured for a XTAL, the PLL1
• M1 sync domain. Deassertion of the M1 reset bit
active input reference loss of reference signal gates the output
(Register 0x120, Bit 4) and deassertion of the M1 power-
drivers of the output group.
down bit (Register 0x120, Bit 5).
• PLL0 sync domain. Completion of the first VCO0 calibration The input clock source for OUT10 is selected via the OUT10
routine issued after the deassertion of any chip level reset source bit (Register 0x245, Bit 6). Programming this bit to
or deassertion of the PLL0 reset bit (Register 0x100, Bit 0). Logic 0 selects the output of the Q4 divider as the clock source
Note that this automatic sync affects both the M0 and M1 for OUT10, whereas a Logic 1 selects the PLL1 active input
sync domains. reference as the OUT10 clock source.
• PLL1 sync domain. Deassertion of the PLL1 reset bit Note that, if none of the 3-channel output drivers, OUT8,
(Register 0x200, Bit 0). OUT9, or OUT10, use the PLL1 output as their input, then the
PLL1 power-down signal is automatically asserted, and PLL1 is
powered down.
AD9576 Data Sheet
Output Power-Down When OUT8, OUT9, or OUT10 is operating in the CMOS
The eight output drivers, OUT0 through OUT7, have independent output format, the user must also select the polarity of the
power-down control via the corresponding OUTx PD bits in the output driver via the OUTx CMOS polarity bits (Register 0x242,
serial register. For example, the OUT0 output driver is powered Bits[3:2], Register 0x243, Bits[3:2], and Register 0x246, Bits[3:2]).
down via the OUT0 PD bit (Register 0x142, Bit 2). When the For example, the polarity of OUT8 is controlled via the OUT8
corresponding OUTx PD bit is set to Logic 1, OUTx is powered CMOS polarity bits (Register 0x242, Bits[3:2]). Table 51
down; otherwise, it is powered on and functionally operational. contains a detailed description of the OUTx CMOS polarity bit
fields for OUT8, OUT9, and OUT10.
The three output drivers, OUT8, OUT9, and OUT10 have
independent power-down control via the corresponding OUTx Additionally, when the output format for OUT8, OUT9, or
enable bits. For example, the OUT8 output driver is powered OUT10 is configured for either LVDS or full swing CMOS, the
down via the OUT8 enable bit (Register 0x242, Bit 0). When the driver strength of the output is determined by the OUTx drive
corresponding driver enable bit is set to Logic 0, the OUTx strength bits (Register 0x242, Bit 1, Register 0x243, Bit 1, and
output driver is powered down. Likewise, OUTx is powered up Register 0x246, Bit 1 for OUT8, OUT9, and OUT10, respectively).
when the corresponding OUTx PD bit is set to Logic 1. When operating in the LVDS output format (OUTx driver
Output Driver Format format bit = 010), programming this bit to Logic 0 results in an
output drive strength of 3.5 mA, whereas a Logic 1 produces a
The OUT0 through OUT7 output channels support HSTL,
drive strength of 4.5 mA.
LVDS, and 1.8 V CMOS outputs. The user has independent
control of the operating mode of each of the eight output When operating in the full swing CMOS output format,
channels via the OUTx driver format bits in the serial register programming this bit to Logic 0 results in nominal output drive
(for example, Register 0x142, Bits[1:0] for OUT0). Table 49 strength, whereas a Logic 1 results in low output drive strength
contains a detailed description of the OUTx driver format bit that can be used to minimize coupling effects. The drive strength
fields for OUT0 through OUT7. The differential resistive load bit only applies to the full swing CMOS format. The 1.8 V swing
termination is removed for 1.8 V CMOS outputs. When an CMOS output drivers only operate in a low drive strength mode.
OUT0 through OUT7 driver is configured as 1.8 V CMOS, the PPRx PINS
positive and negative pins are in a complimentary phase
The AD9576 makes use of four PPRx pins to configure the
relationship (for example, 180° offset).
device. Internal circuitry scans the PPRx pins for the presence
Use HSTL format and ac couple the output signal for an of resistor terminations and configures the device accordingly.
LVPECL-compatible output. A PPRx pin scan occurs automatically as part of the power-on
The OUT8, OUT9, and OUT10 output channels also support reset sequence (see the Power-On Reset (POR) section) or
HSTL, LVDS, and 1.8 V CMOS outputs as well as HCSL and following the assertion of the RESET pin.
full swing CMOS outputs. The user has independent control of the Each PPRx pin controls a specific function or functional block
operating mode of OUT8, OUT9, and OUT10 through the OUTx within the device (see Table 30). The power-on configuration of
driver format bits (Register 0x242, Bits[6:4], Register 0x243, a functional block depends on the scanned state of the corre-
Bits[6:4], and Register 0x246, Bits[6:4]). Table 51 contains a sponding PPRx pin. The scan of a PPRx pin identifies one of
detailed description of the OUTx driver format bit fields for eight possible states based on an external pull-up or pull-down
OUT8, OUT9, and OUT10. resistor (maximum 10% tolerance) per Table 31.
When OUT8, OUT9, or OUT10 are operating in the CMOS
Table 30. PPRx Pin Function Assignments
output format, the user must select the output swing level via
the OUTx CMOS enable full swing bits (Register 0x242, Bit 7, Mnemonic Pin No. Function Assignment
Register 0x243, Bit 7, and Register 0x246, Bit 7). For example, PPR0 24 Input receiver configurations, PLL1
source, and PLL input doubler states
OUT8 is controlled via the OUT8 CMOS enable full swing bit
PPR1 26 OUT10 configuration
(Register 0x242, Bit 7). When the OUTx CMOS enable full
PPR2, PPR3 32, 56 PLL0 frequency translation and OUT0
swing bit is set to Logic 0, the CMOS ouput of the corresponding to OUT9 configuration
driver has a 1.8 V swing. When the OUTx CMOS enable full
swing bit is set to Logic 1, the CMOS swing is determined by
the voltage applied to VDD_OUTx. Only set the OUTx CMOS
enable full swing bits to Logic 1 if the associated output format
is configured as CMOS.
Data Sheet AD9576
Device programming consists of connecting the appropriate For details regarding the device configuration based on the
value programming resistors to the PPRx pins and terminating the scanned PPRx states, refer to the description of each PPRx pin
resistors to VDD_x or GND (per Table 31). For example, Figure 27 in the following sections.
shows how to program PPR0 to State 3. PPR0—Reference Clock Input Configuration
Table 31. PPRx State The PPR0 pin controls the configuration of the reference clock
PPRx State Resistance Terminus inputs (REF0, REF1, REF2) and the select line of the PLL1
0 820 Ω GND reference input mux. Table 32 associates each PPR0 state with a
1 1.8 kΩ GND particular reference input configuration and PLL1 source
2 3.9 kΩ GND combination.
3 8.2 kΩ GND PPR1—OUT10 Configuration
4 820 Ω VDD
The PPR1 pin controls the frequency, driver format, and source
5 1.8 kΩ VDD
of OUT10, which requires the PLL1 reference input, and therefore
6 3.9 kΩ VDD
REF2, if used, to be 25 MHz. Note that, if REF0/REF1 is configured
7 8.2 kΩ VDD
to a frequency other than 25 MHz, the PLL1 source must be
configured as REF2. Table 33 associates each PPR1 state with a
particular OUT10 configuration.
AD9576 PPR2 and PPR3—REF0/REF1 Frequency and OUT0 to
OUT9 Configuration
24
PPR0
The PPR2 and PPR3 pins control the configuration of the REF0
13993-027
8.2kΩ
and REF1 input frequency, PLL0, OUT0 to OUT9 driver format
Figure 27. PPRx Programming Resistor Example and frequency, and the OUT8 to OUT9 source. Table 34 associates
each combination of PPR2 and PPR3 states with a particular
predefined frequency translation.
Table 32. PPR0—Input Receiver Formats and PLL1 Source

PPR0 State REF0/REF1 Input Configuration REF2 Input Configuration PLL1 Source PLL0 Doubler PLL1 Doubler
0 XTAL 2.5 V/3.3 V CMOS PLL0 active reference Enabled Disabled
1 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS PLL0 active reference Enabled Disabled
2 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS PLL0 active reference Disabled Disabled
3 Differential/1.8 V LVCMOS 2.5 V/3.3 V CMOS PLL0 active reference Disabled Disabled
4 XTAL XTAL REF2 Enabled Disabled
5 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS REF2 Enabled Disabled
6 Differential/1.8 V LVCMOS XTAL REF2 Enabled Disabled
7 Differential/1.8 V LVCMOS 2.5 V/3.3 V CMOS REF2 Enabled Disabled
Table 33. PPR1—OUT10 Configuration

PPR1 State OUT10 Frequency (MHz) OUT10 Format OUT10 Source
0 25 2.5 V/3.3 V CMOS PLL1 reference
1 33.3 (100/3) 2.5 V/3.3 V CMOS PLL1 output
2 50 2.5 V/3.3 V CMOS PLL1 output
3 66.67 (200/3) 2.5 V/3.3 V CMOS PLL1 output
4 100 LVDS PLL1 output
5 133.3 (400/3) LVDS PLL1 output
AD9576 Data Sheet
Table 34. PPR2 and PPR3—REF0/REF1 Frequency and OUT0 to OUT9 Configuration 1
REF0/REF1 OUT0 to OUT3 OUT4 to OUT5 OUT6 to OUT7 OUT8 to OUT9
PPR2 PPR3 Frequency Frequency Frequency Frequency Frequency
State State (MHz) (MHz) Format (MHz) Format (MHz) Format (MHz) Format Source
0 0 25 Disabled N/A Disabled N/A Disabled N/A Disabled N/A N/A
0 1 25 156.25 HSTL 156.25 HSTL 156.25 HSTL 156.25 HSTL PLL0
0 2 25 156.25 LVDS 156.25 LVDS 156.25 LVDS 156.25 LVDS PLL0
0 3 25 156.25 HSTL 156.25 HSTL 100 HSTL 25 2.5 V/3.3 V PLL1
CMOS source
0 4 25 156.25 LVDS 156.25 LVDS 100 HSTL 25 2.5 V/3.3 V PLL1
CMOS source
0 5 25 156.25 HSTL 125 HSTL 100 HSTL 50 2.5 V/3.3 V PLL1
CMOS
CMOS source
0 7 25 156.25 LVDS 125 LVDS 100 HSTL 25 2.5 V/3.3 V PLL1
CMOS source
CMOS source
CMOS source
1 2 25 156.25 HSTL 100 HSTL 50 HSTL 125 HSTL PLL0
1 3 25 156.25 LVDS 100 LVDS 50 HSTL 125 HSTL PLL0
1 4 25 156.25 LVDS 100 LVDS 100 LVDS 25 2.5 V/3.3 V PLL1
CMOS source
CMOS source
CMOS source
1 7 25 156.25 HSTL 100 HSTL 125 HSTL 312.5 HSTL PLL0
2 0 25 156.25 LVDS 100 LVDS 125 LVDS 312.5 LVDS PLL0
2 1 25 156.25 HSTL 312.5 HSTL 125 HSTL 25 HSTL PLL1
source
2 2 25 156.25 LVDS 312.5 LVDS 125 LVDS 25 LVDS PLL1
source
2 7 25 312.5 HSTL 100 HSTL 156.25 HSTL 156.25 HSTL PLL0
3 0 25 312.5 LVDS 100 LVDS 156.25 LVDS 156.25 LVDS PLL0
3 1 25 625 HSTL 100 LVDS 100 LVDS 156.25 HSTL PLL0
3 2 25 100 HSTL 312.5 HSTL 156.25 HSTL 125 HSTL PLL0
3 3 25 100 LVDS 312.5 LVDS 156.25 LVDS 125 LVDS PLL0
3 4 25 100 HSTL 312.5 HSTL 156.25 HSTL 25 HSTL PLL1
source
3 5 25 100 LVDS 312.5 LVDS 156.25 LVDS 25 LVDS PLL1
source
3 6 25 100 HSTL 100 HSTL 100 HSTL 100 HCSL PLL0
3 7 25 100 LVDS 100 LVDS 100 LVDS 100 HCSL PLL0
4 0 25 125 HSTL 125 HSTL 125 HSTL 125 HSTL PLL0
4 1 25 125 LVDS 125 LVDS 125 LVDS 125 LVDS PLL0
4 2 25 125 HSTL 100 HSTL 100 HSTL 100/3 HSTL PLL1
4 3 25 125 LVDS 100 LVDS 100 LVDS 100/3 LVDS PLL1
4 4 25 125 HSTL 100 HSTL 25 HSTL 25 HSTL PLL1
source
4 5 25 125 LVDS 100 LVDS 25 LVDS 25 LVDS PLL1
source
4 7 25 100 LVDS 100 LVDS 125 HSTL 25 2.5 V/3.3 V PLL1
CMOS source
5 0 25 100 HSTL 100 HSTL 125 HSTL 25 2.5 V/3.3 V PLL1
CMOS source
Data Sheet AD9576
REF0/REF1 OUT0 to OUT3 OUT4 to OUT5 OUT6 to OUT7 OUT8 to OUT9
PPR2 PPR3 Frequency Frequency Frequency Frequency Frequency
State State (MHz) (MHz) Format (MHz) Format (MHz) Format (MHz) Format Source
CMOS source
5 2 25 156.25 LVDS 50 LVDS 125 LVDS 25 2.5 V/3.3 V PLL1
CMOS source
5 3 25 100 HSTL 100 HSTL 100 HSTL 100 HCSL PLL1
5 5 25 25 HSTL 25 HSTL 25 HSTL 400 LVDS PLL1
5 6 25 156.25 HSTL 50 HSTL 125 HSTL 400 HCSL PLL1
5 7 25 156.25 LVDS 50 LVDS 125 LVDS 400 HCSL PLL1
62 02 25 70.656 HSTL 70.656 HSTL 70.656 HSTL 25 HSTL PLL1
source
62 12 25 24.576 HSTL 24.576 HSTL 24.576 HSTL 100 HCSL PLL1
2 2 25 24.576 LVDS 24.576 LVDS 24.576 LVDS 100 HCSL PLL1
6 2
2 2 25 312.5 × HSTL 156.25 × HSTL 156.25 × HSTL 100 HCSL PLL1
6 3
(33/32) (33/32) (33/32)
62 42 25 312.5 × LVDS 156.25 × LVDS 156.25 × LVDS 100 HCSL PLL1
(33/32) (33/32) (33/32)
62 52 25 148.5 HSTL 148.5 HSTL 148.5 HSTL 100 HCSL PLL1
2
6 62 25 148.5 LVDS 148.5 LVDS 148.5 LVDS 100 HCSL PLL1
63 73 19.44 625 × (33/32) HSTL 156.25 × HSTL 156.25 × HSTL 100 HCSL PLL1
(33/32) (33/32)
73 03 19.44 625 × (33/32) LVDS 156.25 × LVDS 156.25 × LVDS 100 HCSL PLL1
(33/32) (33/32)
73 13 19.44 156.25 HSTL 125 HSTL 50 HSTL 100 LVDS PLL1
3
7 23 19.44 156.25 LVDS 125 LVDS 50 LVDS 100 LVDS PLL1
73 33 30.72 156.25 HSTL 50 HSTL 125 HSTL 25 2.5 V/3.3 V PLL0
CMOS
73 43 30.72 156.25 LVDS 50 LVDS 125 LVDS 25 2.5 V/3.3 V PLL0
CMOS
73 53 30.72 156.25 HSTL 125 HSTL 50 HSTL 100 HCSL PLL1
3
7 63 30.72 156.25 LVDS 125 LVDS 50 LVDS 100 HCSL PLL1
7 7 Reserved
1
N/A means not applicable.
2
Frequency translation requires the PLL0 input doubler to be enabled. Only valid if PPR0 = 0, 1, 4, 5, 6, or 7.
3
PLL1 input must be 25 MHz. Only valid if PPR0 = 4, 5, 6, or 7.
POWER-ON RESET (POR) sequence, which results in the configuration of the internal
Applying power to the AD9576 causes an internal power-on registers. With a reference signal applied to the input of each
reset (POR) event. A POR event allows the device to initialize to PLL, the VCO0 calibration sequence initiates, while PLL1
a known state at power-up by initiating a scan of the PPRx pins immediately begins locking to the reference. Assuming a valid
(see the PPRx Pins section). input reference signal, the PLLs eventually locks to the reference
signal(s), as indicated by assertion of the LD_0 pin and the
In general, the AD9576 follows an orderly power-on sequence LD_1 pin. These lock signals enable the prescale dividers at the
beginning with the POR circuit detecting a valid 2.5 V or 3.3 V output of each VCO, which starts the output drivers toggling
supply. This activates the internal LDO regulators. Detection of (that is, those output drivers enabled per the PPRx settings).
valid LDO voltages by the POR circuit triggers a PPRx scan
AD9576 Data Sheet
SERIAL CONTROL PORT

The AD9576 serial control port is a flexible, synchronous serial The CS (chip select) pin is an active low control that gates read
communications port that provides a convenient interface to and write operations. Assertion (active low) of the CS pin initiates
many industry-standard microcontrollers and microprocessors. a write or read operation to the AD9576 SPI port. Any number
The AD9576 serial control port is compatible with I²C and SPI. of data bytes can be transferred in a continuous stream. The
The serial control port allows read/write access to the AD9576 register address is automatically incremented or decremented
register map. based on the setting of the address ascension bit (Register 0x000).
The AD9576 uses the Analog Devices unified SPI protocol (see CS must be deasserted at the end of the last byte transferred,
the Analog Devices Serial Control Interface Standard) implement- thereby ending the stream mode. When CS is high, the SDIO
ation, but does not support a 4-wire protocol with dedicated input pin goes into a high impedance state.
and output data pins. Rather, only a 3-wire mode with a single, Implementation Specific Details
bidirectional data pin is supported. The SPI port configuration
The following product specific items are defined in the unified
is programmable via Register 0x000. This register is a part of
SPI protocol:
the SPI control logic rather than in the register map and is
distinct from the I2C Register 0x000. • Analog Devices unified SPI protocol revision: 1.0
Although the AD9576 supports both the SPI and I C serial port
2 • Chip type: 0x5
protocols, only one is active following power-up (as determined • Product ID: 0x014F
by the SP0 and SP1 pins during the start-up sequence). The only • Physical layer: 3-wire supported and 2.5 V and 3.3 V
way to change the serial port protocol is to reset (or power cycle) operation supported
the device. • Optional single-byte instruction mode: not supported
• Data link: not used
SPI/I²C PORT SELECTION
• Control: not used
Because the AD9576 supports both SPI and I2C protocols, the
active serial port protocol depends on the logic state of the SP0 Communication Cycle—Instruction Plus Data
and SP1 pins at reset or power-on. See Table 35 for the serial The unified SPI protocol consists of a two part communication
port configuration decode. cycle. The first part is a 16-bit instruction word that is coincident
with the first 16 SCLK rising edges and a payload. The instruction
Table 35. SPI/I²C Serial Port Setup
word provides the AD9576 serial control port with information
SP1 SP0 SPI/I²C Address
regarding the payload. The instruction word includes the R/W
Floating Floating SPI with PPRx load
bit that indicates the direction of the payload transfer (that is, a
0 Floating I²C, 0111001 (0x39)
read or write operation). The instruction word also indicates
1 Floating I²C, 0111010 (0x3A)
the starting register address of the first payload byte.
Floating 0 I²C, 0111011 (0x3B)
0 0 I²C, 0111100 (0x3C) Write
1 0 I²C, 0111101 (0x3D) If the instruction word indicates a write operation, the payload
Floating 1 I²C, 0111110 (0x3E) is written into the serial control port buffer of the AD9576. Data
0 1 I²C, 0111111 (0x3F) bits are registered on the rising edge of SCLK. Generally, it does
1 1 SPI not matter what data is written to blank registers; however, it is
customary to use 0s. Note that the user must verify that all
SPI SERIAL PORT OPERATION reserved registers within a specific range have a default value of
Pin Descriptions 0x00; however, Analog Devices makes every effort to avoid
The SCLK (serial clock) pin serves as the serial shift clock. This having reserved registers with nonzero default values.
pin is an input. SCLK synchronizes serial control port read and Most of the serial port registers are buffered. Therefore, data
write operations. The rising edge SCLK registers write data bits, written into buffered registers does not take effect immediately.
and the falling edge registers read data bits. The SCLK pin An additional operation is needed to transfer buffered serial
supports a maximum clock rate of 50 MHz. control port contents to the registers that actually control the
The SPI port supports only a 3-wire (bidirectional) hardware device. This transfer is accomplished with an I/O update operation,
configuration. This 3-wire mode uses the SDIO (serial data which is performed by writing a Logic 1 to Register 0x00F, Bit 0
input/output) pin for transferring data in both directions. Both (this bit is an autoclearing bit). The user can change as many
MSB first and LSB first data formats are supported and are register bits as desired before executing an I/O update. The I/O
software programmable. update operation transfers the buffer register contents to their
active register counterparts.
Data Sheet AD9576
Read 1. Immediately after the LSB first bit(s) is set, subsequent serial
If the instruction word indicates a read operation, the next control port operations are LSB first.
N × 8 SCLK cycles clock out the data starting from the address Address Ascension
specified in the instruction word. N is the number of data bytes If the address ascension bits (Register 0x0000, Bit 5 and Bit 2)
read. The read back data is driven to the pin on the falling edge are zero, the serial control port register address decrements
and must be latched on the rising edge of SCLK. Blank registers from the specified starting address toward Address 0x0000.
are not skipped over during read back.
If the address ascension bits (Register 0x0000, Bit 5 and Bit 2)
A read back operation takes data from either the serial control are one, the serial control port register address increments from
port buffer registers or the active registers, as determined by the starting address toward Address 0x7FFF. Reserved addresses
Register 0x001, Bit 5. are not skipped during multi-byte input/output operations;
SPI Instruction Word (16 Bits) therefore, write the default value to a reserved register and 0s to
The MSB of the 16-bit instruction word is R/W, which indicates unmapped registers. Note that it is more efficient to issue a new
whether the instruction is a read or a write. The next 15 bits are write command than to write the default value to more than
the register address (A14 to A0), which indicates the starting two consecutive reserved (or unmapped) registers.
register address of the read/write operation (see Table 37). Table 36. Streaming Mode (No Addresses Skipped)
SPI MSB/LSB First Transfers Address Ascension Stop Sequence
The AD9576 instruction word and payload can be MSB first or Increment 0x0000 … 0x7FFF
LSB first. The default for the AD9576 is MSB first. The LSB first Decrement 0x7FFF … 0x0000
mode can be set by writing a 1 to Register 0x0000, Bit 6 and Bit
Table 37. Serial Control Port, 16-Bit Instruction Word

MSB LSB
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Table 38. Serial Control Port Timing

Parameter Description
tDS Setup time between data and the rising edge of SCLK
tDH Hold time between data and the rising edge of SCLK
tSCLK Period of the clock
tS Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle)
tC Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)
tHIGH Minimum period that SCLK should be in a logic high state
tLOW Minimum period that SCLK should be in a logic low state
tDV SCLK to valid SDIO (see Figure 36)
CS
SCLK DON'T CARE DON'T CARE
SDIO DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE
13993-028
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA
Figure 28. Serial Control Port Write—MSB First, Address Decrement, Two Bytes of Data
AD9576 Data Sheet
tDS tHIGH
tS tSCLK tC
tDH
CS tLOW
13993-029
SDIO DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE
Figure 29. Timing Diagram for Serial Control Port Write—MSB First
CS
SCLK
tDV
13993-030
SDIO DATA BIT N DATA BIT N – 1
Figure 30. Timing Diagram for Serial Control Port Register Read—MSB First
CS
SDIO DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE
13993-031
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA
Figure 31. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data
CS tS tC
tSCLK
tHIGH tLOW
tDS
SCLK
tDH
SDIO BIT N BIT N + 1

13993-032
Figure 32. Timing Diagram for Serial Control Port—Write
I2C SERIAL PORT OPERATION The AD9576 I2C port consists of a serial data line (SDA) and a
The I2C interface is popular because it requires only two pins serial clock line (SCL). In an I2C bus system, the AD9576 is
and easily supports multiple devices on the same bus. Its main connected to the serial bus (data bus SDA and clock bus SCL) as
disadvantage is programming speed, which is 400 kbps maximum. a slave device; that is, no clock is generated by the AD9576. The
The AD9576 I2C port design uses the I2C fast mode; however, it AD9576 uses direct 16-bit memory addressing instead of more
supports both the 100 kHz standard mode and 400 kHz fast mode. common 8-bit memory addressing.
The AD9576 does not strictly adhere to every requirement in The AD9576 allows up to seven unique slave devices to occupy
the original I2C specification. In particular, specifications such the I2C bus. These are accessed via a 7-bit slave address
as slew rate limiting and glitch filtering are not implemented. transmitted as part of an I2C packet. Only the device with a
Therefore, the AD9576 is I2C-compatible, but may not be fully matching slave address responds to subsequent I2C commands.
I2C compliant. Table 35 lists the supported device slave addresses.
Data Sheet AD9576
I2C Bus Characteristics Data Transfer Process
2
A summary of the various I C abbreviations appears in Table 39. The master initiates data transfer by asserting a start condition,
which indicates that a data stream follows. All I2C slave devices
Table 39. I2C Bus Abbreviation Definitions connected to the serial bus respond to the start condition.
Abbreviation Definition
The master then sends an 8-bit address byte over the SDA line,
S Start
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
Sr Repeated start
This bit determines the direction of the data transfer, that is,
P Stop
whether data is written to or read from the slave device (0 =
A Acknowledge
write and 1 = read).
A No acknowledge
W Write The peripheral whose address corresponds to the transmitted
R Read
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
The transfer of data is shown in Figure 33. One clock pulse is for data to be read from or written to it. If the R/W bit is 0, the
generated for each data bit transferred. The data on the SDA master (transmitter) writes to the slave device (receiver). If the
line must be stable during the high period of the clock. The R/W bit is 1, the master (receiver) reads from the slave device
high or low state of the data line can change only when the (transmitter).
clock signal on the SCL line is low. The format for these commands is described in the Data
Transfer Format section.
SDA
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (eight bits) from either master (write
SCL mode) or slave (read mode) followed by an acknowledge bit
from the receiving device. The number of bytes that can be
13993-033
DATA LINE CHANGE

STABLE; OF DATA
DATA VALID ALLOWED transmitted per transfer is unrestricted. In write mode, the first
Figure 33. Valid Bit Transfer two data bytes immediately after the slave address byte are the
internal memory (control registers) address bytes, with the high
Start/stop functionality is shown in Figure 33. The start
address byte first. This addressing scheme gives a memory
condition is characterized by a high to low transition on the
address of up to 216 − 1 = 65,535. The data bytes after these two
SDA line while SCL is high. The master always generates the
memory address bytes are register data written to or read from
start condition to initialize a data transfer. The stop condition is
the control registers. In read mode, the data bytes after the slave
characterized by a low to high transition on the SDA line while
address byte are register data written to or read from the control
SCL is high. The master always generates the stop condition to
registers.
terminate a data transfer. Every byte on the SDA line must be
eight bits long. Each byte must be followed by an acknowledge When all the data bytes are read or written, stop conditions are
bit; bytes are sent MSB first. established. In write mode, the master (transmitter) asserts a stop
condition to end data transfer during the clock pulse following
The acknowledge bit (A) is the ninth bit attached to any 8-bit
the acknowledge bit for the last data byte from the slave device
data byte. An acknowledge bit is always generated by the
(receiver). In read mode, the master device (receiver) receives
receiving device (receiver) to inform the transmitter that the
the last data byte from the slave device (transmitter) but does
byte has been received. It is done by pulling the SDA line low
not pull SDA low during the ninth clock pulse. This is known as
during the ninth clock pulse after each 8-bit data byte.
a nonacknowledge bit. By receiving the non-acknowledge bit,
The no acknowledge bit (A) is the ninth bit attached to any 8-bit the slave device knows that the data transfer is finished and
data byte. A no acknowledge bit is always generated by the enters idle mode. The master then takes the data line low
receiving device (receiver) to inform the transmitter that the during the low period before the 10th clock pulse, and high
byte has not been received. It is done by leaving the SDA line during the 10th clock pulse to assert a stop condition.
high during the ninth clock pulse after each 8-bit data byte.
A start condition can be used in place of a stop condition.
After issuing a nonacknowledge bit, the AD9576 I2C state
Furthermore, a start or stop condition can occur at any time,
machine goes into an idle state.
and partially transferred bytes are discarded.
AD9576 Data Sheet
SDA
SCL
S P
13993-034
START CONDITION STOP CONDITION
Figure 34. Start and Stop Conditions
SDA MSB
ACK FROM ACK FROM
SLAVE RECEIVER SLAVE RECEIVER
13993-035
SCL 1 2 3 TO 7 8 9 1 2 3 TO 7 8 9 10
S P
Figure 35. Acknowledge Bit
SDA MSB
ACK FROM ACK FROM
SLAVE RECEIVER SLAVE RECEIVER
13993-036
SCL 1 2 3 TO 7 8 9 1 2 3 TO 7 8 9 10
S P
Figure 36. Data Transfer Process (Master Write Mode, 2-Byte Transfer)
SDA
ACK FROM NONACK FROM

MASTER RECEIVER MASTER RECEIVER
13993-037
SCL 1 2 3 TO 7 8 9 1 2 3 TO 7 8 9 10
S P
Figure 37. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First Acknowledge From Slave
Data Sheet AD9576
Data Transfer Format
The write byte format is used to write a register address to the
RAM starting from the specified RAM address.
S Slave W A RAM address high byte A RAM address low byte A RAM A RAM A RAM A P
address Data 0 Data 1 Data 2
The send byte format is used to set up the register address for subsequent reads.
S Slave address W A RAM address high byte A RAM address low byte A P
The receive byte format is used to read the data byte(s) from RAM starting from the current address.
S Slave address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A P
The read byte format is the combined format of the send byte and the receive byte.
S Slave W A RAM address A RAM address A Sr Slave R A RAM A RAM A RAM A P
address high byte low byte address Data 0 Data 1 Data 2
I²C Serial Port Timing
SDA
tF tLOW tR tSU; DAT tHD; STA tR tBUF

tSP
tF
SCL
13993-038
tHD; STA tSU; STA tSU; STO
S tHD; DAT tHIGH Sr P S
Figure 38. I²C Serial Port Timing
Table 40. I2C Timing Definitions

Parameter Description
fSCL Serial clock
tBUF Bus free time between stop and start conditions
tHD; STA Repeated hold time start condition
tSU; STA Repeated start condition setup time
tSU; STO Stop condition setup time
tHD; DAT Data hold time
tSU; DAT Data setup time
tLOW SCL clock low period
tHIGH SCL clock high period
tR Minimum/maximum receive SCL and SDA rise time
tF Minimum/maximum receive SCL and SDA fall time
tSP Pulse width of voltage spikes that must be suppressed by the input filter
AD9576 Data Sheet
CONTROL REGISTER MAP

Table 41. Register Summary
Address Default
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) R/W
Serial Port Configuration Registers
0x000 SPI Soft reset LSB first Address Reserved Address LSB first Soft reset 0x00 R/W
Configuration A ascension ascension
0x001 SPI Single Reserved Read buffer Reserved Reset sans Reserved 0x00 R/W
Configuration B instruction registers register map
0x003 Chip type Reserved Chip type 0x05 R
0x004 Product ID1 Serial ID[3:0] Reserved 0x4F R
0x005 Product ID2 Serial ID[11:4] 0x01 R
0x006 Revision Device version Device revision 0x11 R
0x00B SPI version SPI version 0x00 R
0x00C Vendor ID Vendor ID[7:0] 0x56 R
0x00D Vendor ID[15:8] 0x04 R
0x00F I/O update Reserved I/O update 0x00 R/W
Status Indicator Registers
0x020 PLL status Reserved PLL0 PLL1 lock PLL0 lock 0x00 R
calibration in detect detect
progress
0x021 Reference Reserved Reference status Active REF2 LOR REF1 LOR REF0 LOR 0x00 R
reference
Chip Mode Register
0x040 Mode selection Reserved Chip PLL1 0x02 R/W
power- reference
down select
Reference Input Configuration Registers
0x080 Reference Reserved REF1 REF1 format Reserved REF0 power- REF0 format 0x00 R/W
inputs power- down
down
0x081 Reserved REF2 power- REF2 format 0x00 R/W
down
Reference Switchover Registers
0x082 Reference Reserved Disable Enable XTAL Enable soft Soft 0x00 R/W
switchover smooth redundancy reference reference
switchover switchover select select
0x083 Reference Enable Reserved Monitored Reference Reference monitor clock Error window 0x00 R/W
monitor control reference frequency monitor frequency
monitor 8 kHz
operation
PLL0 Configuration Registers
0x100 PLL0 controls Reserved PLL0 PLL0 sync PLL0 PLL0 reset 0x00 R/W
calibration power-
down
0x101 PLL0 Reserved PLL0 PLL0 loop mode N0 SDM 0x01 R/W
configuration doubler power-
enable down
0x102 PLL0 charge PLL0 charge pump current 0x8D R/W
pump current
0x103 PLL0 loop filter PLL0 RPOLE2 loop filter PLL0 RZERO loop filter PLL0 CPOLE1 loop filter 0xE8 R/W
0x104 Reserved PLL0 loop 0x00 R/W
filter
bypass
0x105 PLL0 input Reserved R0 divider ratio 0x01 R/W
divider
0x107 PLL0 fractional N0 divider integer value 0x64 R/W
feedback divider
(integer)
Data Sheet AD9576
Address Default
0x108 PLL0 fractional N0 divider fractional value 0x00 R/W
0x109 feedback divider N0 divider fractional value 0x00 R/W
(fractional)
0x10A N0 divider fractional value 0x00 R/W
0x10B PLL0 fractional N0 divider modulus value 0x00 R/W
0x10C feedback divider N0 divider modulus value 0x00 R/W
(modulus)
0x10D N0 divider modulus value 0x00 R/W
0x10E PLL0 cascaded N0A Divider Ratio 0x00 R/W
0x10F feedback divider Reserved N0A Divider Ratio[11:8] 0x00 R/W
0x110 PLL0 zero delay Reserved QZD divider ratio 0x00 R/W
0x111 feedback divider Reserved QZD initial phase 0x00 R/W
PLL0 VCO Dividers Registers
0x120 VCO dividers Reserved M1 sync M1 power- M1 reset Reserved M0 sync M0 power- M0 reset 0x20 R/W
control down down
0x121 VCO dividers M1 divider ratio M0 divider ratio 0x44 R/W
ratios
0x122 VCO dividers Reserved M1 mask M1 mask M0 mask M0 mask M0 mask sync M0 mask M0 mask 0x00 R/W
sync mask sync Q2 sync Q1 sync QZD sync Q3 Q2 sync Q1 sync Q0
PLL0 Distribution Registers
0x140 Q0 divider Reserved Q0 Q0 divider ratio 0x03 R/W
power-
down
0x141 Reserved Q0 initial phase 0x00 R/W
0x142 Channel 0 Reserved OUT0 power- OUT0 driver format 0x00 R/W
driver config- down
uration
driver config- down
uration
driver config- down
uration
driver config- down
uration
0x146 Q1 divider Reserved Q1 Q1 divide ratio 0x03 R/W
power-
down
0x147 Reserved Q1 source Q1 initial phase 0x00 R/W
driver config- down
uration
driver config- down
uration
0x14A Q2 Divider Reserved Q2 Q2 divide ratio 0x03 R/W
power-
down
0x14B Reserved Q2 source Q2 initial phase 0x00 R/W
0x14C Channel 6 Reserved OUT6 power- OUT6 driver format 0x00 R/W
driver config- down
uration
0x14D Channel 7 Reserved OUT7 power- OUT7 driver format 0x00 R/W
driver config- down
uration
AD9576 Data Sheet
Address Default
PLL1 Configuration Registers
0x200 PLL1 controls Reserved PLL1 sync PLL1 PLL1 reset 0x00 R/W
power-
down
0x201 PLL1 feedback N1 divider ratio 0x10 R/W
divider
0x202 PLL1 input Reserved R1 divider ratio PLL1 0x01 R/W
dividers doubler
enable
PLL1 Distribution Registers
power-
down
0x241 OUT89 Q3 Q3 initial phase 0x00 R/W
source source
0x242 Channel 8 OUT8 CMOS OUT8 driver format OUT8 CMOS polarity OUT8 drive OUT8 0xC1 R/W
driver config- enable full strength enable
uration swing
0x243 Channel 9 OUT9 CMOS OUT9 driver format OUT9 CMOS polarity OUT9 drive OUT9 0xC1 R/W
driver config- enable full strength enable
uration swing
power-
down
0x245 Reserved OUT10 Q4 initial phase 0x80 R/W
source
0x246 Channel 10 OUT10 OUT10 driver format OUT10 CMOS polarity OUT10 OUT10 0xC1 R/W
driver CMOS drive enable
configuration enable full strength
swing
Data Sheet AD9576
CONTROL REGISTER DESCRIPTIONS

SERIAL PORT CONFIGURATION REGISTERS (REGISTER 0x000 TO REGISTER 0x00F)
Table 42. Serial Port Configuration Registers
Address Bits Bit Name Settings Description Reset Access
0x000 7 Soft reset Mirror of Bit 0. 0x0 R/W
6 LSB first Mirror of Bit 1. 0x0 R/W
5 Address Mirror of Bit 2. 0x0 R/W
ascension
[4:3] Reserved Reserved. 0x0 R
2 Address This bit determines how the register address pointer is automatically 0x0 R/W
ascension changed in a multibyte transfer.
0 Decrement.
1 Increment.
1 LSB first This bit determines the bit order for data readback. This bit has no 0x0 R/W
effect in I2C mode.
0 Serial data stream starts with the LSB.
1 Serial data stream starts with the MSB.
0 Soft reset This bit issues a chip level reset. This bit is autoclearing. 0x0 R/W
0x001 7 Single instruction This bit disables streaming operation. For SPI transfers, this bit forces 0x0 R/W
each data byte to be preceded by a new instruction.
6 Reserved Reserved. 0x0 R/W
5 Read buffer This bit specifies the data source for serial port read commands. 0x0 R/W
registers
2 Reset sans This bit issues a chip level reset, but does not reset register map values. 0x0 R/W
register map 0 Normal operation.
1 Chip held in reset.
0x003 [7:4] Reserved Reserved. 0x0 R
[3:0] Chip type These bits are the unique identifier for the type of device. 0x5 R
0x004 [7:4] Serial ID[3:0] These bits are a unique identifier, when combined with chip type, for 0x4 R
an individual device supporting the Analog Devices serial control
interface standard.
[3:0] Reserved Reserved. 0xF R
0x005 [7:0] Serial ID[11:4] These bits are a unique identifier, when combined with chip type, for 0x1 R
an individual device supporting the Analog Devices serial control
interface standard.
0x006 [7:4] Device version These bits indicate the silicon variant of the device 0x1 R
[3:0] Device revision These bits indicate the silicon revision of the device. 0x1 R
0x00B [7:0] SPI version These bits indicate the version of the analog devices serial control 0x0 R
interface standard implemented on the device.
0x00C [7:0] Vendor ID[7:0] These bits are the unique vendor ID and are reflective of the Analog 0x56 R
Devices allocated USB vendor ID.
0x00D [7:0] Vendor ID[15:8] These bits are the unique vendor ID and are reflective of the Analog 0x4 R
Devices allocated USB vendor ID.
0x00F [7:1] Reserved Reserved. 0x0 R
0 I/O update This bit initiates a transfer of the buffered registers to the active 0x0 R/W
registers. This is an autoclearing bit.
AD9576 Data Sheet
STATUS INDICATOR REGISTERS (REGISTER 0x020 TO REGISTER 0x021)
Table 43. Status Indicator Registers
2 PLL0 calibration in This bit indicates the status of the PLL0 VCO calibration. 0x0 R
progress 0 PLL normal operation.
1 VCO calibration active.
1 PLL1 lock detect PLL1 lock detect status. 0x0 R
0 Unlocked.
1 Locked.
0 PLL0 lock detect PLL0 lock detect status. 0x0 R
0 Unlocked.
1 Locked.
[5:4] Reference status PLL0 active reference frequency indicator. If the reference monitor 0x0 R
is Inactive, this bit field indicates the relationship between the
requested reference input and the currently active reference.
00 Agreement.
11 Disagreement.
If the reference monitor is active, the following settings apply:
00 Valid.
01 Slow.
10 Fast.
11 Indeterminate fault.
3 Active reference PLL0 active reference indicator. 0x0 R
0 REF0.
1 REF1.
2 REF2 LOR Reference status indicator. 0x0 R
0 Reference present.
1 Loss of reference.
CHIP MODE REGISTER (REGISTER 0x040)

Table 44. Chip Mode Register
1 Chip power-down Chip level power-down control. 0x1 R/W
0 Enabled.
1 Powered down.
0 PLL1 reference select This bit determines the PLL1 reference input source. 0x0 R/W
0 PLL0 active reference.
1 REF2.
Data Sheet AD9576
REFERENCE INPUT CONFIGURATION REGISTERS (REGISTER 0x080 TO REGISTER 0x081)
Table 45. Reference Input Configuration Registers
0x080 7 Reserved Reserved. 0x0 R
6 REF1 power-down Input receiver power-down control. 0x0 R/W
0 Normal operation.
1 Powered down.
[5:4] REF1 format Input receiver format. 0x0 R/W
00 CMOS (VDD_x swing).
01 AC-coupled differential.
10 XTAL.
11 Reserved.
3 Reserved Reserved. 0x0 R
1 Powered down.
0 Normal operation.
10 XTAL.
11 Reserved.
1 Powered down.
0 Normal operation.
10 XTAL.
11 Reserved.
AD9576 Data Sheet
REFERENCE SWITCHOVER REGISTERS (REGISTER 0x082 TO REGISTER 0x083)
Table 46. Reference Switchover Registers
3 Disable smooth This bit sets the reference switchover mode. 0x0 R/W
switchover
0 Bounded phase transient.
1 Immediate.
2 Enable XTAL This bit requires the reference monitor to be enabled and both 0x0 R/W
redundancy switchover REF0 and REF1 to be configured as XTAL inputs.
1 Enable soft reference This bit establishes the control source of the PLL0 reference 0x0 R/W
select input mux select line. Not applicable when XTAL redundancy
switchover is enabled.
0 REF_SEL pin (Pin 3).
1 Soft reference select (Register 0x082, Bit 0).
0 Soft reference select This bit controls the PLL0 reference input mux select line. 0x0 R/W
Applicable only when the enable soft reference select = 1.
0 REF0 select.
1 REF1 select.
0x083 7 Enable reference The REF2 input clock serves as the reference monitor frequency 0x0 R/W
monitor reference.
5 Monitored frequency This bit determines the frequency being monitored by the 0x0 R/W
reference monitor.
0 REF0 and REF1 input frequency is 25 MHz.
1 REF0 and REF1 input frequency is 19.44 MHz.
4 Reference monitor This bit configures the reference monitor for an 8 kHz frequency 0x0 R/W
8 kHz operation reference and overrides the reference monitor clock frequency
bit field (Register 0x083, Bits[3:2]).
[3:2] Reference monitor These bits designate the reference monitor frequency reference 0x0 R/W
clock frequency carrier.
00 10 MHz.
01 19.44 MHz.
10 25 MHz.
11 38.88 MHz.
[1:0] Error window These bits set the frequency tolerance for a reference monitor 0x0 R/W
decision.
00 ±10 ppm.
01 ±25 ppm.
10 ±50 ppm.
11 ±100 ppm.
Data Sheet AD9576
PLL0 CONFIGURATION REGISTERS (REGISTER 0x100 TO REGISTER 0x111)
Table 47. PLL0 Configuration Registers
3 PLL0 calibration This bit issues a manual VCO calibration on a low to high 0x0 R/W
transition.
2 PLL0 sync This bit issues a distribution sync command to the dividers 0x0 R/W
driven by PLL0.
0 Normal operation.
1 Dividers held in sync.
1 PLL0 power-down PLL0 power-down control. 0x0 R/W
0 Normal operation.
1 Powered down.
0 PLL0 reset PLL0 reset control. 0x0 R/W
0 Normal operation.
1 Reset.
3 PLL0 doubler enable This bit selects the PLL0 input divider path used. 0x0 R/W
0 R0 divider output.
1 ×2.
[2:1] PLL0 loop mode These bits select the PLL0 feedback path. 0x0 R/W
00 Loop Mode 0 (single feedback divider).
01 Loop Mode 1 (cascaded feedback dividers).
10 Loop Mode 2 (fixed delay divider).
11 Reserved.
0 N0 SDM power-down N0 SDM power-down control 0x1 R/W
0 Normal operation.
1 Powered down.
0x102 [7:0] PLL0 charge pump These bits control the magnitude of the PLL0 charge pump 0x8D R/W
current current.
Total current (µA) = 4 × the bit field value.
0x103 [7:6] PLL0 RPOLE2 loop filter Internal loop filter Pole 2 resistor setting. 0x3 R/W
00 2000 Ω.
01 666 Ω.
10 400 Ω.
11 285 Ω.
[5:3] PLL0 RZERO loop filter Internal loop filter zero resistor setting. 0x5 R/W
000 1500 Ω.
001 1875 Ω.
010 2250 Ω.
011 2650 Ω.
100 3000 Ω.
101 3375 Ω.
110 3750 Ω.
111 4125 Ω.
[2:0] PLL0 CPOLE1 loop filter Internal loop filter Pole 1 capacitor setting. 0x0 R/W
000 2 pF.
001 8 pF.
010 42 pF.
011 48 pF.
100 82 pF.
101 88 pF.
110 122 pF.
111 128 pF.
AD9576 Data Sheet
0 PLL0 loop filter bypass This bit bypasses the internal loop filter. 0x0 R/W
[5:0] R0 divider ratio PLL0 reference input divide ratio. 0x1 R/W
0 Reserved.
1 to 63 Divide ratio = bit field value.
0x107 [7:0] N0 divider integer value These bits set the operating divide ratio. Divide ratio = bit 0x64 R/W
field value.
0 to 11 Invalid.
12 to 14 Valid if the SDM is disabled.
15 to 252 Valid.
253 to 255 Valid if the SDM is disabled.
0x108 [7:0] N0 divider fractional value These bits set the SDM fractional value, Bits[7:0]. 0x0 R/W
0x109 [7:0] These bits set the SDM fractional value, Bits[15:8]. 0x0 R/W
0x10A [7:0] These bits set the SDM fractional value, Bits[23:16]. 0x0 R/W
0x10B [7:0] N0 divider modulus value These bits set the SDM modulus value, Bits[7:0]. These bits 0x0 R/W
must be greater than fractional value.
0x10C [7:0] These bits set the SDM modulus value, Bits[15:8]. These bits 0x0 R/W
must be greater than fractional value.
0x10D [7:0] These bits set the SDM modulus value, Bits[23:16]. These 0x0 R/W
bits must be greater than fractional value.
0x10E [7:0] N0A Divider Ratio[7:0] These bits set the operating divide ratio. Divide ratio = bit 0x0 R/W
field value.
0 to 3 Invalid.
4 to 4095 Valid.
0x10F [7:4] Reserved Reserved. 0x0 R
[3:0] N0A Divider Ratio[11:8] These bits set the operating divide ratio. Divide ratio = bit 0x0 R/W
field value.
0 to 3 Invalid.
4 to 4095 Valid.
[5:0] QZD divider ratio PLL0 fixed delay feedback divider ratio. 0x0 R/W
Divide ratio = bit field value + 1.
[5:0] QZD initial phase PLL0 fixed delay feedback divider static phase offset. 0x0 R/W
Phase offset in units of half cycles of the input clock.
Data Sheet AD9576
PLL0 VCO DIVIDERS REGISTERS (REGISTER 0x120 TO REGISTER 0x122)
Table 48. PLL0 VCO Dividers Registers
6 M1 sync This bit issues a distribution sync command to the dividers 0x0 R/W
driven by M1.
0 Normal operation.
1 Dividers held in reset.
5 M1 power-down Divider power-down control. 0x1 R/W
0 Normal operation.
1 Powered down.
4 M1 reset Divider reset control 0x0 R/W
0 Normal operation.
1 Divider held in reset.
2 M0 sync This bit issues a distribution sync command to the dividers 0x0 R/W
driven by M0.
0 Normal operation.
1 Dividers held in reset.
1 M0 power-down Divider power-down control. 0x0 R/W
0 Normal operation.
1 Powered down.
0 M0 reset Divider reset control 0x0 R/W
0 Normal operation.
1 Divider held in reset.
0x121 [7:4] M1 divider ratio Sets operating divide ratio. 0x4 R/W
0 to 1 Powered down.
2 to 11 Divide = bit field value.
[3:0] M0 divide ratio These bits set the operating divide ratio. 0x4 R/W
2 to 11 Divide = bit field value.
6 M1 mask sync Q2 This bit sets the Divider Q2 ignore and M1 sync signal flag. 0x0 R/W
4 M0 mask sync QZD This bit sets the Divider QZD ignore and M0 sync signal flag. 0x0 R/W
AD9576 Data Sheet
PLL0 DISTRIBUTION REGISTERS (REGISTER 0x140 TO REGISTER 0x14D)
Table 49. PLL0 Distribution Registers
6 Q0 power-down Divider power-down control. 0x0 R/W
0 Normal operation.
1 Powered down.
[5:0] Q0 divider ratio These bits set the operating divide ratio. Divide ratio = bit field value + 1. 0x3 R/W
[5:0] Q0 initial phase These bits set the divider static phase offset. The phase offset is in 0x0 R/W
units of half cycles of the input clock.
2 OUT0 power-down Driver power-down control. 0x0 R/W
0 Normal operation.
1 Powered down.
[1:0] OUT0 driver format These bits select the driver format of OUT0. 0x0 R/W
00 LVDS, 3.5 mA.
01 LVDS, 4.2 mA.
10 HSTL, 8 mA.
11 1.8 V CMOS.
0 Normal operation.
1 Powered down.
00 LVDS, 3.5 mA.
01 LVDS, 4.2 mA.
10 HSTL, 8 mA.
11 1.8 V CMOS.
0 Normal operation.
1 Powered down.
00 LVDS, 3.5 mA.
01 LVDS, 4.2 mA.
10 HSTL, 8 mA.
11 1.8 V CMOS.
0 Normal operation.
1 Powered down.
00 LVDS 3.5 mA.
01 LVDS 4.2 mA.
10 HSTL 8 mA.
11 1.8 V CMOS.
0 Normal operation.
1 Powered down.
[5:0] Q1 divide ratio These bits set the operating divide ratio. Divide ratio = bit field value + 1. 0x3 R/W
Data Sheet AD9576
6 Q1 source This bit selects the divider input clock. 0x0 R/W
0 M0 output.
1 M1 output.
0 Normal operation.
1 Powered down.
00 LVDS, 3.5 mA.
01 LVDS, 4.2 mA.
10 HSTL, 8 mA.
11 1.8 V CMOS.
0 Normal operation.
1 Powered down.
00 LVDS, 3.5 mA.
01 LVDS, 4.2 mA.
10 HSTL, 8 mA.
11 1.8 V CMOS.
0x14A 7 Reserved Reserved. 0x0 R
0 Normal operation.
1 Powered down.
[5:0] Q2 divide ratio These bits set the operating divide ratio. Divide ratio = bit field value + 1. 0x3 R/W
0x14B 7 Reserved Reserved. 0x0 R
6 Q2 source This bit selects the divider input clock. 0x0 R/W
0 M0 output.
1 M1 output.
0x14C [7:3] Reserved Reserved. 0x0 R
0 Normal operation.
1 Powered down.
00 LVDS, 3.5 mA.
01 LVDS, 4.2 mA.
10 HSTL, 8 mA.
11 1.8 V CMOS.
0x14D [7:3] Reserved Reserved. 0x0 R
0 Normal operation.
1 Powered down.
00 LVDS, 3.5 mA.
01 LVDS, 4.2 mA.
10 HSTL, 8 mA.
11 1.8 V CMOS.
AD9576 Data Sheet
PLL1 CONFIGURATION REGISTERS (REGISTER 0x200 TO REGISTER 0x202)
Table 50. PLL1 Configuration Registers
2 PLL1 sync Issues a distribution sync command to dividers driven by PLL1. 0x0 R/W
0 Normal operation.
1 Dividers held in sync.
1 PLL1 power-down PLL power-down control. 0x0 R/W
0 Normal operation.
1 Power down.
0 PLL1 reset PLL reset control. 0x0 R/W
0 Normal operation.
1 PLL1 held in reset.
0x201 [7:0] N1 divider ratio These bits set the operating divide ratio. Divide value = bit field value. 0x10 R/W
0 to 3 Invalid values.
4 to 255 Valid values.
[3:1] R1 divider ratio PLL1 reference input divider. 0x0 R/W
0 Power down.
1 ÷1.
10 ÷1.5.
11 ÷2.
100 ÷3.
101 ÷4.
110 ÷6.
111 ÷8.
0 PLL1 doubler enable This bit selects the PLL1 input divider path used. 0x1 R/W
0 R1 divider output.
1 ×2.
PLL1 DISTRIBUTION REGISTERS (REGISTER 0x240 TO REGISTER 0x246)

Table 51. PLL1 Distribution Registers
0x240 7 Reserved Reserved. Always configure this bit to the default value. 0x1 R/W
0 Normal operation.
1 Powered down.
[5:0] Q3 divider ratio These bits set the operating divide ratio. Divide ratio = bit field 0x3 R/W
value + 1.
0x241 7 OUT89 source This bit selects the OUT8 and OUT9 input clock. 0x0 R/W
0 Q3 divider output.
1 PLL1 active reference.
6 OUT10 source This bit selects the divider input clock. 0x0 R/W
0 PLL1 output.
1 M0 output.
[5:0] Q3 initial phase These bits select the divider static phase offset. The phase offset is 0x0 R/W
in units of half cycles of the input clock.
Data Sheet AD9576
0x242 7 OUT8 CMOS This bit determines the full swing of the OUT8 CMOS driver. Set this 0x1 R/W
enable full swing bit only if the associated output format is configured as CMOS.
0 1.8 V swing.
1 Full swing.
000 Tristate.
001 HSTL.
010 LVDS.
011 HCSL.
100 CMOS (both outputs active).
101 CMOS (positive output only).
110 CMOS (negative output only).
111 Reserved.
[3:2] OUT8 CMOS These bits set the polarity of the full swing CMOS output driver. 0x0 R/W
polarity 00 Noninverted, inverted.
01 Inverted, inverted.
10 Noninverted, noninverted.
11 Inverted, noninverted.
1 OUT8 drive This bit selects the drive strength of the OUT8 driver and is only 0x0 R/W
strength applicable when the output format is configured as LVDS or full
swing CMOS.
0 CMOS—nominal drive; LVDS—3.5 mA.
1 CMOS—low drive; LVDS—4.5 mA.
0 OUT8 enable Output driver enable control. 0x1 R/W
0 Power down.
1 Enable.
0x243 7 OUT9 CMOS This bit determines the swing of the OUT9 CMOS driver. Set this bit 0x1 R/W
enable full swing only if the associated output format is configured as CMOS.
0 1.8 V swing.
1 Full swing.
[6:4] OUT9 driver These bits select the driver format of OUT9. 0x4 R/W
format 000 Tristate.
001 HSTL.
010 LVDS.
011 HCSL.
111 Reserved.
1 OUT9 drive This bit selects the drive strength of the OUT9 driver and is only applic- 0x0 R/W
strength able when the output format is configured as LVDS or full swing CMOS.
0 Power down.
1 Enable.
AD9576 Data Sheet
0 Normal operation (default). The Q4 divider works normally.
1 Powered down. The Q0 divider is powered down.
[5:0] Q4 divider ratio These bits set the operating divide ratio. Divide ratio = bit field value + 1. 0x3 R/W
6 Q4 source This bit selects the OUT10 input clock source. 0x0 R/W
1 PLL1 selected reference input.
0 Divider, Q4, output.
[5:0] Q4 initial phase These bits set the divider static phase offset. The phase offset in 0x0 R/W
0x246 7 OUT10 CMOS This bit determines the full swing of the OUT10 CMOS driver. Only 0x1 R/W
enable full swing set this bit if the associated output format is configured as CMOS.
0 1.8 V swing.
1 Full swing.
[6:4] OUT10 driver These bits select the driver format of OUT10. 0x4 R/W
format 000 Tristate.
001 HSTL.
010 LVDS.
011 HCSL.
111 Reserved.
1 OUT10 drive This bit selects the drive strength of the OUT10 driver and is only 0x0 R/W
strength applicable when the output format is configured as LVDS or full
swing CMOS.
0 Power down.
1 Enable.
Data Sheet AD9576
APPLICATIONS INFORMATION
INTERFACING TO CMOS CLOCK OUTPUTS INTERFACING TO LVDS AND HSTL CLOCK
Apply the following general guidelines when using the single- OUTPUTS
ended 1.8 V or 3.3 V CMOS clock output drivers. LVDS and HSTL both employ a differential output driver. The
Design point to point nets such that a driver has only one recommended termination circuit for LVDS and HSTL drivers
receiver on the net, if possible. This allows simple termination appears in Figure 41.
3.3V
schemes and minimizes ringing due to possible mismatched
impedances on the net. Series termination at the source is 50Ω 100Ω
10Ω
generally required to provide transmission line matching and/or CMOS
5pF
to reduce current transients at the driver. 100Ω
13993-041
The value of the series termination depends on the board
design and timing requirements (typically 10 Ω to 100 Ω). Figure 41. CMOS Output with Far End Termination
CMOS outputs are limited in terms of the capacitive load or
See the AN-586 Application Note for more information about
trace length that they can drive. Typically, trace lengths less
LVDS.
than 6 inches are recommended to preserve signal rise/fall
times and signal integrity. INTERFACING TO HCSL CLOCK OUTPUTS
60.4Ω HCSL uses a differential open-drain architecture. The open-
1.0 INCH
10Ω
CMOS drain architecture necessitates the use of an external termination
MICROSTRIP resistor. Figure 42 shows the typical method for interfacing to
5pF HCSL drivers.
13993-039
GND INDEPENDENT
UNCOUPLED 50Ω
Figure 39. Series Termination of CMOS Output TRANSMISSION LINES
HCSL
Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the AD9576 do not supply enough current RECEIVER
to provide a full voltage swing with a low impedance resistive,
13993-042
50Ω 50Ω
far end termination, as shown in Figure 40. Ensure that the
impedance of the far end termination network matches the PCB Figure 42. HCSL Output Termination
trace impedance and provides the desired switching point. The
In some cases, the fast switching capability of HCSL drivers
reduced signal swing may still meet receiver input requirements
results in overshoot and ringing. The alternative HCSL interface
in some applications. This can be useful when driving long
shown in Figure 43 can mitigate this problem via a small series
trace lengths on less critical nets.
resistor, typically in the 10 Ω to 30 Ω range.
INDEPENDENT
UNCOUPLED 50Ω INDEPENDENT
TRANSMISSION LINES UNCOUPLED 50Ω
TRANSMISSION LINES
100Ω HCSL
10Ω TO 30Ω
13993-040
HSTL/LVDS RECEIVER 10Ω TO 30Ω RECEIVER

DRIVER
13993-043
50Ω 50Ω
Figure 40. LVDS or HSTL Output Termination
Figure 43. Alternate HCSL Output Termination
AD9576 Data Sheet
POWER SUPPLY beads with approximately 75 Ω impedance at 100 MHz are
The AD9576 requires a power supply of 2.5 V ± 5% or 3.3 V ± suitable for use with Pin 52 and Pin 57.
10%. The Specifications section gives the performance expected The layout of the AD9576 evaluation board is a good example
from the AD9576 with the power supply voltage within this of how to route power supply traces and where to place bypass
range. The absolute maximum range of −0.3 V to +3.6 V, with capacitors and ferrite beads.
respect to GND, must never be exceeded on the VDD_x pins. The exposed metal pad on the AD9576 package is an electrical
Follow good engineering practice in the layout of power supply connection, as well as a thermal enhancement. For the device to
traces and the ground plane of the PCB. Bypass the power function properly, the pad must be properly attached to ground
supply on the PCB with adequate capacitance (>10 µF). Bypass (GND). The PCB acts as a heat sink for the AD9576; therefore,
the AD9576 with adequate capacitors (0.1 µF) at all power pins this GND connection provides a good thermal path to a larger
as close as possible to the device. heat dissipation area, such as a ground plane on the PCB.
In addition to these bypass capacitors, the AD9576 evaluation POWER AND GROUNDING CONSIDERATIONS AND
board uses six ferrite beads between the 2.5 V (or 3.3 V) source POWER SUPPLY REJECTION
and Pin 29, Pin 35, Pin 41, Pin 46, Pin 52, and Pin 57. Although Many applications seek high speed and performance under
these ferrite beads may not be needed for every application, the less than ideal operating conditions. In these application
use of these ferrite beads is strongly recommended. At a circuits, the implementation and construction of the PCB is as
minimum, include a place for the ferrite beads (as close to the important as the circuit design. Proper RF techniques must be
bypass capacitors as possible) and populate the board with used for device selection, placement, and routing, as well as for
0402, 0 Ω resistors. By doing so, there is a place for the ferrite power supply bypassing and grounding to ensure optimum
beads, if needed. Ferrite beads with low (<0.7 Ω) dc resistance performance.
and approximately 600 Ω impedance at 100 MHz are suitable
for use with Pin 29, Pin 35, Pin 41, and Pin 46, while ferrite
Data Sheet AD9576
OUTLINE DIMENSIONS
DETAIL A
9.10 (JEDEC 95)
9.00 SQ 0.30
8.90 0.25
PIN 1 0.18
INDICATOR 49 64
P IN 1
1
IN D IC ATO R AR E A OP T IO N S
48 (SEE DETAIL A)
0.50 EXPOSED 6.30

BSC PAD
6.20 SQ
6.10
33 16
0.45
32 17
TOP VIEW BOTTOM VIEW 0.20 MIN

0.40
7.50 REF
0.35
0.80
FOR PROPER CONNECTION OF
0.75 END VIEW 0.05 MAX THE EXPOSED PAD, REFER TO
0.70 0.02 NOM THE PIN CONFIGURATION AND
COPLANARITY FUNCTION DESCRIPTIONS
SEATING 0.08 SECTION OF THIS DATA SHEET.
PLANE 0.203 REF
08-27-2018-A
PKG-004559
COMPLIANT TO JEDEC STANDARDS MO-220-WMMD
Figure 44. 64-Lead Lead Frame Chip Scale Package [LFCSP]

9 mm × 9 mm and 0.75 mm Package Height
(CP-64-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD9576BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP] CP-64-17
AD9576BCPZ-REEL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP] CP-64-17
AD9576/PCBZ Evaluation Board
Z = RoHS-Compliant Part.
1
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D13993-0-9/18(A)

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Dual PLL,

Asynchronous Clock Generator

Integrated loop filter (requires a single external capacitor) REF2

Rev. A Document Feedback

7/2016—Revision 0: Initial Version

SUPPLY CURRENT SPECIFICATIONS

POWER DISSIPATION SPECIFICATIONS

REFERENCE SWITCHOVER OUTPUT DISTURBANCE SPECIFICATIONS

CLOCK DISTRIBUTION OUTPUTS SPECIFICATIONS

Figure 2. CMOS Timing, Single-Ended, 10 pF Load

Figure 3. LVDS, HSTL, and HCSL Timing, Differential

OUT8 TO OUT10 CHANNEL CYCLE TO CYCLE CLOCK JITTER SPECIFICATIONS

STATUS OUTPUT PINS CHARACTERISTICS—LD_0, LD_1, REF_SW, REF_STATUS, REF_ACT

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 19. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

OUTPUT VOLTAGE (V)

100 1k 10k 100k 1M 10M 0 5 10 15 20 25

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

RELATIVE PHASE (Degrees)

Figure 18. Reference Smooth Switchover Phase Disturbance for OUT0 at

÷N1 9 1.8V CMOS

Figure 20. Detailed Functional Block Diagram

OVERVIEW The AD9576 provides up to 11 output channel clocks (OUT0 to

÷N0A Loop 2: Zero Delay 10

Figure 21. PLL0 Functional Block Diagram

Figure 22. PLL0 Loop Configuration 0 fOUT = 

configure the N0 modulus value to the largest possible value as

Table 32. PPR0—Input Receiver Formats and PLL1 Source

Table 33. PPR1—OUT10 Configuration

SERIAL CONTROL PORT

Table 37. Serial Control Port, 16-Bit Instruction Word

Table 38. Serial Control Port Timing

SCLK DON'T CARE DON'T CARE

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA

SCLK DON'T CARE DON'T CARE

SCLK DON'T CARE DON'T CARE

SDIO BIT N BIT N + 1

Figure 32. Timing Diagram for Serial Control Port—Write

DATA LINE CHANGE

Figure 34. Start and Stop Conditions

Figure 35. Acknowledge Bit

ACK FROM NONACK FROM

I²C Serial Port Timing

tF tLOW tR tSU; DAT tHD; STA tR tBUF

Figure 38. I²C Serial Port Timing

Table 40. I2C Timing Definitions

CONTROL REGISTER MAP

CONTROL REGISTER DESCRIPTIONS

CHIP MODE REGISTER (REGISTER 0x040)

PLL1 DISTRIBUTION REGISTERS (REGISTER 0x240 TO REGISTER 0x246)

Termination at the far end of the PCB trace is a second option.

HSTL/LVDS RECEIVER 10Ω TO 30Ω RECEIVER

0.50 EXPOSED 6.30