EZ-BIST User Manual

v3.3
 EZ-BIST User Manual v3.3

Contents
1. Introduction to EZ-BIST ............................................................... 1
1.1. Features ......................................................................................... 1
1.2. Architecture .................................................................................... 2
2. EZ-BIST Command Options and Parameters ............................. 3
2.1. Invoke EZ-BIST with the GUI Mode ............................................... 4
2.2. Input Verilog Files ........................................................................... 5
2.3. Specify the Working Path ............................................................... 7
2.4. Auto-Identify the Memory Model .................................................... 8
2.5. The Generate the ROM Signature ................................................. 9
2.6. Template File Generator ................................................................. 9
2.7. Input BFL File ............................................................................... 10
2.8. Insert MBIST to Design ................................................................ 10
2.9. Specify Top Module ...................................................................... 10
2.10. Disable Clock Tracing ................................................................... 12
2.11. Input UDM File.............................................................................. 12
2.12. Generate UDM File in GUI Mode ................................................. 13
2.13. Integrate Multiple MBIST Circuits ................................................. 18
2.14. Generate UDM File with Library File ............................................ 18
2.15. Generate UDM File with Configuration File .................................. 19
2.16. Parsing Type Definition ................................................................ 20
2.17. Fault Free ..................................................................................... 20
2.18. RCF Generator ............................................................................. 21
2.19. STIL Format .................................................................................. 21
3. EZ-BIST BFL Options ................................................................. 22
3.1. OPTION Function Block ............................................................... 22
3.2. MBIST Function Block .................................................................. 35
4. EZ-BIST Output Files.................................................................. 59
4.1. Self-MBIST Related Files ............................................................. 59
4.2. Insert MBIST Related Files........................................................... 60
4.3. Generate Folders ......................................................................... 61
4.4. Makefile ........................................................................................ 62
4.5. Macro File ..................................................................................... 64
5. BII File ......................................................................................... 66
5.1. Integrator Function Block ............................................................. 66
5.2. Testbench Function Block ............................................................ 75
6. Appendixes ................................................................................. 80
6.1. “Include” Case .............................................................................. 80

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6.2. Parsing Mode ............................................................................... 80

6.3. *.rcf File ........................................................................................ 80
6.4. Supported Testing Algorithm ........................................................ 81
6.5. Statistics in TSMC SP Memory .................................................... 84

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List of Figures
Figure 1-1 EZ-BIST Operation Flow Diagram ...................................................... 2
Figure 2-1 EZ-BIST Command Options ............................................................... 3
Figure 2-2 EZ-BIST GUI Mode ............................................................................ 4
Figure 2-3 Verilog File Path ................................................................................. 5
Figure 2-4 File-list File Example .......................................................................... 6
Figure 2-5 Work Path........................................................................................... 7
Figure 2-6 Memchecker Information .................................................................... 8
Figure 2-7 The Example of *_gold_signature.txt .................................................. 9
Figure 2-8 EZ-BIST Template Generator ............................................................. 9
Figure 2-9 Top Module Name .............................................................................11
Figure 2-10 User Defined Memory ...................................................................... 12
Figure 2-11 Open UDM GUI ................................................................................ 13
Figure 2-12 Support Batches Adding and Multiple Formats ................................. 14
Figure 2-13 Memory Parameter Settings ............................................................. 15
Figure 2-14 IO Editing through EZ-BIST .............................................................. 16
Figure 2-15 IO Adding Rapidly Using Drag & Drop .............................................. 16
Figure 2-16 Delete IO with Right Click ................................................................. 17
Figure 2-17 User Define Memory Generation ...................................................... 17
Figure 2-18 UDM Configuration File Example ..................................................... 19
Figure 3-1 OPTION Function Block ................................................................... 22
Figure 3-2 Block Diagram of System Design with MBIST Inserted .................... 24
Figure 3-3 Clock Sub Function Block................................................................. 26
Figure 3-4 Group Function Block ....................................................................... 28
Figure 3-5 Open Memory Info File ..................................................................... 30
Figure 3-6 Example of Memory Info File ............................................................ 31
Figure 3-7 Support Batches Adding and Multiple Formats ................................. 31
Figure 3-8 Memory Info Setting Information ...................................................... 32
Figure 3-9 PHYSICAL Sub Function Block ........................................................ 33
Figure 3-10 MBIST Function Block ...................................................................... 35
Figure 3-11 Example of Synchronous/Asynchronous Circuit ............................... 38
Figure 3-12 Example of ATPG Circuit .................................................................. 39
Figure 3-13 Commands for Programmable Algorithm Function ........................... 39
Figure 3-14 The Example Loop Test Waveform ................................................... 41
Figure 3-15 Example of Retention Time Option in testbech.v .............................. 45
Figure 3-16 Implementation of Bypass Circuit by Wire ........................................ 47
Figure 3-17 Implementation of Bypass Circuit by Register .................................. 47
Figure 3-18 Example of Register Sharing ............................................................ 48

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Figure 3-19 Clock Architecture of clock_function_hookup Option ........................ 49

Figure 3-20 Clock Architecture of clock_switch_of_memory Option .................... 49
Figure 3-21 Diagnosis Fail Memory Information .................................................. 50
Figure 3-22 Diagnosis Fail Time Information ....................................................... 50
Figure 3-23 Default Algorithm Function Block...................................................... 52
Figure 3-24 select_elem_testing .......................................................................... 53
Figure 3-25 Select Testing Elements Sub Function Block ................................... 54
Figure 3-26 BFL TechNode .................................................................................. 56
Figure 3-27 BFL Setting File ................................................................................ 57
Figure 3-28 Run the BFL Setting File .................................................................. 58
Figure 4-1 Clock Gating Logic for Simulation and Synthesis ............................. 65
Figure 4-2 Clock Gating Cell with Waveform ..................................................... 65
Figure 5-1 Load BII ............................................................................................ 66
Figure 5-2 Options of Integrator Function Block ................................................ 67
Figure 5-3 Hookup Sub Function Block ............................................................. 70
Figure 5-4 BII File Hookup Information Table in *.integ File ............................... 71
Figure 5-5 The Example of Port Connection...................................................... 72
Figure 5-6 The Example of Wire Connection ..................................................... 73
Figure 5-7 Group Sub Function Block................................................................ 74
Figure 5-8 Testbench Function Block................................................................. 76
Figure 5-9 Initial_sequence Sub Function Block ................................................ 77
Figure 5-10 Example of BII Setting Content ........................................................ 78
Figure 5-11 Run BII Setting File .......................................................................... 79
Figure 5-12 The Status Window When BII Flow is Completed ............................ 79

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List of Tables
Table 1-1 EZ-BIST Features............................................................................... 1
Table 1-2 EZ-BIST Input Files ............................................................................ 2
Table 1-3 EZ-BIST Output Files ......................................................................... 2
Table 3-1 Clock Information ............................................................................. 27
Table 3-2 Commands for Programmable Algorithm.......................................... 40
Table 3-3 BG Field Definition ........................................................................... 42
Table 3-4 Example of Bit Inverse ..................................................................... 42
Table 3-5 Example of Column Inverse ............................................................. 43
Table 3-6 Example of User-defined Background and Test Pattern ................... 44
Table 3-7 Supported Units of Retention Time ................................................... 46
Table 3-8 Fixed Four Memory Address ............................................................ 51
Table 3-9 Fixed Two Memory Address ............................................................. 51
Table 3-10 Format of March CW Element .......................................................... 55
Table 4-1 Self-MBIST Related Files ................................................................. 59
Table 4-2 Insert MBIST Related Files ............................................................... 60
Table 4-3 Generated Folder ............................................................................. 61
Table 4-4 Commands of Makefile ..................................................................... 62
Table 6-1 Testing Algorithms for SRAM in EZ-BIST ......................................... 81
Table 6-2 Testing Algorithms for ROM in EZ-BIST ........................................... 83
Table 6-3 The Default Setting of BFL file .......................................................... 84
Table 6-4 Synthetic Area of default.bfl .............................................................. 85
Table 6-5 Area Comparison Table .................................................................... 87

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Type conversion in this document

Conversion Meaning for use

Items in the user interface that you select or click and text
Bold
that you type into the user interface
<Italic> Variables in commands, code syntax, and path names
Courier File name
“” Emphasize the meaning
Color in blue The outputs from EZ-BIST tool presenting in blue color
… Omitted material in a line of code
Omitted lines in code and report examples
…

[] Optional items in syntax descriptions to specify

() Explanations or to clarify meaning
{} Repeatable items in syntax descriptions
| Separated the individual item in syntax descriptions

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1. Introduction to EZ-BIST

EZ-BIST is an EDA tool that can generate the test circuit for MBIST (Memory Built-In
Self-Test), providing total solutions including comprehensive test algorithms, auto-
grouping mechanism, and auto-integration mechanism for MBIST circuits and the
original circuit. It is easy for users to generate optimized MBIST circuits.

1.1. Features

As shown in Table 1-1, EZ-BIST supports several features. For more details, please
refer to Application Notes.
Table 1-1 EZ-BIST Features

Feature Description
It is used to guarantee that memory can execute normally
POT Power_On-Test after powered on, EZ-BIST supports the POT function for
users to implement the POT design.
ACT can trace the clock root to the clock source of memory
modules and classify those memories into different clock
Auto-Clock
ACT domains. This mechanism not only saves time of
Tracing
connecting clock sources manually but also helps users to
trace the clock in an easier way during creating MBIST.
BUF is designed for IP/Harden implementation. Users can
BUF Bottom-Up Flow insert MBIST in an individual module. Then, integrate these
individual modules in the top module.
Auto-Gating To reduce power consumption, EZ-BIST supports AGC for
AGC Clock Cell users to insert gate cells and MUX in front of MBIST
Insertion Flow automatically.
In general, MBIST only shows the results of pass or fail
after MBIST executes memory testing. To analyze memory
defects, EZ-BIST supports memory diagnosis to collect
Diagnosis
DIAG related information such as memory failure addresses,
Function
failure patterns, etc. In addition to collecting information,
EZ-BIST diagnosis can also assign diagnosis buffer sizes
and control the diagnosis timing.

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1.2. Architecture

Figure 1-1 shows the operation flow of EZ-BIST.

Figure 1-1 EZ-BIST Operation Flow Diagram

EZ-BIST input files include the files listed below:

Table 1-2 EZ-BIST Input Files
Top HDL Design Top HDL design with memory models
Memory Module Verilog files of memory models
UDM Files User-defined memory files

EZ-BIST output files include the files listed below:

Table 1-3 EZ-BIST Output Files
Inserted Design Integrated MBIST circuits with the top HDL design
Synthesis Scripts Synthesis scripts for users to synthesize
MBIST Verilog Design Generated MBIST circuits design
Fault Memory Generated fault memory models
This is used to verify functional correctness of MBIST and
circuits with a pre-defined error bit memory.
Testbench Testbench of MBIST circuits simulation

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2. EZ-BIST Command Options and Parameters

Users can execute EZ-BIST commands with the options, --help or -h, to know all the
options supported by EZ-BIST. Figure 2-1 shows an example of executing EZ-BIST
with option -h and this chapter will introduce these options. The upper section is the
command list. The lower section is the command descriptions.

usage: ezBist [-h] [-bii INTEGRATE_FILE] [-bfl BFL_FILE]

[-f RUN_FILE [RUN_FILE ...]] [-v VERILOG_FILE [VERILOG_FILE ...]]
[-W DIR] [-top MODULE] [-I] [--genmeminfo]
[-integ FILE [FILE ...]] [-u FILE [FILE ...]] [-pm Verilog type]
[--integrator] [--faultfree] [--ug UDM_FILE config_FILE]
[--rcfg Addr_length Data_width output_FILE] [--tempgen]
[--memchecker] [--memlib2udm MEMLIB_FILE]
[--bflconfig [BFL_FILE]] [--biiconfig [BII_FILE]]
[--pathconv work_path] [--STILloopformat work_path]
[--latchgo_hier latchgo_data meminfo] [--udmgui [UDMGUI]]
[--meminfogui [MEMINFO]]

optional arguments:

-h, --help show this help message and exit

-bii INTEGRATE_FILE input BII file
-bfl BFL_FILE input BFL file
-f RUN_FILE [RUN_FILE ...] input run file(s)
-v VERILOG_FILE [VERILOG_FILE ...] input 4 verilog file(s)
-W DIR specify working path
-top MODULE, -T MODULE specify top module
-I, --insert insert BIST to design

(……………………………………………………………………………………………………)
Figure 2-1 EZ-BIST Command Options

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2.1. Invoke EZ-BIST with the GUI Mode

Usage: --gui
Description: This option is used to invoke EZ-BIST with the GUI mode.
Example: $ ezBist --gui

Figure 2-2 EZ-BIST GUI Mode

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2.2. Input Verilog Files

Figure 2-3 Verilog File Path

Usage: -v [VERILOG_PATH]
Description: This option specifies the paths of Verilog design files. The design
files here include “system design files” and “memory models”. EZ-
BIST provides an auto-insertion function to integrate MBIST circuits
into the original system design. For this reason, users need to
provide the whole design files rather than the memory files only.
This option supports either reading one Verilog file or reading all
files in the working directory. It also supports the file-list file format
*.f. Users can integrate all design files into a single file-list file and
read it through EZ-BIST commands. EZ-BIST will read design files
automatically. The file-list file also supports +define+, +incdir+, and
the -y options.

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Example 1: $ ezBist -v vlog_1

EZ-BIST will read the Verilog files in vlog_1 directory.
Example 2: $ ezBist -v vlog_1/file1.v vlog_2/file4.v
EZ-BIST will read the file1.v in vlog_1 directory and file4.v
in vlog_2 directory.
Example 3: $ ezBist -v filelist.f
EZ-BIST will read the designs in fielist.f. Figure 2-4 is an
example of the file-list file.

-v ./memory/rf_2p_24x28.v
-v ./memory/sram_sp_4096x64.v
-v ./memory/rom_6144_64.v
-v ./memory/rf_sp_128x22.v
-v ./memory/sram_dp_1024x64.v
-v ./memory/rf_2p_24x56.v
-v ./memory/sram_sp_2048x64.v
-v ./memory/sram_sp_640x32.v
-v ./memory/rf_2p_64x64.v
-v ./memory/rf_2p_72x14.v
-v ./memory/sram_sp_1024x32.v
-v ./memory/RA1RW_D2048_W128_BE_RE.v
-v ./memory/RA1RW_D2048_W140_BE_RE.v
-v ./memory/RA1RW_D1024_W128_BE_RE.v

./top.v
Figure 2-4 File-list File Example

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2.3. Specify the Working Path

Usage: -W [WORK_PATH]
Description: This option is for setting the output directory of EZ-BIST execution
results.
Example 1: $ ezBist -v [VLOG_PATH]/[file_1].v -W [WORK_PATH]
EZ-BIST will read the file_1.v design file and save output results
into WORK_PATH.
Example 2: $ ezBist -v [VLOG_PATH]/[file_1].v
Without the -W option, EZ-BIST will save all generated results into
the current working directory.

Figure 2-5 Work Path

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2.4. Auto-Identify the Memory Model

Usage: --memchecker
Description: This option is used to execute EZ-BIST memory checker to identify
memory models defined by users with the -v option.
Example: $ ezBist --memchecker -f filelist.f
Users can check if there is a memory model that cannot be
identified by reviewing the output messages as Figure 2-6.

Input file(s):
[1] /home /workspace/project/memchecker/memory/rom_6144_64.v
[2] /home//workspace/project/memchecker/memory/rf_2p_24x56.v
[3] /home//workspace/project/memchecker/memory/sram_sp_4096x64.v
[4] /home//workspace/project/memchecker/memory/sram_sp_640x32.v
[5] /home//workspace/project/memchecker/memory/sram_sp_2048x64.v
[6] /home//workspace/project/memchecker/memory/rf_2p_72x14.v
[7] /home//workspace/project/memchecker/memory/RA1RW_D2048_W140…
[8] /home//workspace/project/memchecker/memory/RA1RW_D2048_W128…
[9] /home//workspace/project/memchecker/memory/sram_sp_1024x32.v
[10] /home//workspace/project/memchecker/memory/rf_sp_128x22.v
[11] /home//workspace/project/memchecker/top.v
[12] /home//workspace/project/memchecker/memory/sram_dp_1024x64.v
[13] /home//workspace/project/memchecker/memory/RA1RW_D1024_W128…
[14] /home//workspace/project/memchecker/memory/rf_2p_24x28.v
[15] /home//workspace/project/memchecker/memory/rf_2p_64x64.v
Valid file(s):
[1] /home//workspace/project/memchecker/memory/rom_6144_64.v
[2] /home//workspace/project/memchecker/memory/rf_2p_24x56.v
[3] /home//workspace/project/memchecker/memory/sram_sp_4096x64.v
[4] /home//workspace/project/memchecker/memory/sram_sp_640x32.v
[5] /home//workspace/project/memchecker/memory/sram_sp_2048x64.v
[6] /home//workspace/project/memchecker/memory/rf_2p_72x14.v
[7] /home//workspace/project/memchecker/memory/RA1RW_D2048_W140_BE_RE.v
[8] /home//workspace/project/memchecker/memory/RA1RW_D2048_W128_BE_RE.v
[9] /home//workspace/project/memchecker/memory/sram_sp_1024x32.v
[10] /home//workspace/project/memchecker/memory/rf_sp_128x22.v
[11] /home//workspace/project/memchecker/memory/sram_dp_1024x64.v
[12] /home//workspace/project/memchecker/memory/rf_2p_24x28.v
[13] /home//workspace/project/memchecker/memory/rf_2p_64x64.v
Unrecognized file(s):
[1] /home//workspace/project/memchecker/top.v

Figure 2-6 Memchecker Information

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2.5. The Generate the ROM Signature

Usage: --memchecker
Description: This option is used to execute the EZ-BIST memory checker to
generate a golden ROM signature with the -v [ROM memory RTL
code file] option.
Example: $ ezBist --memchecker -v [ROM memory RTL code file]
Users can verify the signature created by the MBIST and compare
with the golden one.
$ ezBist --memchecker -v rom_6144_64.v

Note: The value of a signature will be saved in the

*_gold_signature.txt file (see Figure 2-7) and in the
meantime, a top.v file will be generated and replaced the
previous one in the memory folder.
rom_6144_64_verilog gold_signature = 7be4eb
Figure 2-7 The Example of *_gold_signature.txt

2.6. Template File Generator

Usage: --tempgen
Description: This option is used to generate a template file of EZ-BIST. These
template files include BII (MBIST Integration Information) files, BFL
(MBIST Feature List) files, UDM files, and PGF files as Figure 2-8.
Example: $ ezBist --tempgen

[ezBist][TEMPLATE] ezBist template generator:

1. BIST Feature List (BFL)
2. BIST Integration Information (BII)
3. User defined memory
4. Pattern Gen File (PGF)
5. Quit
[ezBist][TEMPLATE] Select an option (Enter ':q' to quit):
Figure 2-8 EZ-BIST Template Generator

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2.7. Input BFL File

Usage: -bfl BFL_FILE

Description: This option is used to define a BFL file for EZ-BIST.
Example: $ ezBist -bfl [filename].bfl -W [WORK_PATH]
After executing this command, EZ-BIST will base on the parameter
setting in the [filename].bfl file to generate MBIST related
files into WORK_PATH.

2.8. Insert MBIST to Design

Usage: -I, --insert

Description: This option is used to integrate the generated MBIST circuits into
the original system designs. Users need to define a top module
name with the -top option when using this option.
Example: $ ezBist -I -top [TOP_MODULE] -v [VLOG_PATH]/[file_1].v

2.9. Specify Top Module

Usage: -top [TOP_MODULE]

Description: This option is used to integrate the generated MBIST circuits into the
original system designs. Users need to define a top module name
with the -top option when using this option.
Example: $ ezBist -I -top [TOP_MODULE] -v [VLOG_PATH]/[file_1].v

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Figure 2-9 Top Module Name

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2.10. Disable Clock Tracing

Usage: -N, --disabletracedclk

Description: This option is used to disable the clock tracing function of EZ-BIST.
The default setting is “enabled”.
Example: $ ezBist -N -I --top [TOP_MODULE] -f file_list.f

2.11. Input UDM File

Usage: -u UDM_FILE
Description: This option is used to read the UDM files generated by users. Users
can generate UDM files when EZ-BIST cannot identify memory
models automatically. To edit a UDM file, please refer to Application
Notes for details.
Example: $ ezBist -bfl [filename].bfl -u *.udm -W [WORK_PATH]
EZ-BIST will read BFL files and UDM files in the working directory.
The output results will be saved into WORK_PATH.

Figure 2-10 User Defined Memory

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2.12. Generate UDM File in GUI Mode

User can choose Open UDM GUI directly from BFL GUI.

Figure 2-11 Open UDM GUI

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Figure 2-12 Support Batches Adding and Multiple Formats

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Set the parameters below through GUI:

⚫ Memory basic parameter

⚫ Port read/write behavior
⚫ Test Port
⚫ IO Port, Don’t Touch Port, Repair Port

Figure 2-13 Memory Parameter Settings

(For the detailed information, please refer to Chapter 10 in Application Notes)

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Figure 2-14 IO Editing through EZ-BIST

Figure 2-15 IO Adding Rapidly Using Drag & Drop

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Figure 2-16 Delete IO with Right Click

Figure 2-17 User Define Memory Generation

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2.13. Integrate Multiple MBIST Circuits

Usage: --integrator
Description: This option is used to integrate multiple MBIST circuits.
Example: $ ezBist --integrator -bii [filename].bii -W [WORK_PATH]
EZ-BIST will refer to BII files to integrate multiple MBIST circuits
and save output results into WORK_PATH.

2.14. Generate UDM File with Library File

Usage: --memlib2udm [filename].memlib

Description: This option is used to generate UDM files from memory library files.
Example 1: $ ezBist --memlib2udm sram_512x8.memlib
EZ-BIST will generate UDM files for memory sram_512x8.

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2.15. Generate UDM File with Configuration File

Usage: --ug UDM_File config_file

Description: This option is used to generate UDM files based on the settings in
the configuration file. The configuration file is used to set different
widths for address port and data port. Figure 2-18 shows an
example of the configuration file. The first column defines the
memory model name, the second column defines the address
count, the third column defines data width, and the fourth column
defines mux.
Example: $ ezBist --ug sram_512x8.udm config.file
EZ-BIST will generate UDM files with the same type as the
sram_512x8 memory model but with different data width or address
width.

#module_name address_count data_width mux

U40LP_VHD_SRF_16X8M4B1 16 8 4
U40LP_VHD_SRF_116X38M4B1 116 38 4
U40LP_VHD_SRF_216X28M4B1 216 28 4
U40LP_VHD_SRF_316X18M4B1 316 18 4
Figure 2-18 UDM Configuration File Example

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2.16. Parsing Type Definition

Usage: -pm, --parsingmode

Description: This option is used to specify the input design type. The supported
types are RTL_only and Netlist_only.
Example: $ ezBist -pm Netlist_only -v example.v
EZ-BIST will import example.v with the nestlist format.

2.17. Fault Free

Usage: --faultfree
Description: This option is used to decide whether the generated system
designs include fault memory modes or not. When this option is
set, the system designs with and without fault memories will be
generated. When this option is not set, only the system designs
with fault memories will be generated. The file name will be
[design]_INS.v.
Example 1: $ ezBist -bfl ezBist _template.bfl -I -W ./work
EZ-BIST will generate an integrated system design with fault
memory models.
Example 2: $ ezBist -bfl ezBist _template.bfl -I --faultfree -W ./work
EZ-BIST will generate integrated system designs with and without
fault memory models, respectively.

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2.18. RCF Generator

Usage: --rcfg address_length data width output_file

Description: This option is used to generate an example RCF file for ROM
memory model. The content of output RCF file is random.
Example: $ ezBist --rcfg 32 8 example.rcf
EZ-BIST will generate an example RCF file with 32x8 matrix
format.

2.19. STIL Format

Usage: --STILloopformat
Description: Change STIL file into the loop format.
Example: $ ezBist --STILloopformat
EZ-BIST will generate STIL file into loop format.
If there are many repetitive testing commands, using the option will
simplify the testing commands as loop instructions.

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3. EZ-BIST BFL Options

Users can execute EZ-BIST to generate the MBIST circuits with the BFL flow. This
chapter will introduce the setting options in the BFL file.
The definitions of function blocks in BFL file are defined as follows:
define{function}
…
end_define{function}
Users can find different options in each function block as below.

3.1. OPTION Function Block

Figure 3-1 shows the parameters in the OPTION function block.

Figure 3-1 OPTION Function Block

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Argument Option
Description
verilog_path User defined
Set the Verilog file paths for EZ-BIST. The format can be set either by file1.v | file2.v |
fileN.v or file-list file (*.f).

Note: Each file is separated by a vertical bar “|”.

Example:
set verilog_path = ./top.f
user_define_memory User defined
Set UDM file paths for EZ-BIST. The format can be memory1.udm | memory2.udm | … |
memoryN.udm.

Note: Each file is separated by a vertical bar “|”.

For more details, please refer to Application Notes.

Example:
set user_define_memory = BRAINS.udm
top_module_name User defined
Set the top module name of the system design which includes memory modules.

Example:
set top_module_name = top
top_hierarchy User defined
Specify the location (instance name) of the controller for MBIST circuits in the design
architecture.

Example:
set top_hierarchy = top
clock_trace No, Yes
This option is for users to disable/enable the clock source tracing function. The default
setting is “no”.

No: Disable the clock source tracing function

Yes: Enable the clock source tracing function

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Argument Option
Description
auto_group No, Yes
This option is for users to automatically group memory models based on the settings in
the GROUP function block. The default setting is “no”.

No: Disable the clock auto-grouping function

Yes: Enable the clock auto-grouping function

insertion No, Yes

This option is used to integrate the generated MBIST circuits and the original system
designs. Figure 3-2 shows the block diagram of the inserted system design.

No: Disable the insertion function

Yes: Enable the insertion function

Figure 3-2 Block Diagram of System Design with MBIST Inserted

integrator_mode No, Yes
This option is for users to add the dedicated testing port in the top module of MBIST.
Because these testing ports adhere to standard protocols such as IEEE 1149.1, users can
use the shared pin design to reduce the pin count. The default setting is “no”.

No: EZ-BIST will generate some specific hookup pins for the BII flow. Users can use
them to control MBIST or get data from MBIST.
Yes: EZ-BIST will reserve signals internally in advance for testing only in the BFL
flow.

Note: The option must be set to “yes” when clock tracing turns on.
work_path User defined
Specify the path for saving the generated results in the BFL flow.

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Argument Option
Description
fault_free No, Yes
When this option is set to “no”, EZ-BIST will generate an integrated system design with
fault memory models. On the contrary, when this option is set to “yes”, EZ-BIST will
generate two integrated system designs with and without fault memory. However, the
simulation will run on without fault memory. MBIST circuits are integrated into the original
system design.
parsing_mode RTL_only, Netlist_only
This option defines the file format of the imported design, supporting RTL_only and
Netlist_only.

Note: If the Netlist file are not uniquified, the parsing mode must be set to “RLT_only.”
ecc_prefix User defined
Specify the prefix of ECC (Error Correction Code) related files.

For example, when this option is set to “ECC”, the output repair-related files will be named
like ECC_[design]_INS.v and ECC_[filename]_tb.v etc.
memory_library User defined
Define the memory library (shown in example 1), or the memory library file list (shown in
example 2) will make EZ-BIST to load the information of memory models.

Example 1: set memory_library = /home/workspace/ram1024x32.lvlib

Example 2: set memory_library = ./mem_lib.f
block_path User defined
While the design is implemented with the bottom-up flow to insert MBIST into the sub
module, it will generate a *.blockinfo file in the sub module.

Example:
set block_path = ./block1/START_block1.blockinfo | ./block2/START_block2.blockinfo
force_system_verilog No, Yes

The parsing format will be changed to System Verilog when users set the option to “yes”.
The default setting is “no”.

No: Initial parsing format is Verilog.

Yes: Changed parsing format to System Verilog.

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3.1.1. CLOCK Sub Function Block

Users can define the information of clock domain or provide an SDC file for EZ-BIST
to do clock tracing.

Figure 3-3 Clock Sub Function Block

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Table 3-1 Clock Information

Argument Option

Description
sdc_file User defined
Specify the path of an SDC file.
define{clock_name} User defined
Set the clock domain name.
clock_cycle User defined
Set the operating period of clock domain defined in “clock_name”.

clock_source_list User defined

Set the source pin or port of clock domain defined in “clock_name”.

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3.1.2. GROUP Sub Function Block

EZ-BIST assigns memory grouping according to the rule of clock domains, types of
memory models, the criteria of grouping specifications, and power consumption.
Users can also do memory grouping manually based on their own project
requirements by editing the memory information file *.meminfo. Memory models in
the same group can be tested in parallel to reduce the testing time.

Each memory will have the dedicated Sequencer ID (SEQ_ID) and Group ID
(GRP_ID). Memories have the same SEQ_ID and GRP_ID are in the same group
and can be tested at the same time.

The SEQ_ID is classified by types, specifications, and the clock domains of memory
models. This ID means which sequencer the memory models belong to. The GRP_ID
is classified by power consumption and number limitations of a single group.

Figure 3-4 Group Function Block

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Argument Option

Description
sequencer_limit User defined
This option defines the maximum amount of memory instances in a sequencer.

Default Value: 60
group_limit User defined
This option is used to define the maximum amount of memory instances in a group. This
number should be less than the value of sequencer_limit.

Default Value: 30
memory_list User defined
Specify the paths of memory info file (*.meminfo). Figure 3-8 is an example of memory
info file.

For more details, please refer to Application Notes.

lib_path User defined
This option is for users to set the path of memory libraries. EZ-BIST will load power
information of memory models from *.lib files and do memory grouping automatically
based on the power criteria through the power_limit option.
time_hierarchy 0 (time) <= value <= 1 (hierarchy)
This option is for users to adjust the weight between the testing time and design hierarchy.
The default value is 0.5.

For example:
set time_hierarchy = 0 EZ-BIST will assign memory grouping based on the optimized
testing time. The testing time will be the highest priority.
set time_hierarchy = 1 EZ-BIST will assign memory grouping by hierarchy
relationships.
In this case, the logical hierarchy will be the highest priority.

power_limit User defined

Set the maximum limitation of power consumption in one group.

For example:
set power_limit = 0.005

Note: The unit is mW and can be decimal.

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Argument Option

Description
hierarchy_limit User defined

Set the maximum hierarchy number when doing auto-grouping. If the hierarchy number
between memory models is larger than this number, EZ-BIST will not group these memory
models into the same group.

Default Value: 0 (no limitation of hierarchy number)

As shown in Figure 3-5, users can open a memory info file by clicking the “File” menu
and selecting “Open”.

Figure 3-5 Open Memory Info File

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Figure 3-6 is an example of the memory info file. For the detailed information, please
refer to Chapter 7 in Application Notes.

Figure 3-6 Example of Memory Info File

As shown in Figure 3-7, users can right click “GROUP” and select “add mem” to add
memories by batches according to the information described below.

Figure 3-7 Support Batches Adding and Multiple Formats

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A memory info file includes the following items. For the detailed information, please
refer to Chapter 7 in Application Notes.

⚫ Clock domain: It shows “memory clock domain name” and “testing clock cycle”.
⚫ Memory module: It shows the “memory module name” and “memory hierarchy”.
⚫ Bypass: Set the values of the bypass function.
⚫ Diagnosis: Set the values of the diagnosis function.
⚫ Q_pipeline: Set the value of the Q_pipeline option.
⚫ Group Architecture: This option shows the grouping architecture information
including the controller, sequencer, and group.
⚫ Design information: This option shows the number of memory instances,
memory types, and testing algorithms.

Figure 3-8 Memory Info Setting Information

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3.1.3. PHYSICAL Sub Function Block

Figure 3-9 PHYSICAL Sub Function Block

(For the detailed information, please refer to the table in the next page.)

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Argument Option
Description
enable_physical No, Yes
If this option is set to “yes”, EZ-BIST will auto-group based on the DEF (Design Physical
Information) file.
physical_location_file User defined
Set the paths of the DEF file.
controller_scope User defined
After editing a SCOPE file, set the path of the SCOPE file. The scope information should
be included with a controller name and position coordinate as follows.

Controller Name Position Coordinate (x1 y1) (x2 y2)

For example, top_default (10000 10000) (300000 400000)

physical_logical 0 <= value <= 1

This option is to adjust the weight between physical coordinates and values defined in the
time_hierarchy option.

For example:
set physical_logical = 0 EZ-BIST will calculate the number of intermediates based
on an internal algorithm. Memory models which are located
near this intermediate number will be merged into the same
group.
set physical_logical = 1 EZ-BIST will execute memory grouping based on the value
of the time_hierarchy option.

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3.2. BIST Function Block

Figure 3-10 MBIST Function Block

Argument Option
Description
STIL_test_bench No, Yes
Generate a test pattern with the STIL format (IEEE 1450-Standard Test Interface
Language) for the tester machine when this option set to “yes”. Since the result in the
default STIL format might be a lot of repeated codes, users can change it into the loop
format by using command lines, -- STILloopformat.

No: Not generate the test pattern with the STIL format
Yes: Generate the test pattern with the STIL format

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Argument Option
Description
WGL_test_bench No, Yes
Generate a test pattern with the WGL format (Waveform Generation Language) when
this option is set to “yes”.

No: Not generate the test pattern with the WGL format
Yes: Generate the test pattern with the WGL format
bist_interface basic, basicIO, ieee1500, ieee1149.1
Select the MBIST interface.

Note: For more details of these interfaces, please refer to IO Pin Definition.
Note: When users set bist_interface to “ieee1149.1”, then IEEE 1149.7 will be the output
interface.
Note: When users set bist_interface to “ieee1500”, then IEEE 1149.1 will be the output
interface.
add_address_y No, Yes
This option defines MBIST algorithms and supports the Y direction. The generated
testbench supports the X and Y addressing modes (X stands for the row of the memory,
and Y stands for the column of the memory.)

No: The MBIST pattern testing only supports the X direction.

Yes: The MBIST pattern testing supports both X and Y directions.

X_Y = 00 Write MBIST pattern in the X direction only.

X_Y = 01 Write MBIST pattern the X direction first, and then Y direction.
X_Y = 10 Write MBIST pattern in the Y direction first, and then X direction.
X_Y = 11 Write MBIST pattern in the Y direction only.

Note: This option does not support memories with a column width of “0”.
Note: To define the X or Y directions, users must modify the X_Y setting in the testbench
file.
clock_source_switch No, Yes
This option is used to select the testing frequency while the clock_within_pll option and
clock_switch_of_memory option is turned on. The MBIST circuit will have a dedicated
test input signal named TRANS. Users can use this input signal to choose the testing
frequency (from SCK or MCK).
Note: The option must be set to “no” when clock tracing is turned on.

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Argument Option
Description
clock_within_pll No, Yes
If this option is set to “yes”, the MBIST circuit will have another clock input source, SCK.
This signal is used to connect with an ATE (Automatic Test Equipment) machine.

Note: The option must be set to “no” when clock tracing is turned on.
diagnosis_support No, Yes
This option is used to enable the diagnosis mode, which can provide users with the failure
time and failed memory information.

No: Disable the Diagnosis mode

Yes: Enable the Diagnosis mode
diagnosis_data_sharing No, Yes
Users can integrate diagnosis circuits into the sequencer to do diagnosis storage sharing
to reduce the area of MBIST circuits when this option set to “yes”.

diagnosis_faulty_items algorithm, operation, element, seq_id,

grp_id, address, ram_data, rom_data
This option is used to select the output items of the diagnosis result based on the chip
failure analysis requirement.

Example:
set diagnosis_faulty_items = algorithm, operation, element, seq_id, grp_id, address,
ram_data, rom_data
rom_result_shiftin No, Yes
This option is used to do ROM memory testing and import the signatures for internal
verification. The scenario is used when the contents of the ROM memory is not confirmed
at the initial development stage.

For example, when users set rom_result_shiftin to “yes” and the POT function is
enabled, the testing results of ROM memory will be transferred to the internal circuit via
commands.
rom_result_shiftout No, Yes
This option is used to do ROM memory testing and export the signatures for external
verification. The scenario is used when the contents of ROM memory is not confirmed at
the initial development stage.

For example, when user set rom_result_shiftout to “yes” and the testing results of the
ROM memory will be transferred to the output interfaces via commands.

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Argument Option
Description
Q_pipeline No, Yes
This option is used to add an extra pipeline register to MBIST logics.

No: No extra register will be added to the data output of a memory model.
Yes: An extra register will be added to the data output of a memory model to enhance the
operating timing of MBIST logics.
asynchronous_reset No, Yes
The option is used to specify asynchronous or synchronous reset of MBIST. The circuit
can be differentiated into two types, “synchronous reset” and “asynchronous reset”.
“Synchronous reset” indicates all DFFs are triggered to reset and then reset at the same
time. “Asynchronous reset” indicates the reset of the circuit is based on the sequential
order. In other word, this is not synchronous reset.

No: Synchronous reset will be applied with two DFFs. In addition, hookup the
RSTN port (the MBIST reset signals) and the ATPGen port.
Yes: It indicates the asynchronous reset while one reset signal asserts.
Additionally, hookup the RSTN port in the BII flow.

Figure 3-11 shows an example of synchronous/asynchronous circuits. When the ATPGen

port is under the “scan mode”, the synchronous circuit will be bypassed and be regarded
as the asynchronous circuit to select signals.

Figure 3-11 Example of Synchronous/Asynchronous Circuit

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Argument Option
Description
atpg_reset No, Yes
This option is for users to reset the “Automatic Test Pattern Generation”. When the option
is set to “yes”, EZ-BIST tool will string all the reset signals under MBIST into a series of
ATPG_rstn.

Note: In the BII flow, hookup ATPG_rstn and ATPGen ports at the same time.
Note: When users set atpg_reset to “yes”, the ATPG signal will be inserted into the
multiplexer (MUX) for the selection of ATPG_rstn or async_rstn_in signal as shown in
Figure 3-12.

Figure 3-12 Example of ATPG Circuit

select_elem_testing No, Yes

This option is for users to do testing with user-defined test algorithms rather than EZ-BIST
built-in algorithms by controlling input interfaces. When this function is turned on, users
can select the algorithm elements in the SEQ, and the elements can be tested in the
testbench.
A programmable algorithm is presented as a PROG entry. Figure 3-13 shows the testing
commands while this option is turned on. Table 3-2 is the definition of these entries.

Note: User-defined testing algorithms cannot support ROM memory testing and the
diagnosis function.

PROG SEQ_ID GRP_ID MEB_ID BG ALG_CMD

SDI_Command

Figure 3-13 Commands for Programmable Algorithm Function

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Table 3-2 Commands for Programmable Algorithm

Command Description
PROG = 0, executing the EZ-BIST built-in algorithm
PROG
PROG = 1, executing the user-defined algorithm
SEQ_ID Sequencer ID of the memory
GRP_ID Group ID of the memory
MEB_ID Memory ID of the memory
“SOLID” is the default background style.
BG Only when “5A” is chosen, users can select four different modes to test.
For more details, please refer to Table 3-3.
This ALG_CMD entry is based on March algorithm, users also can
define it. While PROG = 1, MBIST circuits will execute user-defined
ALG_CMD
algorithms. The width of the ALG_CMD entry is based on the March
element definition.

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Argument Option
Description
algorithm_selection No, Outside, Scan
This option is for users to choose a single test algorithm or multiple test algorithms to test
sequentially.

No: Users can select algorithms which will be tested with MBIST circuits
sequentially.
Outside: Users can select the test algorithm with the input port ALG and this input port
will be added when the basic interface is defined.
Scan: Users can launch a test with IEEE 1149.1 or IEEE 1500.
algorithm_loop_test No, Yes
This option is for users to improve the loop mode testing efficiency. Some tests require a
loop mode, but using multiple testing commands can cause delays between the
commands.

No: Not support continuous memory testing

Yes: Support continuous memory testing

Users can send commands to control the BURN_IN signal to define the period of testing
as Figure 3-14 when this option set to “yes”.

Figure 3-14 The Example Loop Test Waveform

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Argument Option
Description
background_style SOLID, 5A

The type of background_style can be set to “SOLID” and “5A” (Check Board), the
contents are defined in the bg_table file.
There is an entry named BG (Background) in the SDI_Command. When
background_style is set to 5A, the BG settings are shown as Table 3-3.

Note: If users adopt “March Mdsn1” as an algorithm, background_style cannot be set to

“5A”.
Table 3-3 BG Field Definition
BG [1:0] Definition
00 SOLID + 5A
01 SOLID
10 5A
11 SOLID + 5A
background_bit_inverse No, Yes
Bit inverse means that the BG testing data will be inversed by the increasing order or
decreasing order of the memory address.
For example, the BG testing data of a 64x8 memory with SOLID BG is shown as Table
3-4.
Table 3-4 Example of Bit Inverse

Memory Address SOLID BG Test Data Description

0000_0000 0000_0000 testing data non-inversed
0000_0001 1111_1111 testing data inversed
0000_0010 0000_0000 testing data non-inversed
0000_0011 1111_1111 testing data inversed
… … …

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Argument Option
Description
background_col_inverse No, Yes
Column inverse means that the BG testing data will be inversed by the changes of the row
memory address. If this changing time is larger than the CIC (Column Inverse Counts)
number, the BG testing data will be inversed. The CIC number is defined by the memory
Mux value.

For example, a 64x8 memory with Mux = 4 and the BG type = SOLID. The BG testing data
is shown as Table 3-5.

Table 3-5 Example of Column Inverse

Memory Address SOLID BG Test Data Description

0000_0000 0000_0000 testing data non-inversed
0000_0001 0000_0000
0000_0010 0000_0000
0000_0011 0000_0000
0000_0100 1111_1111 testing data inversed
0000_0101 1111_1111
0000_0110 1111_1111
0000_0111 1111_1111
0000_1000 0000_0000 testing data non-inversed
0000_1001 0000_0000
0000_1010 0000_0000
0000_1011 0000_0000
… … …

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Argument Option
Description
user_define_bg User defined
Users can specify the background test pattern via the setting of user_define_bg.

For example, if the width of the data is 4 bits:

Example 1: When users assign user_define_bg to “3” and background_style to

“SOLID”, then the testing pattern will be 0x3.
Example 2: When users assign user_define_bg to “3” and background_style to
“5A”, then the testing pattern will be 0x3,0xC,0x5,0xA.

Table 3-6 lists the example of user-defined background and the corresponding test
patterns.

Table 3-6 Example of User-defined Background and Test Pattern

User-defined
Background Style Test Pattern
Background
SOLID 3 3
3 3, C, 5, A
5A
3, 7 3, C, 7, 8

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Argument Option

Description

retention Handshake, Time

This option is for users to set the mode of retention.

Handshake: The retention time can be set in retention_time option in BFL file or in
testbech.v file as shown in Figure 3-15.
Time: The retention time is fixed after being set in the retention_time option in
the BFL file.

`timescale 1ns / 1ps

module stimulus;
parameter top_default_bcyc = 100.0;
parameter RP_default_bcyc = 100.0;
parameter tcyc = 100.0;
parameter rcyc = 100.0;
parameter cyc = tcyc;

parameter CORE_ID = {3{1'b1}};

parameter RP_default_RET_time = 5.0;
parameter top_default_RET_time = 5.0;
parameter TAP_IR_width = 1*3;

parameter test_result_width = 10;

parameter test_command_width = 17;
parameter max_config_width = 17;
parameter WIR_width = 6;
parameter COMMAND_DR_ID = {2'b1, 2'b1, 2'b1};
parameter TEST_RESULT_DR_ID = {2'd2, 2'd2, 2'd2};
parameter max_config_width = 367;
parameter DIAG_RESULT_DR_ID = {2'd3, 2'd3, 2'd3};
parameter top_default_ALG_width = 2;
parameter top_default_SEQ_ID_width = 2;
parameter top_default_GRP_ID_width = 1;
Figure 3-15 Example of Retention Time Option in testbech.v

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Argument Option
Description
retention_time User defined
This option is used to define the retention time. The supported unit of retention time are
listed in Table 3-7.

Table 3-7 Supported Units of Retention Time

Symbol Unit
T 1012
G 109
M 106
K or k 103
m 10-3
u 10-6
n 10-9
p 10-12

Some memory testing algorithms allow users to do retention testing.

For example, March-RET algorithm is <(wb) (SLP) <(rb) >(wa) (SLP) >(ra). The (SLP)
element indicates the sleeping time is 1ms. If users want to extend the sleeping time more
than 1ms, they can specify the retention time through retention_time.

define{BIST}
…
set retention_time = 1m
…
end_define{BIST}

Note: The syntax of the retention time has different formats.

Take 1ms as an example,

The timing setting format in Verilog is retention_time = 1000000 (n).
The timing setting format in System Verilog is retention_time = 1000000 (n)
or retention_time = 1m.

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Argument Option
Description
bypass_support No, Wire, Reg
Define whether the bypass circuit is implemented by wire or register.

No: Disable the bypass mode

Wire: Implement the bypass circuit by wire as Figure 3-16
Reg: Implement the bypass circuit by register as Figure 3-17
When entering the bypass mode, all input signals of the memory will be combined with
normal access output. This option can increase logical testability and fault coverage.

Figure 3-16 Implementation of Bypass Circuit by Wire

Figure 3-17 Implementation of Bypass Circuit by Register

Note: If the bypass_support option is enabled, the ATPG clock (Scan) will switch to
MBIST clock (MCK, memory clock) in the multi-source scenario.

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Argument Option
Description
bypass_memory_disable No, Yes
This option is available only when bypass_support is enabled. The memory CS (chip
select) will be disabled. For example, when CS is active high, the parameter of CS will be
“0”. When CS is active low, the parameter of CS will be “1”. All the memory clocks will be
tied together with “0”.

No: The memory CS will be enabled.

Yes: The memory CS will be disabled.

bypass_reg_sharing 1 <= value <= 1024

Users can set this option to define the register sharing number of bypass registers when
bypass_suppor is set to “reg”. The range is between “1 ~1024”. EZ-BIST will base on
this option to implement register sharing to reduce the area of bypass registers.

For example, when users assign bypass_reg_sharing to “4” and data output Q to “32”
bits, the number of bypass registers will be “8” as Figure 3-18.

Figure 3-18 Example of Register Sharing

bypass_clock No, Yes

If users decide to implement the bypass circuit by “reg” method, they can turn on this
option to add a dedicated input port BCK for the bypass register and users can define the
frequency of BCK based on their project requirements.

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Argument Option
Description
clock_function_hookup No, Yes
This option is for users to hookup MCK with a memory functional clock. When this option
is set to “yes”, MCK will be driven by the memory functional clock directly.

Note: The option is available only when clock tracing is turned on. Figure 3-19 shows the
clock architecture of this option.

Figure 3-19 Clock Architecture of clock_function_hookup Option

clock_switch_of_memory No, Yes

When this option is set to “yes”, the clock signal of the memory model will be changed to
MCK by clock multiplexer in the test mode. The clock signal of the memory model is
running at the same frequency according to users’ requirements. Figure 3-20 shows the
clock architecture of this option. The MCK also can be driven by the internal testing clock.
Users can hookup it with internal clock signal in BII mode.

Figure 3-20 Clock Architecture of clock_switch_of_memory Option

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Argument Option
Description
diagnosis_memory_info No, Yes
EZ-BIST will generate MBIST circuits with N-bits width LATCH_GO output signals when
this option is turned on. N means the number of memory models and each bit of a
LATCH_GO signal indicates one memory model. Figure 3-21 shows the waveforms of
LATCH_GO signals. When the signal turns from high to low, it indicates that memory has
failed.

Figure 3-21 Diagnosis Fail Memory Information

diagnosis_time_info No, Yes
EZ-BIST will generate MBIST circuits with the MBIST_GO output signal when this option
is turned on. If the memory fails, this signal will change from high to low and return to high
in the next clock cycle as shown in Figure 3-22.

Figure 3-22 Diagnosis Fail Time Information

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Argument Option
Description
parallel_on No, Yes
Specify the memory to support parallel testing. When this option is set to “yes” and assign
testbench parameter PRL_ON to “1”, all memories under a controller will launch the testing
simultaneously.
reduce_address_simulation No, Yes
EZ-BIST executes testing with fixed four memory addresses as Table 3-8. This option
speeds up simulation by reducing memory testing addresses. If the column width is zero,
the testing address will be fixed to two memory addresses as Table 3-9.

Table 3-8 Fixed Four Memory Addresses

Memory Address Row Memory Address Column

…000000 000000…
…000000 111111…
…111111 000000…
…111111 111111…

Table 3-9 Fixed Two Memory Addresses

Memory Address Row

…000000
…111111

pot No, basic, hw_rom, rom

When the system requires the Power_On testing, the following options are available. For
more details, please refer to Chapter 9 in Application Notes.

No: Disable the POT function.

Basic: It indicates supporting some generic signals to enable or disable
MBIST and the test results. This function only supports the RAM test.
hw_rom: It indicates that the POT testing commands will be designed to
hardwired circuits. This function supports the ROM test.
Rom: It indicates that the POT testing commands will be stored in the ROM.
This function supports the ROM test.

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3.2.1. Default Algorithm Sub Function Block

EZ-BIST provides various testing algorithms for users to choose according to different
testing requirements. Figure 3-23 shows the default setting of single-port memories
is the March C+ algorithm. If users want to add more testing algorithms into MBIST
circuits, they just need to add algorithms into this function block.
The ROM setting is used to set the algorithm for ROM, and there are two options:
ROM test and ROM Test 3n.
Section 6.4 shows the testing algorithms provided by EZ-BIST.

Figure 3-23 Default Algorithm Function Block

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3.2.2. Programmable Algorithm Sub Function Block

As shown in Figure 3-24, users can set the programmable algorithm in the GUI mode.

Figure 3-24 select_elem_testing

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Figure 3-25 shows the select testing elements sub function block, describing the
testing elements created by users.

Figure 3-25 Select Testing Elements Sub Function Block

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While users chose the programmable algorithm function, the ALG_CMD entry will be
added for programming usage. Users can define elements of their own testing
algorithm.
For example, the March CW algorithm provided by EZ-BIST. The contents of this
algorithm is >(wa) >(ra, wb) >(rb, wa, ra) <(ra, wb, rb) <(rb, wa) <(ra), the number of
March elements is 6 and the supported elements are r, w, rw and rwr. In this case, the
width of the ALG_CMD entry is 7 × 5 = 35 (5 indicates element width / EOT, End of
Test should be 0) and the format definition of March element can be Direction, Parity,
and Operation as Table 3-10. Users also can find the definition in the
march_command.alias file.

ALG_CMD = {ALG_CMD6, ALG_CMD5, … , ALG_CMD1, ALG_CMD0}

Table 3-10 Format of March CW Element

Type Field Width Value Description

> 0 Address increase
Direction 1
< 1 Address decrease
Data a 0 Data background
1
Background b 1 Inverse data background
r 001 Read
rw 010 Read, Write
Operation 3
rwr 011 Read, Write, Read
w 100 Write

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3.2.3. BFL TechNode

To avoid the possibility of dynamic defects in electronic devices which are

manufactured from the advanced processes below 50nm, more accurate algorithms
are needed for memory testing. EZ-BIST provides another way to select the
algorithms. According to the needs of different processes and applications, EZ-BIST
TechNode will check the recommended algorithms for users as Figure 3-26.

Figure 3-26 BFL TechNode

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3.2.4. BFL Setting File

Users can check the settings of the BFL file in the BFL content page.

Figure 3-27 BFL Setting File

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As shown in Figure 3-28, users can click “Run” from the “File” drop-down menu to
complete the MBIST execution.

Figure 3-28 Run the BFL Setting File

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4. EZ-BIST Output Files

This chapter introduce EZ-BIST’s output files and their usages. These output files are
divided into Self-MBIST and Inserted-MBIST. Users can use these generated files to
verify the MBIST circuit, and also verify the MBIST circuit integrated with customers’
own logic design.

4.1. Self-MBIST Related Files

The generated self-MBIST related files include the self MBIST circuits (.v), test bench
(.v), file-list file (.f), synthesis script (.tcl) and brief introduction file (.html). When
users run simulations with these output files, it only simulates between MBIST circuits
and memories.

Table 4-1 Self-MBIST Related Files

EZ-BIST output Description

This is an EZ-BIST project file and includes
Project file (.bid) [filename]_spec.bid
all settings of EZ-BIST.
[filename]_top.v includes memory
models, fault memory models and MBIST
circuits.
Self MBIST circuits [filename]_top.v It is integrated with MBIST circuits and
(.v) [filename].v memory models of original system design.

[filename].v is HDL file of MBIST

circuits.
This is a test bench for testing
Test bench (.v) [filename]_tb.v
[filename]_top.v.
File-list file records [filename]_top.v,
File list (.f) [filename].f [filename].v and memory models. This
file is used for simulation.
Synthesis script This is a script file for synthesis of MBIST
[filename].tcl
(.tcl) circuits.

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4.2. Insert MBIST Related Files

EZ-BIST can insert MBIST circuits into customers' design. Users can verify the
inserted-MBIST with their own system circuit. The following table shows the related
files of the insert MBIST circuits.

Table 4-2 Insert MBIST Related Files

EZ-BIST output Description

Inserted [design]_INS.v The file [design]_INS.v integrate MBIST
MBIST [design]_INS_f.v circuits with user’s system designs. The [design]
circuits (.v) is the name of user’s system designs. This file
does not include fault memory models.

Different from [design]_INS.v,

[design]_INS_f.v is integrated with fault
memory models.
Test bench [filename]_tb_INS.v This is a test bench for testing
(.v) [design]_INS.v.
File list (.f) [filename]_INS.f File-list [filename]_INS.f records
[filename]_INS_FAULT.f [design]_INS.v, memory models and MIBST
circuits.

Different from file-list [filename]_INS.f,

[filename]_INS_FAULT.f also includes fault
memory models.

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4.3. Generate Folders

The following table shows the generated folders when executing EZ-BIST.

Table 4-3 Generated Folder

EZ-BIST Output Description

This folder is used to save the results of
REPORT
synthesis.
[mem_name]_f.v is fault memory models.
Some values inside of memory are tied to 0 or
1. This is used to verify functional correctness
[mem_name]_f.v of MBIST circuits.
FAULT_MEMORY
fault_memory.f
The file-list fault_memory.f records all
generated fault memory models.

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4.4. Makefile

EZ-BIST also generates Makefile which includes related commands of simulation and
synthesis for users to verify their designs. Using Makefile, it can easily run various
simulations along with MBIST circuits. Table 4-4 shows the commands of Makefile.

Table 4-4 Commands of Makefile

Command Description
It is used to run self MBIST simulation with
make
Self-MBIST [bistname]_tb.v and [bistname].f. The
[bistname]
simulation simulation results will be printed out in the command
FUNC=tb
line window.
It is used to run self MBIST simulation with
Self-MBIST make [bistname]_tb.v, [filename].f and fault
simulation with [bistname] memory models. This simulation will show “Failed”
fault memories FUNC=tb_f because MBIST has detected faults in the memory
models.
make It is used to run synthesis with [bistname].tcl
MBIST circuits
[bistname] scripts using Design Compiler. The output will be
synthesis
FUNC=dc saved into the REPORT folder.
Check syntax
make It is used to run syntax check with [bistname].f by
of self MBIST
[bistname] using nLint. The checking result will be saved to file
circuits with
FUNC=lint [bistname]_lint.log.
nLint
It is used to remove generated files including *.log,
Remove
make clean *.fsdb,*.db, *.sdf and *.rpt files in the
generated files
REPORT folder.
It is used to run the Inserted MBIST simulation with
[bistname]_tb_INS.v and
Inserted- make
[bistname]_INS_FAULT.f, the simulation results
MBIST [bistname]
will be printed out in the command line window.
simulation FUNC=tb_INS
This command is available while the BFL option
insertion is "yes".
It is used to run the Inserted MBIST simulation with
Inserted-
make [bistname]_tb_INS.v,
MBIST
[bistname] [bistname]_INS_FAULT.f and fault memory
simulation with
FUNC=tb_INS_f models. The simulation results will show “Failed”
fault memories
because MBIST has detected faults in the memory

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models.
Check syntax It is used to run syntax check with
make
of inserted- [bistname]_INS_FAULT.f by using nLint. This
[bistname]
MBIST circuits checking result will be saved to file
FUNC=lint_INS
with nLint [bistname]_lint_INS.log.
make It is used to run formal checking with
Formal
[bistname] [bistname]_fm.tcl. The output message will be
checking
FUNC=fm saved into [bistname]_fm.log.

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4.5. Macro File

iSTART’s latch-based clock gating cell model is *_GCK.v (* will be generated

according to the module name in customers’ designs). It can be synthesized in RTL
modeling. However, to control clock skews, it is preferrable to integrate clock cells
from the standard library.

Note: Please change each module in the macro file into the corresponding
standard cell. Figure 4-1 is the example of a clock gating module. Here
“ctr_name” means the prefix name coming from the controller name in
the customer’s design.

module ctr_name_gck (clk_out, clk_en, clk_in, test_en);

input clk_in;
input clk_en;
input test_en;

output clk_out;

`ifdef SYNTHESIS
GCK_VENDOR_CELL gck(
Q(clk_out)
E(clk_en)
TE(test_en)
CK(clk_in)
);
`else
reg latch_out;

assign clk_out = clk_in & latch_out;

always @(clk_in or clk_en or test_en) begin

if (~clk_in) begin
latch_out = clk_en | test_en;

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end
end
`endif

endmodule

Figure 4-1 Clock Gating Logic for Simulation and Synthesis

Figure 4-2 shows the schematic diagram of a clock gating cell with the waveform.

Figure 4-2 Clock Gating Cell with Waveform

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5. BII File

EZ-BIST provides a BII (Integration Information) File for the integration task, which is
in charge of integrating different MBIST controllers with an integrator module and then
use IEEE1149.1 interface to communicate with ATE. This is used to save the pin count
of the chip level. We will introduce the options of a BII file in this chapter.
5.1. Integrator Function Block

Users can define the hookup pin mapping settings and order of different MBIST
controller in the following function block.

define{Integrator}[Name]
…
end_define{Integrator}

The parameter, [Name] can be modified by users, and this will be the module name
of the generated integrator module. This integrator module will integrate the WSI
signal and WSO signal of each MBIST controller.
Figure 5-1 shows an example to load the existing BII file as the default setting.

Figure 5-1 Load BII

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The options of the integrator function block are shown in Figure 5-2.

Figure 5-2 Options of Integrator Function Block

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The following is the list of BII parameters and their functionalities:

Argument Option

Description

group_order User defined

This option is for users to define the ordering of an MBIST controller by setting the group
sub function block. The testing sequence will follow the setting of group_order.

top_module_name User defined

This option is for users to define the top level module of their design.

TAP_hierarchy User defined

This option is for users to define the hierarchy of integrator module.
verilog_path User defined
Specify the file list which is generated by the BFL flow.
For example,
If the BFL option, fault_free is set to “yes”, the generated filelist file is *_INS.f.
If the BFL option, fault_free is set to “no”, the generated filelist file is *_INS_FAULT.f.

Users can assign “*_INS.f” or “*_INS_FAULT.f” to the verilog_path option.

work_path User defined
Specify the path of the working directory of the BII flow. All generated files in the BII flow
will be saved to work_path.
bist_integ_path User defined
Set the path of the integration specification file *_spec.integ.
Users can assign more than one integration specification files and separate them by the
vertical bar “|”.
For example,
bist_1_spec.integ | bist_2_spec.integ | bist_3_spec.integ.
skip_include_check No, Yes
No: Transform all included paths in the output files into absolute paths
Yes: Only transform the included paths in the modified files (which are named with
keyword “_INS”) into the absolute path

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Argument Option
Description
serial _order User defined
The option is used to specify the memory testing order under the individual controller
group. If the option parallel_on in the BFL file is “yes”, the memory will be tested by one
controller sequentially one after another. For some particular cases, users want to test
memories under more than one controller at the same time. By using the serial_order
option, users can assign the controller group priority testing order, and the controller group
contains one or more controllers.

For example, when users assign serial_order to “top_default0, top_default1 |

RP_default0 | RP_default1” and set “parallel_on” to “yes”. In this case:
The priority testing order is [top_default0 & top_default1] => [RP_default0] =>
[RP_default1]

Note: Each memory controller under a group separated by comma “,” is tested at the same
priority order. An individual testing controller group is separated by a vertical bar “|”.

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5.1.1. Hookup Sub Function Block

EZ-BIST can support to implement the hookup function automatically. When the
MBIST has been completed, users can get the *.integ file in the MBIST folder. The
*.integ file provides the hookup pins shown in Figure 5-4. Furthermore, users can
define the hookup pin information and pin the remapping information in hookup sub
function block.

The definitions of hookup sub function blocks in the BII file are defined as follows:

define{hookup}[signal]
…
end_define{hookup}

Figure 5-3 Hookup Sub Function Block

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Consequently, the BII hookup information table in *.integ file might differ depending
on the user’s interface.

In Figure 5-4, it shows the IEEE 1149.1 JTAG interface. EZ-BIST supports several
interfaces, such as basic, basicIO, IEEE1149.7, and IEEE1149.1.

# BII flie hookup information table

# interface TCK => define{hookup}[TCK]
# interface TRST => define{hookup}[TRST]
# interface TMS => define{hookup}[TMS]
# interface TDI => define{hookup}[TDI]
# interface TDO => define{hookup}[TDO]
# controller clock => define{hookup}[top_default_MCK]
# BIST reset in => define{hookup}[RSTN]
end_define{BIST}

Figure 5-4 BII File Hookup Information Table in *.integ File

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Argument Option

Description

hookup User defined

It indicates a hookup sub function block.

signal User defined

It indicates the signals on the integrator module and will be connected with the mapping
port. This signal could be IEEE 1149.1, IEEE 1149.7 signals, IEEE 1687 signals, MCK, or
TCK. For example, the signal name in IEEE 1149.1 could be TCK, TDI, TMS, TRST, and
TDO.

dedicate_port User defined

Set the pin name on the boundary port of a chip. This port could be IEEE 1149.1, IEEE
1149.7 signals, IEEE 1687 signals, MCK, or TCK.
mapping_port User defined
mapping_port is users’ reserved port for MBIST and it can be connected to MBIST by the
mode of replacing the port. The hierarchy must be specified and can be separated by a
space bar. Figure 5-5 is the example of port connection.

The following is the example of command setting:

define{hookup}[TCK]
set dedicate_port = itck
set mapping_port = top u_pm otck
end_define{hookup}

Figure 5-5 The Example of Port Connection

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Argument Option

Description
mapping_wire User defined
It connects to MBIST through the wire assignment. The hierarchy must be specified and
can be separated by a space bar. Figure 5-6 is the example of wire connection.

The following is the example of command setting:

define{hookup}[TCK]
set dedicate_port = itck
set mapping_wire = top u_pm otck
end_define{hookup}

Note: Either mapping_port or mapping_wire can be chosen.

Figure 5-6 The Example of Wire Connection

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5.1.2. Group Sub Function Block

The Group sub function block defines the grouping mechanism of all MBIST
controllers.
The following syntax defines the Group sub function block.

define{group}[group_name]
set connection_type = …
set bist_order = …
end_define{group}

Note: [group_name] should be the name which is listed in the column of group_order.

Figure 5-7 Group Sub Function Block

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Argument Option

Description

bist_order User defined

This option is for users to establish the connection order of controllers in a chain.

For example, set bist_order to “bist1_controller, bist2_controller, bist3_controller”, and separate

each MBIST controller comma “,”. In this case, the integrating order is bist1_controller →
bist2_controller → bist3_controller.

5.2. Testbench Function Block

The testbench block defines testbench conditions like testbench file format, pll stable
cycles and reset cycles.
The following syntax defines the testbench sub function block:

define{Testbench}[integration_filename]
set pll_wait_cycle = …
set reset_cycle = …
set file_format = …
…sub function block…
end_define{Testbench}

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Figure 5-8 Testbench Function Block

Argument Option
Description
bench_name User defined
Set the test bench file name, and the default name is “INTEG_tb”.
pll_wait_cycle User defined
Specify the stable cycle time of PLL. The MBIST circuit will be reset after these stable cycles.
Default Value: 100000
reset_cycle User defined
This option defines the waiting cycles to reset the MBIST circuit. While PLL is stable, the MBIST
circuit will be reset after the period of reset_cycle.
file_format STIL format, WGL format, Verilog
Define the output format of testbench.
The default Setting is “Verilog”.

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5.2.1. Initial_sequence Sub Function Block

The Initial_sequence sub function defines the signals on the top level which can force
the system to enter testing mode. In a real chip, users may use some signals to switch
function or testing mode. To run MBIST mode simulation, EZ-BIST will switch these
signals to testing mode. The following syntax defines the testbench sub function block:

define{initial_sequence}[signal]
set width = …
set assert_value = …
set initial_value = …
set enable_cycle = …
set cycle_time = …
end_define{initial_sequence}

Figure 5-9 is the example of Initial sequence from the GUI view.

Figure 5-9 Initial_sequence Sub Function Block

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Argument Option
Description
width User defined
Define the width of a signal. On the top level, users will use pins to switch function mode
and testing mode.
assert_value User defined
Define the assert_value while entering the testing operation.
initial_value User defined
Define the initial value of the switch signal.
enable_cycle User defined
The defined signal will be changed from the initial value to the asserted value after cycle
values are defined with this option.
cycle_time User defined
The defined signal will keep the asserted value with the cycle number which is defined in
this option.

Figure 5-10 is the example of the BII setting content from the GUI view.

Figure 5-10 Example of BII Setting Content

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Select and click “Run” from the “File” drop-down list to execute the BII flow as Figure
5-11 shows.

Figure 5-11 Run BII Setting File

When the BII flow is completed, the status window will pop up to inform you the result
after BFL executed as Figure 5-12 shows.

Figure 5-12 The Status Window When BII Flow is Completed

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6. Appendixes

6.1. “Include” Case

For those designs, which contain a relative path with “include” and will be modified,
EZ-BIST will rewrite the relative path to absolute path. Therefore, if user plan to copy
the design to another path, please manually edit the absolute path based on new path
or re-execute EZ-BIST to generate the correct path.

6.2. Parsing Mode

If the design is RTL, please make sure it could be synthesized. Otherwise, EZ-BIST
cannot parse the design for inserting MBIST circuit to the design.
Due to the diverse syntax of RTL, we suggest users using netlist as an input if RTL
keeps having parsing issue.

6.3. *.rcf File

To avoid simulation failure, please use the absolute path in rom.v if you try to open
a *.rcf file.

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6.4. Supported Testing Algorithm

Table 6-1 Testing Algorithms for SRAM in EZ-BIST

Memory Name Fault Detection Algorithm

Type
SRAM March CW (part 1) SAF, TF, AF, CFin, CFid, CFst, >(wa) >(ra,wb) >(rb,wa,ra)
SOF, RDF <(ra,wb,rb) <(rb,wa) <(ra)
March CW (part 2) Word-oriented CF >(wa) >(wb) >(rb,wa,ra)
March Y SAF, TF, CFin, SOF, RDF >(wa) >(ra,wb,rb) <(rb,wa,ra)
<(ra)
March X SAF, TF, AF, CFin >(wa) >(ra,wb) <(rb,wa) <(ra)
MATS++ SAF, TF, AF, SOF >(wa) >(ra,wb) <(rb,wa,ra)
MOVI SAF, TF, AF, CFin, CFst, SOF, <(wa) >(ra,wb,rb) >(rb,wa,ra)
RDF <(ra,wb,rb) <(rb,wa,ra)
Ext March C- SAF, TF, AF, CFin, CFid, CFst, >(wa) >(ra,wb) >(rb,wa,ra)
SOF <(ra,wb) <(rb,wa) <(ra)
*March C+ SAF, TF, AF, CFin, CFid, CFst, >(wa) >(ra,wb,rb) >(rb,wa,ra)
SOF, RDF <(ra,wb,rb) <(rb,wa,ra) <(ra)

March C- SAF, TF, AF, CFin, CFid, CFst >(wa) >(ra,wb) >(rb,wa) <(ra,wb)
<(rb,wa) <(ra)
March C Gray ADOF >(wa) >(ra,wb) >(rb,wa) <(ra,wb)
<(rb,wa) <(ra)
Address only one bit change
March LR SAF, TF, AF, CFin, CFid, CFst, >(wa) >(ra,wb) >(rb,wa,ra,wb)
SOF >(rb,wa) >(ra,wb,rb,wa) >(ra)

March C SAF, TF, AF, CFin, CFid, CFst >(wa) >(ra,wb) >(rb,wa) >(ra)
<(ra,wb) <(rb,wa) <(ra)
March B SAF, TF, AF, CFin, CFid, SOF >(wa) >(ra,wb,rb,wa,ra,wb)
>(rb,wa,wb) <(rb,wa,wb,wa)
<(ra,wb,wa)
March A SAF, TF, AF, CFin, CFid >(wa) >(ra,wb,wa,wb)
>(rb,wa,wb) <(rb,wa,wb,wa)
<(ra,wb,wa)
March 17N SAF, TF, AF, CFin, CFid, CFst, >(wb) >(rb,wa,ra) >(ra,wb,rb)
SOF, RDF >(rb,wa) <(ra,wb,rb) >(rb)
<(rb,wa,ra) >(ra)

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March 19N 'SAF', 'TF', 'AF', 'CFin', 'CFid', >(wa,ra) >(wa) >(ra,wb,rb) >(rb)
'CFst', 'SOF', 'RDF' >(rb,wa,ra) >(ra) <(ra,wb,rb)
>(rb) <(rb,wa,ra) >(ra)
March 33N dRDF, dIRF, dDRDF, dTF, >(wa) >(wa,wb,wa,wb)
dWDF >(rb,wa,wa) >(wa,wa)
>(ra,wb,rb,wb,rb,rb) <(rb) <(wb,
wa,wb,wa) <(ra,wb,wb) <(wb,wb)
<(rb,wa,ra,wa,ra,ra) <(ra)
March 33N- 'dRDF', 'dIRF','dDRDF', 'dTF', '>(wa) >(wa,wb,wa,wb) >(r-
'dWDF' 1b,wa,wa) >(wa,wa) >(r-1a,wb,r-
1b,wb,r-1b,r-1b) <(r-1b)
<(wb,wa,wb,wa) <(r-1a,wb,wb)
<(wb,wb) <(r-1b,wa,r-1a,wa,r-
1a,r-1a) <(r-1a)'
March M SAF, TF, AF, CFin, CFid, CFst, >(wa) >(ra,wb,rb,wa) >(ra)
SOF, RDF >(ra,wb) >(rb) >(rb,wa,ra,wb)
>(rb) <(rb,wa)
March Mdsn1 SAF, TF, AF, CFin, CFid, CFst Part1~Part4
RET
March Mdsn1 (part1) SAF, TF, AF, CFin, CFid, CFst >(wa) >(wb,wa) (SLP)
>(ra,wb,wb)
March Mdsn1 (part2) SAF, TF, AF, CFin, CFid, CFst >(rb,wa,ra,wa,ra,wb) >(rb,rb)

March Mdsn1 (part3) SAF, TF, AF, CFin, CFid, CFst <(wa,wb) (SLP) <(rb,wa,wa)

March Mdsn1 (part4) SAF, TF, AF, CFin, CFid, CFst <(ra,wb,rb,wb,rb,wa) <(ra,ra)

March SSSc SAF, TF, AF, CFin, CFid, CFst >(wa) >(wb,wb,rb,rb,wa) >(wb)
>(wb,wb,rb,rb,wa)

Non-March BM detect bit/group write enable >(wa) >(wB5b,rB5b)

faults and datapath shorts. <(wBAb,rBFb) >(wBAa,rBAa)
<(wB5a,rBFa)
MARCH_RET RET <(wb) (SLP) <(rb) >(wa) (SLP)
>(ra)
CB BF >(wa) >(ra) >(wb) >(rb)

March 8R dRDF >(wa,ra,ra,ra,ra,ra,ra,ra,ra)

>(wb,rb,rb,rb,rb,rb,rb,rb,rb)

March 5W SAF, TF, CFst, dWDF, WDF >(wa)

>(ra,wb,rb,wb,wb,wb,wb,wb)

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>(rb,wa,wa,wa,wa,wa)
<(ra,wb,wb,wb,wb,wb)
<(rb,wa,wa,wa,wa,wa)
March RP WDF >(wa) >(ra,wb) >(rb,wa,r-1a)
<(ra,wb,r-1b) <(rb,wa) >(ra)

**March d2PF 'SAF', 'TF', 'AF', 'CFin', 'CFid', '>(n|wa) >(r+1a|n,n|wb)

'CFst', 'SOF', 'RDF', 'Weak WL', >(r+1b|n,n|wb) >(r+1b|n,n|wa)
'2PFavS' >(r+1a|n,n|wa) >(r+1a|n,n|wb)
>(r+1b|n,n|wb) >(r+1b|n,n|wa)
>(r+1a|n,n|wa)'
**March s2PF 'SAF', 'TF', 'AF', 'CFin', 'CFid', '>(n|wa) >(ra|n,ra|n, n|wb) >(rb|n,
'CFst', 'SOF', 'RDF', 'Weak WL', rb|n, n|wa) <(ra|n, ra|n, n|wb)
'2PF1s', '2PF1as' <(rb|n, rb|n, n|wa) <(ra|n)'
***March A2PF-M SAF, TF, AF, CFin, CFid, CFst, >(wa|n) >(ra|ra,wb|r+1a,wb|r-
SOF, RDF, Weak WL, A2PF 1b,rb|rb) >(rb|rb,wa|r+1b,wa|r-
1a,ra|ra) <(ra|ra,wb|r-
1a,wb|r+1b,rb|rb) <(rb|rb,wa|r-
1b,wa|r+1a,ra|ra) <(ra|n)
*: Default testing algorithm of EZ-BIST
** : Support two port memory only
*** : Support dual port memory only
±1: used to increase/ decrease memory address
|: used to separate operation of different port
>: indicates address count from o to the highest address in a memory.
<: indicates address count from the highest address to 0 in a memory.
a: indicates test pattern.
b: indicates inverse “a” test pattern.
MISR (Multiple-Input Signature Register)
LFSR (linear feedback shift register)

Table 6-2 Testing Algorithms for ROM in EZ-BIST

Memory Type Name Address sequence Operation Description

LFSR (rc) Reads and compresses ROM’s content

ROM *ROM Test
N/A Compare MISR Compares the final signature

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6.5. Statistics in TSMC SP Memory

Design Architecture:
✓ Memory: Single-port SRAM *20 and ROM *1
✓ Process: TSMC 55nm
✓ Library: sc9_cln55lp_base_rvt_ss_typical_max_1p08v_125c
✓ NAND Gate area: 1.44 um2

I. The default setting of BFL file: default.bfl

Table 6-3 The Default Setting of BFL file

BFL File Column Default Value

clock_trace no
STIL_test_bench no
asynchronous_reset yes
bist_interface basic
address_fast_y no
algorithm_selection no
background_style SOLID
background_bit_inverse no
background_col_inverse no
bypass_support no
bypass_clock no
bypass_reg_sharing 1
clock_function_hookup no
clock_switch_of_memory yes
clock_source_switch no
clock_within_pll no
diagnosis_support no
diagnosis_data_sharing no
diagnosis_memory_info no
diagnosis_time_info no
diagnosis_faulty_items all
parallel_on no
reduce_address_simulation no
rom_result_shiftout no
Q_pipeline no
algorithm March C+

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BFL File Column Default Value

meminfo 1 Ctr 2 Seq 2 Group

Table 6-4 Synthetic Area of default.bfl

Referenced Library Total Area

top_default_controller 798.120025
top_default_sequencer1 528.84001
top_default_sequencer2 258.480007

top_default_ter_1_1_1 402.840007
top_default_ter_1_1_2 402.840007
top_default_ter_1_1_3 402.840007
top_default_ter_1_1_4 402.840007
top_default_ter_1_1_5 402.840007
top_default_ter_1_1_6 402.840007
top_default_ter_1_1_7 402.840007
top_default_ter_1_1_8 402.840007
top_default_ter_1_1_9 402.840007
top_default_ter_1_1_10 402.840007
top_default_ter_1_1_11 402.840007
top_default_ter_1_1_12 402.840007
top_default_ter_1_1_13 402.840007
top_default_ter_1_1_14 402.840007
top_default_ter_1_1_15 402.840007
top_default_ter_1_1_16 402.840007
top_default_ter_1_1_17 402.840007
top_default_ter_1_1_18 402.840007
top_default_ter_1_1_19 402.840007
top_default_ter_1_1_20 402.840007
top_default_ter_2_1_1 164.160006

top_default_tpg_1_1_1 334.8
top_default_tpg_1_1_2 336.24
top_default_tpg_1_1_3 336.24
top_default_tpg_1_1_4 334.8
top_default_tpg_1_1_5 333.36
top_default_tpg_1_1_6 334.8
top_default_tpg_1_1_7 333.36

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Referenced Library Total Area

top_default_tpg_1_1_8 334.8
top_default_tpg_1_1_9 331.92
top_default_tpg_1_1_10 333.36
top_default_tpg_1_1_11 334.8
top_default_tpg_1_1_12 334.8
top_default_tpg_1_1_13 334.8
top_default_tpg_1_1_14 334.8
top_default_tpg_1_1_15 333.36
top_default_tpg_1_1_16 333.36
top_default_tpg_1_1_17 333.36
top_default_tpg_1_1_18 331.92
top_default_tpg_1_1_19 331.92
top_default_tpg_1_1_20 331.92
top_default_tpg_2_1_1 606.960003

Total 145 references 17092.08019

(Unit:um2)

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II. Refer to Circuit Area Comparison table to change each option in

default.bfl file.

For example, set the option asynchronous_reset to “no”, the circuit area will become
99.085% of the original circuit area, which means the circuit area will decrease by
about 0.91%.

Table 6-5 Area Comparison Table

Process/Lib.: TSMC 55nm/

sc9_cln55lp_base_rvt_ss_typical_max_1p08v_125c Default .bfl
+: Increase, -: Decrease
asynchronous_reset = no -0.91%
address_fast_y = yes 3.08%
clock_within_pll = yes 0.11%
parallel_on =yes 0.96%
reduce_address_simulation = yes 3.10%
rom_result_shiftout = yes 7.05%
Q_pipeline = yes 67.60%

bist_interface = ieee1500 1.03%

bist_interface = ieee1149.1 2.25%

algorithm add March C- 0.44%

algorithm add March C-
0.61%
algorithm_selection = outside
algorithm add March C-
0.61%
algorithm_selection = scan
Note: If the option algorithm_selection set to “outside” or “scan”, the circuit area will increase by
0.17%.

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Process/Lib.: TSMC 55nm/

sc9_cln55lp_base_rvt_ss_typical_max_1p08v_125c Default .bfl
+: Increase, -: Decrease
background_style = 5A 0.93%
background_bit_inverse = yes 2.07%
background_col_inverse = yes 0.67%

bypass_support = wire 14.42%

bypass_support = reg 82.81%
bypass_support = reg
82.81%
bypass_clock = yes
bypass_support = reg
bypass_clock = yes 60.38%
bypass_reg_sharing = 2
bypass_support = reg
bypass_clock = yes 45.74%
bypass_reg_sharing = 4
Note: If the option bypass_support is set to “reg”, the circuit area will increase by 82.81%. If the option
bypass_clock is set to “yes”, the circuit area will increase by 82.81%. However, if
bypass_reg_sharing is set to “2”, the circuit area will only increase by 60.38%. The option
bypass_reg_sharing can effectively reduce the circuit area.

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