Instruction Set of Intel 8085

4.1 INTRODUCTION

An instruction is a command given to the computer to perform a specified operation on given

data. The instruction set of a microprocessor is the collection of the instruction s that the microproces-
sor is designed to execute. The instructions described in this chapter are of INTEL 8085. These in-
st11fcti.ons are of Intel Corporatio n. They cannot be used by other microproc essor manufactu rers. The
programm er can write a program in assembly language using these instruction s. These instruction s
have been classified into the following groups :
1. Data Transfer Group
2. Arithmetic Group
3. Logical Group
4. Branch Control Group
5. 1/0 and Machine Control Group.
Data Transfer Group. Instructions which are used to transfer data from one register to another
register, from memory to register or register to memory, come under this group. Examples are : MOY,
MVI, LXI, LDA, STA etc. When an instruction of data transfer group is executed, data is transferred
from the source to the destination without altering the contents of the source. For example, when
MOY A, B is executed the content of the register B is copied into the register A, and the content of
register B remains unaltered. Similarly, when LOA 2500 is executed the content of the memory loca-
tion 2500 is loaded into the accumulat or. But the content of the memory location 2500 remains unal-
tered.
Artthmallc Group. The instruction s of this group perform arithmetic operations such as addi-
tion, subtractio n; increment or decrement of the content of a register or memory. Examples are : ADD,
SUB, INR, DAD etc. .
Loglcal Group. The instruction s under this group perfonn logical operation such as AND, OR,
compare, rotate etc. Examples are: ANA, XRA, ORA, CMP, RAL etc.
Branch Control Group. This group includes the instruction s for conditiona l and unconditio n-
al jump, subroutine call and return, and restart. Examples are: JMP, JC, JZ, CALL, CZ, RSf etc.
VO and Machine Control Group. This group includes the instruction s for input/ output ports,
stack and machine control. Examples are: IN, our, PUSH, POP, HLT etc.

4.2 INSTRUCTION AND DATA FORMATS

Intel 8085 is an 8-bit microproc essor. It handles 8-bit data at a time. One byte consists of 8 bits. A
memory location for Intel 8085 microproc essor is designed to accommod ate 8-bit data. If 16-bit d~ta
are to be stored, they are stored in consecutiv e memory locations. The address of a memory location
is of 16 bits i.e. 2 bytes.
The various techniques to specify data for instruction s are :
 MICROPROCESSORS AN D
FUNDAMENTALS OF MICROCQMpl.JTER
4.2 S
. . the ins tru cti on itse lf.
(1)8-bit or 16-bit dat a ma y be d i·rectly giv en in
. 0 ort or I/0 dev ice , wh ere d ata 'd
(i,)The add res s of the me mo ry locatio res1 es, ma y be
n, 1/ P
g iven in the ins tru ctio n itself. . .if'ed
(ii,) In som e ins tru ctio ns
onl y one regis · ter 1s spe c 1 · Th e con ten t of the spe cif ied reg iste r is
. h
der sto od tha t t e o the r op era nd is in the acc um ula tor .
one of the ope rand s. Itis un .
. .
(iv) Som e ins tru ctio 'fy two re01sters. Theco n ten ts of the reg iste rs are the req uir ed dat a.
ns spec•
M In som e instructions dat a is impo · t ins tru cti ons of thi s typ e ope
rat e on the
lied. Th e mo s
con ten t of the acc um ula tor.
Du e to different wa ys of specify . ti ns the ma chi ne cod es of all
ing dat a for ins tru c O ' ins tru ctio ns
are not of the sam e len gth .
8085 ins tru ctio ns as des cnb ed b l
There are thr ee typ es of the Intel • •
(1) Single-Byte Ins tru ctio n e ow ·
(2) Two-Byte Ins tru ctio n
(3) Three-Byte Ins tru ctio n
Thi s has alre ady bee n dis cus sed
in Ch apt er 3; see det ails .
4.3 ADDRESSING MODES
Eac h ins tru ctio n req uir es cer tain
dat a on wh ich it has to ope rat e.
tha t the re are var iou s tec hni que s It has alr ead y bee n exp lain ed
to specify dat a for ins tru ctio ns. Th
ing modes. Int el 8085 use s the foll ese tec hni que s are cal led address
owing add res sin g mo des : -
l. Dir ect add res sin g
2. Reg iste r add res sin g
3. Reg iste r ind irec t add res
sin g
4. Im me dia te add res sin g.

4.3.1 Direct Addressing

In this mo de of add res sin g the add
Exam ples are : res s of the ope ran d (da ta) is viv
o·
en in th · tru · · If
em s cti on 1tse .
(1) STA 2400 H Store the con ten t of the acc um ula
32v 00, 24 tor in the m •
The above instru ctio n in the cod e
for m
em ory 1oca ho n 240 0 H .
In this ins tru ctio n 2400H is the
ins tru ctio n itBelf. The 2nd and 3rd me mo ry add res s wh ere dat · ·
byt es of the ins tru cti . a is to be sto
tio n. He re, it is und ers too d tha t
the source of the dat a is on spe cify the add res sredf.th It is giv en in the
(2) IN 02
acc um ula tor. 0
e me mo ry Ioca -
Read data from the por t c.
DB, 02 Ins tru ctio n in the cod e form.
In this ins tru ctio n 02 is the add res
He re, it is imp lied tha t the des tina s of the por t C of an I/ o rt f
the add res s of the por t. tion is the acc um ula tor. Th ~~ d
~m wh ere ~e dat a is to be rea
n yte of the ins tru ctio n spe cifi d.
es
4.3.2 Register Ad dn ,ui ng
In reg iste r add res sin g mo de
spe cif ies the add res s of the registethe ope ran d is in one of the gen e
r(s) in additiQn to the ope rati o rta 1
bpu rpo se reg iste
( 1) MO VA , B Mo ve the con ten t of reg iste r to n o e per for me d Ers. Thle opc ode
78 . 8 . · xam p es are :
The ins tru ctio n in the cod e form reg ~~ rA
. ·
INSTRUCTION SET OF INTEL 8085
4.3

(2) ADD B Add the content of register B to the content of register A.

80 The instructio ninthecode form .
In Exa rnple 1 the opcode for MOY A, Bis 78H. Besides the operation to be performe d the opcode
also specifies source and destination registers. The opcode 78H can be written in binary form as
01111000 . The first two bits, i.e. 01 are for MOY operation, the next three bits 111 are the binary code
for register A, and the last three bits 000 are the binary code for register B.
In Example 2 the opcode for ADD Bis 80H. In this instruction one of the operands is register B
(i ts content is one of the data) which is indicated in the instruction itself. In this type of instruction
(arithme tic group) it is understo od that the other operand is in the accumulator. The opcode 80H in
the binary form is 10000000. The first five bits, i.e. 10000 specify the operatio n to be performe d, i.e.
ADD. The last three bits 000 are the binary code for register B for 8085 microprocessor.

4.3.3 Register Indirect Addressing

In this mode of addressi ng the address of the operand is specified by a register pair. Example s
are :
(1) LXI H , 2500 H Load H-L pair with 2500 H.
MOVA, M Move the content of the memory location, whose address is in
H-L pair (i.e. 2500 H) to the accumul ator
HLT Halt.
In the above program the instructio n MOY A, M is an example of register indirect addres.sing.
For this instructi on the operand is in the memory. The address of the memory is not directly given in
the instructi on. The address of the memory resides in H-L pair and this has already been specified by
an earlier instructi on in the program, i.e. LXI H, 2500 H.
(2) LXI H, 2500 H Load the H-L pair with 2500 H.
ADDM Add the content of the memory location, whose address is in H-L
pair (i.e. 2500 H), to the content of the accumulator.
HLT Halt.
In this program the instructi on ADD Mis an example of register indirect addressin g.

4.3.4 Immediate Addressing

ln immedia te addressi ng mode the operand is specified within the instructi on itself, examples
are:
(1) MVIA,0 5 Move 05 in register A.
3E, 05 The instruction in the code form.
(2) ADI06 Add 06 to the content of the accumul ator.
C6, 06 Theinstr uctionin thecodef orm.
In these instructio ns the 2nd byte specifies data. ·
(3) LXI H, 2500 is an example of immedia te addressing. 2500 is 16-bit data which is given in, the
instructio n itself. It is to be loaded into H-L pair.

4.3.5 lmptlctt Addresalng

There are certain instructions which operate on the content of the accumul ator. Such instructions
do not require the address of the operand. Examples are : CMA, RAL, RAR etc.
 - . - ~• I

FUNDAMENT F MICROPR
ALS O OCESSORS
4.4 AND MICRO
CQM
PU°Tt~
4.4 STATU
S FLAGS
. h ic h in d ic a te
There is a set s ta ~ s ( c o n
of five fhp~tl :~ ti o ~ 1 :: :t
arithmetic a n o p;t'~as a lr e a d f 3 ~ f te r the
d logic instru y b e e n d 1 sc executionot
cttons. u ss e m
4 S S y..••.e O L S AND ABBRE
VIATIONS
. The symb hi ed
ols a n d a b b e rv
ia h o n s w c h h a v e b e e n u s w h il e e x p la in e in g In te
are a s follows l 8085 instruct
: . . ir-...
Sym bol/Abbr("",J1at Meaning "' Ill
1ons
addr 16-bit a d d ress 0 f th e m e m o ry .
lo c a ti o n .
d a ta 8-bit d a ta .
d a ta 16 16-bit d a ta .
T, T1 , T2, O n e o f th e re
g is te rs A, B,
A , B ,C , D , H C, D, E, H o r
,L 8-bit register L,
A
Accumulator
H-L
Register p a ir
B -C H -L
Register p a ir
0 -E B -C
Register p a ir
PSW D-E
P ro g ra m S ta
M tu s W o rd
M e m o ry w h o
H s e a d d re ss is
A p p e a ri n g a in H -L p a ir
t th e e n d o f a
e.g. 2 5 0 0 H . g ro u p o f d ig
rp it s s p e c if ie s
O n e of th e re hexadecimal,
gister p a ir s. T
m a d e as d e sc h e re p re s e n
ri b e d b e lo w : ta ti o n o f a re
B represents g is te r pair is
B -C p a ir , B
registe r. D re is h ig h o rd
p re se n ts D-E e r re g is te r a
lo w order reg p a ir , D is h ig n d C lo w ord
ister. H re p re h o rd e r re g is ~r
a n d L lo w o rd se n ts H -L p a te r a n d E 15
e r register. SP ir , H is h ig h
h ig h o rd e r 8 re p re se n ts 1 o rd e r regist~
rh b it s a n d SPL 6 -b it s ta c k p r
T h e h ig h o rd lo w o rd e r 8 b it s o f re o in te r, S P H 15
rl er register o f g is te r SP.
T h e lo w o rd a re g is te r p a ir .
pC e r register o f
16-bit p ro g ra a re g is te r p a ir
m counter, P .
o rd e r 8 b it s o C H is
cs f register PC. h ig h o rd e r 8
b it s a n d P C
C a rr y st a tu s. L low
[1
[ [] ] T h e c o n te n
ts of a regis
ter id e n ti fi e d
T h ~ conte1:'t w it h in b ra c k
o f the m e m o e t.
reg1Ster p a ir id ry lo c a ti o n
I\ entified w it h w h o s e a d d re
A N D o p e ra in b ra c k e ts . s s is in the
V ti on
O R operation
V o r EB .
E X C L U S IV
E -OR
Move d a ta in
the
Exchange con direction o f arrow.
tents.
 4.5
INSTRUCTION SET OF INTEL 8085

4.6 INTEL 8085 INSTRUCTIONS

and some seldom used by the
Some of Intel 8085 instmctions are freque ntly, some occasi onally
ctions to under stand simple
progr amme r. It is not necess ary that one should learn all the instru
ctions such as MOV, MVI, LXI,
progra ms. TI1e begin ner can learn about 15 to 20 impor tant instru
LOA, LHLD , STA, SHLD , ADD, ADC, SUB, JMP JC, JNC, JZ, JNZ,
INX, OCR, CMP etc., and start to
progra ms he can under stand new
under stand simpl e progra ms given in Chapt er 6. While learni ng
instru ctions which he has not learnt earlier.
ations of the most instru c-
· The opera tion codes (opcod es) are given in Appen dix II. The explan
tions are given in the subse quent subsec tions.

4.6.1 Data Transfer Group MOV r1, r2

er).
(Move data; Move the content of the one register to anoth
1.
[rd f-- [r2J. States: 4. Flags: none. Addre ssing: registe r.Mac hine cycle:
instru ction MOV A, B moves
The conten t of regist er r 2 is moved to registe r r 1. For examp le, the
moves the conten t of registe r A to
the conten t of regist er B to registe r A. The instru ction MOV B, A
period . One clock period is called
registe r B. The time for the execu tion of this instru ction is 4 clock
State. No flag is affecte d.
MOV r, M. (Move the conten t of memo ry to register).
Mach ine cycles: 2.
[r] f-- [[H - L]]. States: 7. Flag none. Addre ssing: registe r indire ct.
is move d to regist er r.
The conte nt of the memo ry location, whose addres s is in H-L pair,
Exam ple
LXI H,200 0H Load H-L pair by 2000H.
MOV B,M Move the conten t of the memo ry locatio n 2000H to registe r B.
HLT Halt.
In this examp le the instru ction LXI H, 2000 H loads H-L pair with 2000 H which is the addre ss of
conten t of the memo ry locatio n
a memo ry locatio n. Tnen the instru ction MOV B, M will move the
2000H to regist er B.
MOV M, r. (Move the conten t of registe r to memo ry).
ne cycles: 2.
[[H-L ]] f-- [r]. States: 7. Flags: none. Addre ssing: reg. indire ct. Machi
by H-L pair. For examp le,
The conten t of registe r r is move d to the memo ry locatio n a d ~
n whose addre ss is in H-L pair.
MOV M, C move s the conten t of regist erC to the memo ry locatio
MVI r, dllla. (Move imme diate data to register).
[r) f-- data. States: 7. Flags: none. Addre ssing: imme diate. Machi ne cycle: 2.
ction is the data which is
The 1st byte of the instru ction is its opcod e. The 2nd byte of the instru
moved to regist er r. For examp le, the instru ction MVI A, 05 moves
05 to registe r A. In the code form
it is writte n as 3E, 05. The opcod e for MVI A is 3E and 05 is the
data which is to be move d to regise r
A.
MVI M, data. (Move imme diate data to memo ry).
[[H - L]) f-- data. States: 10. Flags: none. Add~ ing: immed iate/re
g. indirect. Machi ne cycle: 3.
The data is moved to memo ry locatio n whose addre ss is in H -L pair.
Example
LXI H, 2400H Load H-L pair with 2400H.
MVIM , 08 Move 08 to the memo ry locatio n 2400H .
HLT Halt.
I 4.6

\ the
.
inst ruc
FUNDAMENTALS OF MICROPROCESS

t· LXI H 2400 H loa ds H-L pai

ORS ANo Mic~

r
.
wit h 2i1f\ n
,.
'

ln the above examp e . Th th10n,·nstruct, ·11 ~

lJ ·,
ion MV I M, 08 w1 mo ve 08 to rn •Q<:h . q i;,,1.,
address of a memory 1~a .hon · . en e .
2400H. ln the code form ,tis wntte1~ as 36 08. The opc ode for MVI M 1s 36 and 08 is erna th-
r,, \11.
., I():~~
, H
. be ed ecta ~ .~
1s to mov to the memory \ocahon 2400 .
LXI data 16. (Load register pair unmed1 ) . . . '
ate .
rp,data 16 bits lrh} f--8 MSBs, [rl] f--8
lrp1...... F\ . ' Addressing: immediaL5B te.
s of data.
Machine cycles: 3.
States: 10. ags. none.
·. . tructi'on loads l6-bit immediate dat . . . Thi . .
Th1s ms a into register pai r rp. s instruction is for .
. h' h rd reoister is mentioned after the . · F
. or examp Ie, Hmt mstructt~
pa1r;on1y 1g o er o· instruction · he ·
Hstands for H-L pair. Similarly, LXI B1s . . I
for B-C pair. LXI H, 2500H oa _s 25 d · °"l.X!
l500H denotes that the data 2500 is in hex . 00~ mto H-L pair.H 'Nii
adecimal. In the code form it ~s wn tten
1 st byte of the instruction 21 is the opcode for as 21, 00, 2S. The
LXI H. The 2nd byt e _O? 1s 8 LSBs_of
is \oaded into register L. The 3rd byt the data and it
e 25 is 8 MSBs of the data and it 1s loa
ded mto register H.
LOA lddr. (load Accumulator direct).
lAl .-{addr]. States: 13. Flags: none. Add
ressing: direct. Machine cycles: 4.
The content of the memory location, who
se address is specified by the 2nd and
instruction; is loaded into the accumulator 3rd bytes of the
. The instruction LOA 2400 H will loa
memory location 24001:1 into ~e accumul d the content of the
ator. In the code form it is written as 3A,
3A is the opcode of the instruction. The 00, 24. The 1st byte
2nd byte 00 is of 8L.5Bs of the memory
24 is 8 MSBs of the memory address. addres.c;. The 3rd by!e
STA Addr. (Store accumulator direct).
\addr) +- [A). States: 13. Flags: none.
Addressing: direct. Machine cycles: 4.
The content of the accumulator is stor
the 2nd and 3rd byte of the instructi ed in the memory locatio h ddr · pecifi'ed by
memory location H. 2000H will . n w ose a ess IS s
2000 on. STA store the content of the accumulat .
or m the
LHLD lddr. (Load H-L pair direct).
IL}+- [addr), [Hl +- [addr + 1). States: 16.
The content of the memory Flags· none Add . . .
. . . locati h · ·. ressmg: drrect. Machine cycles: 5.
on,
instruction, is loaded into register L. The w ose address 15 specifi'ed b
H. For example, LHLD 2500H will load content O f th Ythe 2nd of the
the co t t ~ :x t memory location is and 3rd bytes .
The content of the memory location 250\H loaded into register
is n deedn ~ e ~emory location 250
1oa mto register H 0 H into register L.
SHLD addr. (Store H-L pair direct)
[addr] +- [L], [addr + 1] +- [H]. States· l .
The content of register Lis stored in tt-.e' 6 Fla
me!s: none. ~ddressing: direct. Machin
and 3ro bytes of the instruction. The con e cycles: 5
tent f 0 ~ locat!on whose address is spec
example, SHLD 2500H will store the content
of register H is stored in the memory loca if st
reg_' er ~ is stored in the next memory
tion ;~, ~~r Lm the memory location 250 locatio~. For
ified by the 2nd

LDAX rp. (lO AD accumulator indirect) 0H. The content

[A) +- ([rp)l. States; 7. Flags; none. Add
The content of the memory location reesin . re . . .
w'-- -· gd. giSler mdlreCt. Machine
accumulator. For exampIe, LDAX B will ' 'IU!ie a dress 1 · h cycles: 2.
in the B-C pair, into the accumulator. Thisload the con te t sfinht e register pair rp is loaded into
• · th
instru t· . n ° t e memory location' e
STAX rp. (Store accumulator indirect) c ion 1s used 1 f , who se addr esS ·
15
on Y or B-C and D-E regi.ster pall'S •
·
[(rp)) +- (A). States: 7. Flags: none. Add
ressin . , . .
g. regiSler indirect. Machine cycles:
2.
 :', .. .. ~ /0 vrr t- y T n • . 1

AM FN1ALS OF MIOlOP l~OCF

~UN O 88<Jl1rJ AIID IAICR,-.,
t6 "~, (A ~
11
I onI.XI II ' 24(X) II load11 11-1. pair with 24'XJ fl "'h'
~
In 1\w i\\)IWl' ,•xilmp l•l
l
ht•lm11ru<1
. h, tru ction MVI M, 08 w1·11 mc .
.
"d(lrr,.11 ot i\ m1•mory Ioco ,Ion I hen I c 1nH 1vc 08 lo mcrn,.. Id, ~&•
.
?4(~1I. In 1\w rode form II lfi wn. • '.\() 08 The opcode for MVI Its
M•
36 and f.t8
"Y I,· ,
llc~ aH. , . iHtht da ~ll,~1
,11 toIx• moved lo lhc mt ta ~ihi.,l
,nory local1on 24!X)I I. .
LXI rp, data 16. (Lo,1d rci;i11lcr
pair immediate) .
\rp\ 4 data 16 blltt, \rh\ i- 8 MS!is, \rll 8
~ LSBs of da_ta. .
State,;: 10. Plag11: none. Add rt'ffsm · . · m"dta ' tc Machine cycles. 3.
. . g. im " .· . .
Th,s m11tru ct·,on l""
,,..
ds l6-bit immediate data int o register pair rp. This 1ru
. . . .
,tru cbo
p:iir;only hii;h ordL'f rcgi!!tcr is me
ntiont.-d after th~ instructio . F I H · h n· 1s for rPo,i .,..
11 stand!! for 11-Lpair.Similar n. or cx amp c, i_n t e ms tru~io-t't" l!!I
n I.Xi
ly, LXI Bis for B-C pair. LXI H, 250
~ lH dcnot1-'8 that the data 250 0H load_s ~SOO~ mto H-L pa1r. H
0 is in hcxadticimal. ln the code for With
ht byte of the instruction 21 m 1t 1s written as 21, 00, 25. 'J'ht
is the opcode for LXI H. The 2nd
is loadc.-d into register L. The 3rd byte _O~ is 8 LS&_of the data
byte 25 is 8 MSBs of the data and and it
1t 1s loa ded mto regisU!r H.
LOA lddr. (Load Accumulator
direct) .
\Al +-\addrj. States: 13. Plags: none. Ad
dressing: direct. Machine cycles
The content of the memory locatio : 4.
n, whose address is specified by
instruction; is loaded into the acc the 2nd and 3rd bytes of the
umulator. The instruction LOA
me~ory location 2400 ~ intot~ 2400 H will load the content of
accumulator. In the code form the
3A 1s the opcode of the instru it is written as 3A, 00, 24. The
ction. The 2nd byte 00 is of 8 l.SB 1st byte
24 is 8 MSBs of the memory add s of the memory address. The
ress. 3rd byte
STA Addr. (Store accumulator
direct).
\addrJ +- IAJ .States: 13. Flags: non
e. Addressing: direct. Machine
The content of the accu~ula cycles : 4.
tor _is stored in the memory locatio
the 2nd and 3rd byte of the instru n whose address is 'fied by
memory location 2000H. ction. SfA2000H will store the 8
co tent f th pea l · the
n o e acc umu ator m
LHLD addr. (Load H-L pair dire
ct).
~~I +- laddr], IHl +- laddr+ lJ.
Ihe content of the memory locStates: 16. Flags: none. Addressin . . .
ation, whose add . . . g. duect. Machine cycles..
ini,lruction, i1, loaded into registe
H. For example, LHLD 2500H
r L. The content f
will load the con:nt ~: t me
:S 18
speahed by the 2nd and 3rd byt
es
5.
of the
The content of the memory loc 0 mory loca~ion is loaded into r~
ation 2501H is 1-. 1.. . . ~m or y location 2500 H into
ter
IHLD lddr. (Store H-L pair dir ~ into reg1Ster H register L.
tct)
laddr} +- lLl, laddr + 11 +- lH]. Sta .
The content of register Lis stored tes: 16. Fla : none . .
in the gs · AddresSmg: direct. Machine cyc
and 3rd bytes of the instruction les: 5
. The co nt en t~ l~at_,on wh
exa mple, SHLD 2500H will store
of register His stoced in the memo
the content of ;:::e
ry location 250lH~ Lm thc memo
~ address is specified by the
~ •s st0red m the nex t memory Jocati 2nd
~. for
LOAX rp. (LOAD accumulator ind ry location 2500H . The content
irect)
[A) +- [lrp]I. States; 7. Flags; non
The content of the memory loc
e. Ad dress· . .
accumulator. For example, LDAX atio n, wh osemgaddreg1, ster in
· ct·
uect. Machine cycles: 2.
B will load the ress 18 in the reg
in the B-C pair, into the acc umula ister pair rp, is loaded into the
tor. This instrucn':°"t~nt of the me
STAX rp. (Store accumulator on is used onl f 8-C mo ry location, whose address is
indirect) Y or . .
([rp)) ~ [A]. States: 7. Flags: non and D-E registe r pairs.
e. Addressing: regist . . d'
er in •rect. Machine cycles:
2.
INSTRUCTION SET OF INTEL 8085 4.7

The content of the accumulator is stored in the memory location whose address is in the register
pair rp. For example, STAX D will store the content of the accumulator in the memory location whose
address is in O-E pair. This instruction is true onJy for register pairs 8-C and D-E.
XCHG. (Exchange the contents of H-L with D-E pair)
[H-L] ~➔ [D-E]. States: 4. Flags: none. Addressing: register. Machine cycles: 1.
The contents of H-L pair are exchanged with contents of D-E pair.

4.6.2 Arithmetic Group

ADD r. (Add register to accumulator)
[A]~ [A]+ [r]. States: 4. Flags: all. Addressing: register. Machine cycle: 1.
The content of register r is added to the content of the accumuJator, and the sum is placed in the
accumulator.
ADD M. (Add memory to accumulator)
[A]~ [A]+ [[H-L]]. States: 7. Flags: all. Addressing: reg. indirect, Machine cycles: 2.
The content of the memory location addressed by H-L pair is added to the content of the ac-
cumulator. The sum is placed in the accumulator.
ADC r. (Add register with carry to accumulator.)
[A]~ [A]+ [r] + [CS]. States: 4. Flags: all. Addressing: register. Machine cycles: 1.
The content of register r and carry status are added to the content of the accumulator. The sum
is placed in the accumulator.
ADC M. (Add memory with carry to accumuJator)
[A]~ [A] + [[H-L]] [CS]. States: 7. Flags: all. Addressing: reg. indirect. Machine cycles: 2.
The content'al the memory location addressed by H-L pair and carry status are added to the content
of the accumulator. The sum is placed in the accumulator.
ADI data. (Add immediate data to accumulator)
[A]~ [A)+ data. States: 7. Flags: all. Addressing: immediate. Machine cycles: 2.
The immediate data is added to the content of the accumulator. The 1st byte of the instruction is
its opcode. The 2nd byte of the instruction is data, and it is added to content of the accumulator. The
sum is placed in the accumuJator. For example, the instruction ADI 08 will add 08 to the content of
the accumulator and place the resuJt in the accumuJator. In code form the instruction is written as
C6, 08.
ACI data. (Add with carry immediate data to accumulator)
[A] ~ [A]+ data+ [CS]. States: 7. Flags: all. Addressing: immediate. Machine cycles: 2
The 2nd byte of the instruction (which is data) and the carry status are added to the content of
the accumulator. The sum is placed in the accumulator.
DAD rp. (Add regisfv.:r paid to H-L pair)
[H-L] ~ [H-L] + [rp]. States: 10. Flags: CS. Addressing: register. Machine cycles: 3.
The contents of register pair rp are added to the contents of H-L pair and the result is placed in
H-L pair. Only carry flag is affected. ,
SUB r. (Subtract register from accumulator) I
[A] ~ [A] - [r]. States: 4 Flags: all. Addressing: register. Machine\:ycles: 1.
The content of register r is subtracted from the content of the accumulator, and the result is
placed in the accumulator.
SUB M. (Subtract memory from accumulator).
 OF MICROPROCESSORS AND MICROCoMPt ..,._
FUNDAMENTALS 'Vltf\s

4.8 . II Addressing: reg. indirect. Machine cycles: 2

[A] r [Al - [[H-L]]. States: 7. F~ags. a . ed b H-L pair is subtracted from the contentof ~-
nt of the memory locat10n address y ,.."
ThelcotnteThe result is placed in the accumulator.
accumu a or. 'th borrow) . .
. ter from accumulator w1
SBB r. (Subtract reg1s . 11 Addressing: register. Machine cycles: 1.
[A] r [A] - [r] - (CS). States: 4· Flags. a · btracted from the content of the accumulator.1h
The content oi register r and carry status are su e
result is placed in the accumulator. .
SBB M. (Subtract memory from accumulator with bo~w). . . . .
[A] +- IA] _ [(H-L]] _ (CS]. States: 7. Flags: all. Addressing: reg. md1rect. Machine cycles. 2.
The content of the memory location addressed by H-L pair and carry status are subtracted from
the content of the accumulator. The result is placed in the accumulator.
SUI data. (Subtract immediate data from accumulator)
[A] r (A] -data. States: 7. Flags: all. Addressing: immediate. Machine cycles: 2.
The 2nd byte of the instruction is data. It is subtracted from the content of the accumulator. The
result is placed in the accumulator. For example, the instruction SUI 05 will subtract 05 from the
content of the accumulator and place the result in the accumulator. In the code form the above in-
struction is written as 06, 05.
SBI data. (Subtract immediate data from accumulator with borrow).
[A] r [A] - data - [CS]. States: 7. Flags: all. Addressing: immediate. Machine cycles: 2
The data and carry status are subtracted from the content of the accumulator. The result is placed
in the accumulator
INR r. (Increment register content)
[r] r [r] + 1. Stat~: 4. Fl~gs: all except carry flag. Addressing: register. Machine cycle: 1.
The content of register r 1s incremented by one. All flags except cs are affected.
INR M. (Increment memory content)
. .
llH-L]] r [[H-L]] + 1. States: 10. Hags: all except carry flag · Addressmg. . d'
Machine cycles: 3. reg. m u-ect.
The anlent of the memory location addressed by H-L pair
. . .
1s mcremented by one. All flags ex-
ceptCSare affected.
DCR r. (Decrement register content)
[r] ..,_ [r] - 1. States: 4. Flags: all exc t fla .
The oontent of register r is decremeniedc:rr g, Address mg: register. Machine cycles: 1.
DCR II. (Deere y one. All flags except CS are affected.
ment memory content)
llH-L]] r [(H-L]] _ 1 Sta .
cycles: 3. .
. d 1rect.
. tes. 10. Flags: all except carry flag. Addressing·. reg. m .
Machine
The content of the m .
except CS a.ffected. emory 1<>cation addressed bY H -L pair . .
is decremented by one. All flags
INX are_
rp. (tncrement register pair)
[rpj [rp) + 1. States: 6. Flags·•none. Address· . .
..,_
The content of the register pair rp . . mg. register. Machine cycles . 1
18 II\Cremented b · ·
DCX rp (Decrement register pair) Yone. No flag is affected.
[rp] ..,_[rpJ - 1. States: 6. Flags: none. Ad .
The content of the register pair rp is . d dressmg: register. Machine .
ecremented b eye1es. 1.
. y one. No fL1g is affected.
...... -
INSTRUCTION SET OF INTEL 8085 4.9

DAA. (Decimal adjust accumulator)

States: 4. Flags: all. Machine cycle : 1.
The instruction DAA is used in the program after ADD, ADI, ACI, AOC, etc instructions. After
the execution of ADD, AOC, etc instructions the result is in hexadecimal and it is placed in the ac-
cumula.tor. The DAA ~~struction operates on this result and gives the final result in decimal system.
It uses carry and aux1hary carry for decimal adjustment. 6 is added to 4 LSBs of the content of the
accumulator if their value lies in between A and For the AC flag is set to 1. Simjlarly, 6 is also added
to 4 MSBs of the content of the accumulator if their value lies in between A and For the CS flag is set
to 1. All status flags are affected. When DAA is used data should be in decimal numbers.

4.6.3 Logical Group

The instructions of this group perform AND, OR, EXCLUSIVE-OR operations; compare, rotate
or take complement of data in register or memory.
ANA r. (AND register with accumulator)
[A] f- [A]" [r] . States: 4. Flags: all. Addressing: register. Machine cycles: 1.
The content of register r is ANDed with the content of the accumulator, and the result is placed
in the accumulator. All status flags are-affected. The flag CS is cleared, i.e. it is set to 0. Auxiliary carry
flag AC is set to 1.
ANA M. (AND memory with accumulator)
[A] f- [A]" [[H-L]]. States: 7. Flags: all. Addressing: reg. indirect. Machine cycles: 2.
The content of the memory location addressed by H-L pair is ANDed with the accumulator. The
result is placed in the accumulator. All flags are affected. The CS flag is set to Oand AC to 1.
ANI data. (AND immediate data with accumulator)
[A] f- [A]" data. States: 7. Flags: all. Addressing: immediate. Machine cycles: 2.
The 2nd byte of the instruction is data, and it is ANDed with the content of the accumulator. The
result is placed in the accumulator. The CS flag is set to Oand AC to 1.
ORA r. (OR register with accumulator)
[A] f- [A] v [r] States: 4. Flags: all. Addressing: register. Machine cycles: 1.
The content of register r is ORed with the content of the accumlilat()r. The result is placed in the
accumulator. All status flags are affected. Carry and auxilary carry are cleared i.e. the CS and AC flags
are set to 0.
ORA M. (OR memory with accumulator).
[A] f- [A] v [[H-L]]. States: 7. Flags: all. Addressing: reg. indirect. Machine cycles: 2.
The content of the memory location addressed by H-L pair is ORed with the content of the ac-
cumulator. The result is placed in the accumulator. The CS and AC flags are set to 0.
ORI data. (OR immediate data with accumulator)
(A] f- [A] v data. States: 7. Flags: all. Addressing: immediate. Machine cycles : 2.
The 2nd byte of the instruction is data, and it is ORed with the content of the accumulator. The
result is placed in the accumulator. All status flags are affected. The CS and AC flags are set 0.
XRA r. (EXCLUSIVE - OR register with accumulator)
[A] f- [A] V [r] States: 4. Flags: all. Addressing: register. Machine cycles: 1.
The content of register r is EXCLUSIVE - ORed with the content of the accumulator. The result
is placed in the accumulator. All status flags are affected. The CS and AC flags are set to 0.
XRA M. (EXCLUSIVE - OR memory w ith accu mulator)
 F MICROPROCESSORS AND MICROCQM~.
FUNDAMENTALSO - ,~

4.1 O . . reg indirect. Machine cycles: 2.

· ll Addressing. . USIVE ORed ·
H L]) States: 7. Flags. a . b H-L pair is EXCL - with thee
(A]+- (A] V ll - · ory location addressed Y tor All status flags are affected. The~
The content of the mem ult is placed in the accumu1a .
tent of the accumulator. The res
and AC flags are set to 0. . . data with accumulator) .
(EXCLUSIVE - OR immediate . ·. diate. Machine cycles: 2.
XRI dlta. ll Addressing: imme h f
(A]+- (A] V data. States: 7. Flags: a . . . EXCLUSIVE-ORed with t e content o the ac.
The 2nd byte of the instruction is data, and it 1n
flags are affected. The CS and AC flags are set
cumulator. The result is plared in the accumulator.
to 0.
CMA. ~omplement the accumulator? des : 1. Addressing : implicit. . .
[A]+- (A]. States: 4. Flags: none. Machine cy l . btained and the result is placed m the
l 's complement of the content of the accumu_ator is o ber Oi~ replaced by 1, and 1 by 0. For
accumulator. To obtain the l's complement of a binary num
example, one's complement of 1100 is 0011.
CUC. (Complement the carry status)
[CS]+- [CS]. States: 4. Flags: CS, Machine cycle: 1.
The CS flag is complemented. Other flags are not affected.
STC. (Set carry status)
[CS]+- 1. States: 4. Flags: CS. Machine cycles: 1.
The status flag CS is set to 1. Other flags are not affected.
CUP r. (Compare register with accumulator)
(A] - [r]. States 4. Flags: all. Addressing: register. Machine cycles: 1.
The content of register r is subtracted from the content of the accumulator and status flags are set
according to the result of the subtraction. But the result is discarded. The content of the accumulator
remains unchanged.
CMP M. (Compare memory with accumulator)
[A] - [[H-L]]. States: 7. Flags: all. Addressing: reg. indirect. Machine cycles: 2.
The content of the memory location addressed by H-L pair is subtracted from the content of the
accumulatoi and status flags are set according.to the result of the subtraction. But the result is dis-
anted The content of the accumulator remains uncharged.
CPt dlta. (Compaie immediate data with accumulator)
[Al - data. Slates: 7. Flags: all. Addressing: immediate. Machine cycles: 2.
The
The sta: 2nd '"-.,,., ol the in1truction
. · data, and it
11 · 15
· subtracted from the content of the accumulator.
tus flags are set a':'ording to the result of subtraction. But the result is discarded The content
of the accumulator remams unchanged. ·
RLC .. (Rotate accumulator left)
rAn+t1 +-[An], [Ao) +-[A1], [CS] +-[A7].
States: 4. Flags: CS. Machine cycles . l Add . . . .
Th · · - ltismg: 1mphcit.
e content of the accumulator is rotated Wt b . .
moved to carry bit as well as to the 1.ero bit f the Yone bit. The seventh bit of the accumulator 15
o accumulator. Only CS flag is affected. See Fig. 4.1

B
CARRY STATUS
--r--r,----r---r---=1
Ll:'.-::-r-Al
,
. . , Ar
ACCUMULATOR

Fig. 4·1 Schematic o·iag,am for RLC.

~
CTION SET OF INTEL 8085 4.11
iNSTA U

RAC. (Rota te accum ulato r right)

IA7] r (Ao], !CS) t - [Ao], _IAnl t-- (A 11 , 1) .
States: 4. Flags : CS. Mach me cycle s : l. Addr essin g: impli cit.
th
The conte nt of e ~ccu mula tor is rotate d right by one
bit. The zero bit o f the acc umul ator is
ed . See Fig. 4 _2 _
moved to the seven th bit as well as to ca rry bit. O nly CS flag is affect

1
L,L, ·GJ LJ I I
A(ClJMUL A TOR
I· j
0}

Fig. 4.2 Schem atic Diagram for ARC.

RAL (Rota te accum ulato r left throu gh carry )

[An+iJ t-- [A"], [CS) t-- [A7], [Aol t-- [CS].
States: 4. Flags: CS. Mach ine cycle s : 1. Addr essin g: impli cit.
gh carry. The seven th bit o f the ac-
The conte nt of the accum ulato r is rotate d left one bit throu
zero bit of the accum ulato r. On ly carry
cumulator is move d to carry , and the carry bit is move d to the
flag is affected. See Fig. 4.3.

~~-ICARRY STATUS
AJ I
ACCUMULATOR

Fig. 4.3 Schematic Diagram for RAL.

RAR. (Rota te accum ulato r right throu gh carry )

[A"] t-- [An+ i), [CS] t-- [Ao], [A7] t-- [CS]
State s: 4 Flags : CS. Mach ine cycle : 1. Addr essin g impli cit.
gh carry. The zero bit of the ac-
The conte nt of the accum ulato r is rotate d right one bit throu
th bit of the accum ulato r. OnJy CS flag is
cumu lator is move d to carry, and the carry bit to the seven
affected. See Fig. 4.4.

CARRY STATUS ACCUMU LATOR

Fig. 4.4. Schematic Diagram for AAA.

4.6.4 Branch Grou p

o f the pro~1..-1m. Thert ' Mt· t\\'t' t:'F'"'"
The instru ction s of this group chang e the norm al seque nce
condi tinn,1I hr,111,.:h in:--tntL tiL1ns tr.in: ,kr
of branc h instru ction s: cond itiona l and uncon ditio nal. The
is ~t~tisfit',i . Tlw u 11t·t)n d itiL1 n,d ~rant :h
the progr am to the specified label when certai n cond ition
d1tton .1ll~ .
instructions trans fer the progr am to the speci fied label uncon
ction s1~l't·ifi,,d b~· th,, .1ddrt·ss).
JMP addr (label). (Unc ondit ional jump : jump to the instru
. M.ich irw t·~·c ks: ] .
[PC] t-- Label. States: 10. Flags: none . Addr essin g: imme diate
the L1_h(•I wlw_r,· the pt\1~r.1m jump s.
Byte 2nd and byte 3rd of the_ins!ru ction give the addr:ess of
for nex t ms tructt on tn hL' execu ted . The
The addre ss of the label is the addre ss of the mem ory locati on
(labe l) unco nditil ln,1lly.
program jumps to the instru ction specified by the addre ss
 MIC A~ . ;
FUNDAMENTALS OF MICROPROCESSORS ANO
~,
4.12
p insh-ucti "
bel) After the execution of the conditional jum
(label) if the specified condition . Ori ~
st
program jumps to the m ructl~n 10
The program proceeds further . e ::e s
:r•
Condltlonal Jum~ addr ~la · 'f d by the address
te al sequence if the specified condition is not
ful~~l~J~
ified label, the execution of a conditional jum ·If~
~~
:e only 2 machine cycles; 7 states are required~Or~
condition is true and prografm iumd_1~s .ts no '
3 machine cycles: 10 states. I con on
execution of the instruction. .
is zero) . ..
(t) JZ addr (label). Oump if the resultStat Add ress mg. imm edia te.
• p t'f z -- 1• es·· 7/10· Flag s: non e.
[PC] ~ address (Iabel), 1um . .
.
Machine cycles: 2/3. 15 zero (1_.e. ~
by the ad d~ (J~bel) if ~e r~u lt
The program jumps to the instruction specified er con.,idero,
zero status z = 1). Here the result after the
execution of the preceding instruction ts und
tion .
zero)
(it) JNZ addr (label). Gump if the result is not
Flags: none. Addressing : immediate.
[PC)~ address (label), jump if Z = 0. States: 7/10.
Machine cycles: 2/3.
by the address (label) if the result is non-zero (i.t
The program jumps to the instruction specified
the zero status Z = 0).
(iit) JC addr (label). Oump if there is a carry)
7/10. Flags: none. Addressing: immediate.
[PC] ~ address (label), jump if CS= 1. States:
Machine cycles: 2/3.
by the address (label) if there is a cany (i.e. the
The program jumps to the instruction specified
ution of the preceding instruction is under cm
carry stat us:~ = 1). Here the carry after the exec
sideration.
)
(iv) JNC addr (label). Oump if there is no carry
7/10. Flags: none. Addressing : immediate.
[PC] ~ address (label), jump if CS= 0. States:
Machine cycles: 2/3.
the address (label) if there is no carry (i.e. the
The program jumps to the instruction specified by
carry states CS = 0 ). .
(v) JP addr (label). Oump if the result is plus
)
Flags: none. Addressing: immediate.
[PC )~ address (label), jump if S = 0. States: 7/10.
Machine cycles: 2/3.
The program jumps to the instruction specified
by the address (label) if the result is plus.
(v,) JM addr (llbll). Ownp if the fflJUlt is minu
s)
10. Flags: none. Addressing: immediate.
[PC) ~ address (label), jump if S = 1. States: 7I
Machine cycles: 2/3.
. th . by the address (label).
If the ult'18 nunu
. res s e program Jumps to the instruction specified
(vu) JPE addr (label). Oump if even parity)
fPCJ ~ address (labe. l)' jumn if · h /10. Flags: none,
Addressin. .. ~-T even parity: t e parity status P = 1, States: 7
g. unmediate. Machine cycles: 2/ 3. .. tJie
h . .
Uthe result contains even number Of 1s, t e piogram Jumps to the instruction speofied by
address (label).
(vii~ JPOaddr,(llbel). Oumpifodd parit
y)
fPCJ f- address (label), jump if.odd pan.ty ; the parity status p = 0, States: 7/10, flags : none,
Addres . . immedia'te, Machine cycles: 2/3.
smg.
 SET Of 1NTEL 8085
~srflucriON 4. 13
1
contains odd number of 1s the pro ·
If tt,e resu11 ' gram Jumps to the instruction specified by the
(111bel). ..
Jdd~LL ,ctdr (label). (Unco nd111011 al CALL: call the subroutine identified by the address)
C,..
[SP! - 1 r
I [PCH], Save the address of the ne xt ms
· t •
ruction of the program in the stack.
I SP] - 2) <- [PCL],
[[ [SP) r [SP) - 2
rrcJ r addr (label)
.;tates: 18. Ftag_s: n? ne, Addressing: imme~iate/ reg. indirect. Machine cycles: 5.
CALL instntCtion 1~ used t~ call a subro~tine. Before the control is transferred to the subroutine,
ress of the next instruction of the mam program is saved in the stack. The content of the stack
tilt' ,1lid ed b twO tO . d . h . .
.1ter is decrement Y m icate t e new stacktop. Then the program 1umps to subroutine
r 1
u_
.1ar11ng 111
address specified by the label.
. cor,dttlonal CALL addr (label)
[[SP] - 1] f- [PCH], [[SP] - 2] f- [PCL],
[PC] f- addr (label), [SP] f- [SP] - 2.
States: 9/ 18. Flags: none. Addressing: immediate/reg. indirect. Machine cycles: 2/5. If the con-
dition is true and program calls the specified subroutine, the execution of a conditional call instruc-
tion takes 5 machine cycles; 18 states. If condition is not true, only 2 machine cycles; 9 states are
required for the execution of the instruction.
(1) CC addr (label) Call subroutine if carry status CS = 1.
(i1) CNC addr (label) Call subroutine if carry status CS = 0.
(iii) CZ addr (label) Call subroutine if the result is zero; the zero status Z = 1.
(iv) CNZ addr (label) Call subroutine if the result is not zero; the zero status Z = 0.
(v) CP addr (label) Call subroutine if the result is plus; the sign status S = 0.
(v1) CM addr (label) Call subroutine if the result is minus, the sign status S = 1.
(vii) CPE addr (label) Call subroutine if even parity; the parity status P = 1.
(viii) CPO addr (label) Call subroutine if odd parity; the parity status P = 0.
RET. (Return from subroutine)
IPCL] ~ [[SP]],
[PCHJ+- [[SP) + 11
[SP) ~ [SP] + 2.
Slates: 10. Flags: none. Addressing: reg. indirect. Machine cycles: 3.
RET instruction is used at the end of a subroutine. Before the execution of a subroutine the ad-
dress of the next instruction of the main program is saved in the stack. The execution of RET instmc-
h~ b .
. nngs back the saved address from the stack to the program counter. The content of the stack
pof II\ter is incremented by 2 to indicate the new stack top. Then the p rogram jumps to the instruction
0 then.,.:_ b .
-ou.u, Program next to CALL instruction which called the su routme.
Cond1t1ona1Return
~~L] ~ [[SP]], [PCH] f- [[SP] + 1),
Sta .~ [SP] + 2. . . .. .
tht~s.
ilJ\d 6/12. Flags: n one. Ad dressing: reg. indirect. Machine cycl~~: 1 / 3. If the ~onditi~n 1s true
3rna .Program returns from the subroutine, the execution of a conditional return mstructi_on takes
chine cycles, 12 states. If con dition is not true only one machine cycle, 6 states are reqwred.
/
4.1 4
FUN DA ME NTA LS OF MIC RO
PR OC ES SO RS AND MICA

(i) RC Re tur n fro m sub rou tin e if car

ry sta tus CS = 1.
~~~
(ii) RN C Re tur n fro m sub rou tin e if car
ry sta tus CS = 0.
(iii ) RZ Re tur n fro m sub rou tin e if the
res ult is zer o; the zer o sta tus
(iv ) RN Z Re tur n fro m sub rou tin e if the Z = 1.
res ult is no t zer o; the zer o sta
(v) RP Re tur n fro m s~b rou tin e if the tus z = o.
res ult is plu s; the sig n sta tus
(vr ) RM Re tur n fro m sub rou tin e if the S = 0.
res ult is mi nu s, the sig n sta tus
(vi i) RP E Re tur n fro m sub rou tin e if ev S = 1.
en par ity , the pa rit y sta tus P
(vi ii) RP O Re tur n fro m sub rou tin e if od = 1.
d par ity , the pa rit y sta tus P =
RS T n (Re sta rt). 0.
[[SP} - 1} +- IPC H} , [[SP} - I
2} <- IPCL},
ISP} +- ISP} - 2, IPC} +-8 tim
es n.
Sta tes : 12. Fla gs: no ne, Ad dre
ssi ng: reg . ind ire ct. Ma chi ne cyc
Re sta rt is a on e-w ord CA LL ins les : 3 .
tru cti on. Th e con ten t of the pro
Th e pro gra m jum ps to the ins gra m cou nte r is sav ed in the stack
tru cti on sta rtin g at res tar t loc ati .
is 8 tim es n. Th e res tar t ins tru on. Th e add res s of the res tar t
cti on an d loc ati ons are as fol low location
s:
Ins tru ctio n
Opcode
RS T0 Restart Locations
C7
RS Tl 000 0
CF
RS T2 000 8
D7
RS T3 001 0
OF
RS T4 001 8
E7
RS TS 002 0
EF
RS T6 002 8
F7
RS T7 003 0
FF
PC HL Ou mp to add res s spe cif ied 003 8
by H- L pai r)
[PC ]+- (H- L], [PC H] +-( H] , (PC
L] <- [L]
Sta tes : 6. Flags: no ne. Ad dre ssi
ng: reg iste r. Ma chi ne cyc le : 1.
Th e con ten ts of H- L pai r are
tra nsf err ed to pro gra m cou nte
mo ve d to hig h ord er 8 bit s of reg r. Th e con ten ts of reg iste r H are
iste r PC . Th e con ten ts of reg iste
of reg iste r PC . r La re tra nsf err ed to low ord er
8 bits
4.8 .5 Sta ck , 1/0 an d Ma ch
ine Co ntr ol Gr ou p
IN po rt- acl drN a. (In pu t to acc
um ula tor fro m I/0 por t)
[A ]+- (Po rt]. Sta tes : 10. Fla gs:
none . Ad dre ssi ng: dir ect . Ma chi
Th e da ta ava ila ble on the po ne cyc les: 3. of
rt is mo ved to the acc um ula tor
the po rt is spe cif ied . Th e 2n . Af ter ins tru cti on IN, the ad =
d by te of the ins tru cti on con tai
ns the add res s of the por t. Th e
ol
a po rt is an 8-b it add res s. Fo r ad of a
exa mp le, lN 01. Th e add res s of
mi cro pro ces sor kit is 01. the po rt B of an 1/0 por t 82.55·1
OU T po rt- ad d,. ... (O utp ut
&om acc um ula tor to 1/ 0 por t)
[Po rt] <- [A] . Sta tes: 10. Fla gs:
none. Ad dre ssi ng: dir ect . Ma chi
Th e con ten t of the acc um ula ne cyc les : 3. Ult? ()I.ff
ins tru cti on , the po rt add res s tor is mo ved to the po rt spe cif ied by its ad~res.s- ~~ ot
is spe cif ied . Th e 2n d by te of tli f
the ins tru cti on con tam s the a
 c; JiUN ~ I I ()I IN 11 I llllll!,
..
,,,,,: 11 HJ 4.16
,
1 111
,11-. ( )l JT ()ll. Tlw ,1dd1\•1-:, 11 1 th
I 1·1'r i''• • 1 l'' ).' ,r,. 1
,. p11rt /\ 111 "" 1/() 1••·1 fl
( 'I 111 I( r111) re I\ f 'H
1
1'1 ' • I.... 1111.
~ii
~•'' pLJSH rp. (l'11~h th,· ,·,11111•111 ,11 n·gh,lt·r p,,ir 111 Hlm·k)
·1•1 11 ( I I/ I 1,
ii~
~ ,I .' I < I rl L
I. I 1 I ·1•1 ,
~r1 < ~ ~·
I,~1.,11•:..: I -1· Fl ''f"'
,· ·
1\11111'. /\dd1\·:,-...i11r : l\'fl',l1·r(• 1111111
. . • . •· ·•
· · )/ 11,
'
j I
')',. '" ln·1t(d1•1,ll11,1lln11), M,1chirn• cyc h·'l· 1 .
. . .1,ntt•nl 111 !hi' rq:is h'r 1'• 11 " "I' is pw,hvd i11111 !ht• •st,• I k.
I 111 '
pLJSH pSW. (l'l 1~11 l'm,·,·ss,,r s l,1l11s w 11 nl)
IISI' I 11, I /~1 , .
w~1·1 21I !~\,\/ (I l'll~~r.1111 St.,tus W,,nl)
' I'] .,
1s1•1 I I~ • -• , ,

s1.,11~: I :!, 1-1.,~s: ,w,w. /\dd n •ssm~: rl'gtsll'r(soun·L•)/ rl'g.i11d i n•, ·t( dl'sl i11,1 tion ), M<1ch i m· cycl1·<1: 1.
The _.,111ll'lll of tlw ,•1l'l'l1tnul.,tor is puslwd into tlw stnck. The conh•nt.s of s t,1tus flt1>4s Mt· .:ibo
,11 ~1wd i11ll1 tlw st.Kl-.. l lw (llnh.•nl 11 f lh,• rq~iskr SP is dl'<.:n•m1·nh•d by 2 lo ind it:c1tl' ne w s t,1ektop.
1
POP rp. (l\1p the n 1nll'nl of n•gish•r pair, which was snvcd, from the s tack)
1ri] <- IISPI]
[rll] <- [[SI'] + I]
1sr1 <- 1sr1 + 2.
Stah-s: 10. Fl.1gs: none. /\ddrl'ssin~: rcgister(dcstination)/rcg.indirec t (sourcc),Machine cycles: 3.
The content of the register p,1ir, which wns saved ci'lrlicr b movl'd from the s tack to the rig is ter
pair.
POP PSW. (Pop Processor St.1tus Word)
rsw <- !ISP]]
IA] <- [ISP] + 1]
ISP] <- ISP] + 2.
States: 10. Flags: all. Addressing: rl'g. indirect. Machine cycles: 3.
Thr processor status word whi ch w.is s.1vcd cn rlicr during the exec ution of the program is
mo,·ed from the stack to PSW. The content of the accumulator which wns nlso saved is m oved from
th e stack to the accumulator.
HLT (Halt)
States: 5. Flags: n on e . Machine cycle : 1.
The execution of the instructio n HLT stops the microprocessor. The rq.;istt•rs and s tatus flags
rl•rnain unaffected.
XTHL. (Exchange stack-top with H-L)
[LJ H [(SP)]
[HJ H l[SP]] + 1).
States: 16. Flags: none. Addressin g: regis te r indirect. Machine cydl's: _c; _
registe . te r 1 a re exc h an ged with the byte of the s t,icl-.-top. The contents of the H
The contents o f tl1e regis J

r exchanged with the byte be low the s tack-top.

SIPHL (Move the conten ts of H-L p a ir to stack pointer)
1-1-LJ ~ [SP].
st
ates: 6 - Flags: none. Addressing: regis tPr. M achine cycle: 1 ·
4.1& FUNDAMENTALS OF
MICROPROCESSOR
S AND MICROC~
The contents of H-L pa
ir are transferred to th e SP
P\nt~
regjster.
El. (Enable interrupts)
States: 4. Flags: none , M
achine cycle: 1.
When this i.nstruchon is
executed the interrupts
are enabled.
DI (Disable lnterrups)
States: 4. Flags : none , M
achine cycle: 1
When this instruction is
executed interrups are
disabled .
SIM (Set lnterupt Mas
ks)
States: 4. Flags: none , M
achi
When this instruction is ne cycle: 1. .
executed bits 0-5 of the .
tart interrupt masks. Bi accumulator are used
ts 6-7 of the accumulato m prograrrurung the Its-
details in Chapter 7, Se r are used in making se
ction 7.5: Interrupts of In rial ou tp ut on SOD lin
tel 8085. e. ~
RIii (Read Interrupt Mas
k)
States: 4. Flags: none. M
achine cycle: 1.
W he n this instruction
is executed, the accum
interrupt masks and th ulator is loaded with pe
e contents of SID. See de nding interrupts, the res
tails in Chapter 7, Secti tart
N!)P (No Operation) on 7.5: Interrupts of In
te l~-
States: 4. Flags: none. M
achine Cycle: 1.
No operation is perform
ed when this instructio
unaffected. n is executed. The regi
sters an d flags remain

PROBLEMS
1. Classify 8085 instruc
tions in various groups
2. What are the vario . Give examples of instr
us types of data formats uctions for each group.
type of data format. for Intel 8085 instructio
ns? Give examples for
3. Discuss various ty each
pes of addressing modes
4. Explain w ha t op of Intel 8085 with suita
eration will take place w ble examples.
LXI rp, data; LOA addr hen the following instr
, LHLD addr, STA addr uc tions are executed:
5. Explain what oper , and SHLD addr.
ation is performed whe
DAD rp, DAA, CMP r, n the following instruc
CMP M, CMA, RAL, RA tions are executed:
R, PUSH rp and POP rp
.