Interrupt

•It is a process where an external device can get the attention of the microprocess
•The process starts from the I/O device.
•The process is asynchronous.
Classification of Interrupts
Interrupts can be classified into two types based on masking:
Maskable Interrupts (Can be delayed or Rejected)
Non-Maskable Interrupts (Can not be delayed or Rejected)

Interrupts can also be classified into two based on vector address:

Vectored (the address of the service routine is hard-wired)
Non-vectored (the address of the service routine needs to
be supplied externally by the device)
An interrupt is considered to be an emergency signal that may be
serviced.
The Microprocessor may respond to it as soon as possible.

What happens when MP is interrupted ?

When the Microprocessor receives an interrupt signal, it suspends the
currently executing program and jumps to an Interrupt Service Routine
(ISR) to respond to the incoming interrupt.

Each interrupt will most probably have its own ISR.

 Responding to an interrupt

This may be immediate or delayed depending on whether the interrupt is

maskable or non-maskable and whether interrupts are being masked or
not.

• There are two ways of redirecting the execution to the ISR depending on
whether the interrupt is vectored or non-vectored.

Vectored: The address of the subroutine is already known to the

Microprocessor

Non Vectored: The device will have to supply the address of the
subroutine to the Microprocessor
 8085 Interrupts

• When a device interrupts, it actually wants the MPU to give a service

which is equivalent to asking the MP to call a subroutine. This subroutine
is called ISR (Interrupt Service Routine)

• The ‘EI’ instruction is a one byte instruction and is used to Enable the
non-maskable interrupts.

• The ‘DI’ instruction is a one byte instruction and is used to Disable the
non-maskable interrupts.

• The 8085 has a single Non-Maskable interrupt

• The non-maskable interrupt is not affected by the value of the Interrupt

Enable flip flop.
The 8085 has 5 interrupt inputs.
The INTR input.
The INTR input is the only non-vectored interrupt.
INTR is maskable using the EI/DI instruction pair.

RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
RST 5.5, RST 6.5, and RST 7.5 are all maskable.

TRAP is the only non-maskable interrupt in the 8085

TRAP is also automatically vectored

Interrupt name Maskable Vectored

INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes
 Interrupt vector and vector Table

• An interrupt vector is a pointer to where the ISR is stored in

memory.

• All interrupts (vectored or otherwise) are mapped onto a memory

area called the Interrupt Vector Table (IVT).

• The IVT is usually located in memory page 00 (0000H - 00FFH).

• The purpose of the IVT is to hold the vectors that redirect the
microprocessor to the right place when an interrupt arrives.
 Interrupts in 8085 microprocessor

The MPU may receive a signal from any peripheral(s) requesting its
services - this signal is named interrupt signal

Steps carried out by MPU on receiving the interrupt signal

it stops its current execution and

program control is transferred to a sub-routine by generating CALL
signal and after executing sub-routine by generating RET signal again
program control is transferred to main program from where it had
stopped.
When microprocessor receives interrupt signals, it sends an
acknowledgement (INTA) to the peripheral which is requesting for its
service.
Interrupt servicing
Interrupts can be classified into various categories based on different parameters:

Hardware and Software Interrupts :

• When microprocessors receive interrupt signals through pins (hardware) of

microprocessor, they are known as Hardware Interrupts.

• There are 5 hardware Interrupts in 8085.

• They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP

• Software Interrupts are those which are inserted in between the program thru
mnemonics of microprocessor.

• There are 8 software interrupts in 8085.

• They are – RST 0 to RST 7

Vectored and Non-Vectored Interrupt :

• Vectored Interrupts are those which have fixed vector address (starting address of sub-
routine) on interrupt and after executing these, program control is transferred to the
main program.

• Vector Addresses are calculated by the formula 8 * TYPE

• Non-Vectored Interrupts are those

in which vectored dress is not
predefined.
• The interrupting device gives the
address of sub-routine for these
interrupts.
• INTR is the only non-vectored
interrupt in 8085 microprocessor.
For Software interrupts vector addresses are given by:
Maskable and Non-Maskable Interrupts :

Maskable Interrupts are those which can be disabled or ignored by the

microprocessor.

These interrupts are either edge-triggered or level-triggered,

so they can be disabled.

INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085

Non-Maskable Interrupts are those which cannot be disabled or

ignored

TRAP is a non-maskable interrupt.

It consists of both level as well as edge triggering and is used in critical

power failure conditions.
Priority of Interrupts:

When microprocessor receives multiple interrupt requests

simultaneously, it will execute the interrupt service request (ISR
according to the priority of the interrupts.
 Triggering levels
RST 7.5 is positive edge sensitive.
When a positive edge appears on the RST7.5 line, a logic 1 is stored in
the flip-flop as a “pending” interrupt.
Since the value has been stored in the flip flop, the line does not have to
be high when the microprocessor checks for the interrupt to be
recognised.
The line must go to zero and back to one before a new interrupt is
recognised.

RST 6.5 and RST 5.5 are level sensitive.

The interrupting signal must remain present until the microprocessor
checks for interrupts.
Interrupt Service Routine (ISR)
A small program or a routine that when executed, services the
corresponding interrupting source is called an ISR.

TRAP
It is a non-maskable interrupt, having the highest priority among all
interrupts. By default, it is enabled until it gets acknowledged. In case of
failure, it executes as ISR and sends the data to backup memory. This
interrupt transfers the control to the location 0024H.

RST7.5
It is a maskable interrupt, having the second highest priority among all
interrupts. When this interrupt is executed, the processor saves the
content of the PC register into the stack and branches to 003CH address.
RST 6.5
It is a maskable interrupt, having the third highest priority among all
interrupts. When this interrupt is executed, the processor saves the content
of the PC register into the stack and branches to 0034H address.

RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor
saves the content of the PC register into the stack and branches to 002CH
address.

INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It
can be disabled by resetting the microprocessor.
 Instruction for Interrupts

EI – This interrupt enable flip-flop once set, all interrupts following the EI instruction
are enabled.
No flags are affected.
After a system reset, the interrupt enable flip-flop is reset, thus disabling
the interrupts.
This instruction is necessary to enable the interrupts again
(except TRAP).

DI– This instruction is used to reset the value of enable flip-flop

hence disabling all the interrupts.
No flags are affected by this instruction.
 Restart sequence

The restart sequence is made up of three machine cycles

In the 1st machine cycle:
The microprocessor sends the INTA signal.
While INTA is active the microprocessor reads the data lines expecting to
receive, from the interrupting device, the opcode for the specific RST
instruction.

In the 2nd and 3rd machine cycles:

The 16-bit address of the next instruction is saved on the stack.
Then the microprocessor jumps to the address associated with the
specified RST instruction.
Example: Let's assume that a device interrupts the MPU using the
RST 7.5 interrupt line.

Because the RST 7.5 interrupt is vectored, MPU knows , in which

memory location it has to go using a call instruction to get the ISR
address.

RST7.5 is knows as CALL 003CH to MPU.

MPU goes to 003C location and will get a JMP instruction to the actual
ISR address.

The MPU will then, jump to the ISR location

 8085 Non- vectored interrupt process

1.The interrupt process should be enabled using the EI instruction.

2.The 8085 checks for an interrupt during the execution of every instruction.

3.If INTR is high, MPU completes current instruction, disables the interrupt
and sends INTA (Interrupt acknowledge) signal to the device that
interrupted

4.INTA allows the I/O device to send a RST instruction through data bus.

5.Upon receiving the INTA signal, MPU saves the memory location of the
next instruction on the stack and the program is transferred to ‘call’ location
(ISR Call) specified by the RST instruction
6.MPU Performs the ISR.

7.ISR must include the ‘EI’ instruction to enable the further interrupt within
the program.

8.RET instruction at the end of the ISR allows the MPU to retrieve the return
address from the stack and the program is transferred back to where the
program was interrupted.

The 8085 recognize 8 RESTART instructions: RST0 - RST7.Each of these

would send the execution to a predetermined hard-wired memory location:
Hardware generation of a RST code
How does the external device produce the opcode for the appropriate
RST instruction?
The opcode is simply a collection of bits.
So, the device needs to set the bits of the data bus to the appropriate
value in response to an INTA signal.
During the interrupt acknowledge machine cycle, (the 1st
machine cycle of the RST operation):
• The Microprocessor activates the INTA signal.
• This signal will enable the Tri-state buffers, which will place
the value EFH on the data bus.
• Thus sending the Microprocessor the RST 5 instruction.
• The RST 5 instruction is exactly equivalent to CALL 0028H
The software RST interrupt sequence -example
RST 4 – 0020H
Mnemonics, Opcode
In Binary Bytes Target Address (n*8)
Operand (in HEX)

RST 0 C7 11 0 0 0 111 1 0000H

RST 1 CF 11 0 0 1111 1 0008H

RST 2 D7 11 0 1 0 111 1 0010H

RST 3 DF 11 0 1 1111 1 0018H

RST 4 E7 111 0 0 111 1 0020H

RST 5 EF 111 0 1111 1 0028H

RST 6 F7 1111 0 111 1 0030H

RST 7 FF 1111 1111 1

0038H
Set Interrupt Mask (SIM) – It is used to implement the hardware
interrupts (RST 7.5, RST 6.5, RST 5.5) by setting various bits to masks
or generate output data via the Serial Output Data (SOD) line.

First the required value is loaded in accumulator then SIM will take the bit
pattern from it.
Read Interrupt Mask (RIM) – This instruction is used to read the status of the
hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A register a
byte which defines the condition of the mask bits for the interrupts.

It also reads the condition of SID (Serial Input Data) bit on the microprocessor.
Write a main program to count continuously in binary with 1 second delay b
each count
Write a ISR at XX70H to flash FFH five times when the program is interrupte
some appropriate delay between each flash

MAIN PROGRAM
Memory
Label Mnemonics
address
XX00 LXI SP, XX99H
03 EI
04 MVI A, 00H
06 NXTCNT : OUT Port 1
08 MVI C, 01H
0A CALL DELAY
0D INR A
0E JMP NXTXNT
Assume that interrupt (RST 5) occurs at XX06H

The RET address XX08 is loaded at XX98 and XX97 H (stack)

RST 5 is at - 0020H
At 0020H JMP XX70H

Memory address Label Mnemonics

XX70 SERV : PUSH B

XX71 PUSH PSW

XX72 MVI B, 0AH
XX74 MVI A,00H
XX76 OUT Port 1
XX78 MVI C, 01H
XX7A CALL DELAY
FLASH :
XX7D CMA
XX7E DCR B
XX7F JNZ FLASH
XX82 POP PSW

XX83 POP B
XX84 EI
XX85 RET
Multiple interrupts and Priorities
There are 8 different RST Instructions .
•How do MPU allow multiple devices to interrupt using the INTR line?
•The microprocessor can only respond to one signal on INTR at a time.
•Therefore, we must allow the signal from only one of the devices to reach the
microprocessor.
We must assign some priority to the different devices and allow their signals to
reach the microprocessor according to the priority.
The solution is to use a circuit called the priority encoder as opcodes for the
different RST instructions follow a set pattern.
When microprocessor receives multiple interrupt requests simultaneously, it
will execute the interrupt service request (ISR) according to the priority of the
interrupt.
Assuming the MP is completing an RST 7.5 interrupt request, check to see if RST 6.5
is pending. If it is pending, enable RST 6.5 without affecting any other interrupts
otherwise, return to the main program

Label Mnemonics

RIM

MOV B,A

ANI 20H // CHECK IF 6.5 PENDING

JNZ NEXT

EI
RET
NEXT :
MOV A,B

ANI 0DH

ORI 08H

SIM
JMP SERV// JMP To ISR of 6.5
 Issues in Implementing INTR Interrupts
How long must INTR remain high?

The microprocessor checks the INTR line one clock cycle before the
last T-state of each instruction.
The INTR must remain active long enough to allow for the longest
instruction.
The longest instruction for the 8085 is the conditional CALL instruction
which requires 18 T-states.

• Therefore, the INTR must remain active for 17.5 T- states.

• If f= 3MHZ then T=1/f and so, INTR must remain active for
[ (1/3MHZ) * 17.5 ≈ 5.8 micro seconds].
 Issues in Implementing INTR Interrupts

How long can the INTR remain high?

–

The INTR line must be deactivated before the EI is

executed.
Otherwise, the microprocessor will be interrupted again.
Once the microprocessor starts to respond to an INTR
interrupt, INTA becomes active (=0).
–

Therefore, INTR should be turned off as soon as the

INTA signal is received.
 Issues in Implementing INTR Interrupts

Can the microprocessor be interrupted again

before the completion of the ISR?

As soon as the 1st interrupt arrives, all maskable

interrupts are disabled.

They will only be enabled after the execution of the EI

instruction.

Therefore, the answer is: “only if we allow it to”.

If the EI instruction is placed early in the ISR, other

interrupt may occur before the ISR is done.
The interrupts in 8085 is classified into the following

Data transfer scheme: Executing of 8085 program where the

communication process is carried out systematically and is not done
directly with the Input Output device.

The data transfer can be either in two forms namely parallel or serial
respectively.

Basic or simple data transfer scheme: The simplest data transfer

scheme is the basic or simple data transfer.

This method is beneficial to us when we have accurate know-ledge of

the Input Output device timing characteristics.
Status check data transfer: Status check data transfer process is
a complex process than simple data transfer.
This method is used when there is a lack of accurate knowledge of
the Input Output device consisting of their timing characteristics.
Status information is received by the processor regarding the
readiness of the Input Output device for performing the data
transfer.

Interrupt driven data transfer: This method is used when there is

a lack of accurate knowledge of the timing characteristics of the
Input Output device which takes maximum time for the device to be
ready for use.
Suppose we resort for the checking of data transfer; the processor
here wastes a huge time in the loop for the device to get ready up to
the mark.