UNIT-3 -DLF

Sequential Logic Circuits

Sequential Logic Circuits use flip-flops as memory elements and in which their output is
dependent on the input state

Unlike Combinational Logic circuits that change state depending upon the actual signals being
applied to their inputs at that time, Sequential Logic circuits have some form of inherent
―Memory‖ built in.

A flip flop is an electronic circuit with two stable states that can be used to store binary data. The
stored data can be changed by applying varying inputs. Flip-flops and latches are fundamental
building blocks of digital electronics systems used in computers, communications, and many
other types of systems. Flip-flops and latches are used as data storage elements

Various types of flip flops are

1. SR Flip Flop [Set-Reset Flip Flop] 2. D Flip Flop [Data Flip Flop]

3. J.K Flip flop 4. T- Flip Flop [Toggle Flip Flop]

5. J.K Master Slave flip flopFlip flop

1. SR Flip flop

It consists of a basic flip-flop circuit and two additional NAND gates. When the pulse input goes
to 1, information from the S or R input is allowed to reach the output

Case (1): No Change:

S=0 R=0 Q = No change

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case (2) RESET :

To change to the reset state, the inputs must be

S = 0, R = 1, and CP = 1.

Q=0 Q'=1

case (3) SET :

The set state is reached with

S = 1, R = 0, and CP = 1 and the output of the flip-flop at Q to go to 1.

Q=1 Q'=0

Case (4) - race around condition

S=1 R=1 CP=1

When the S and R inputs of an SR flipflop is at logical 1 and then the input is changed to
any other condition, then the output becomes unpredictable and this is called the race
around condition.

CHARECTERISTIC TABLE

Clock S R Qt+1

0 — — Qt

1 0 0 Q NO CHANGE

1 0 1 0 RESET

1 1 0 1 SET

1 1 1 Ambiguity state -RACE CONDITION

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 LOGIC CIRCUIT

Clocked S - R Latch

2. D-FLIP FLOP (DATA FLIP FLOP)

D flip flop is also called as DATA flip flop as it is stores a bit of data. i.e. the input data applied at the
input D, it changes the output state according to input and remains in the same state until the input
changes.

One way to eliminate the undesirable condition of the indeterminate state in the RS flipflop is to ensure
that inputs S and R are never equal to 1 at the same time. This is done in the D flip-flop.

The D flip-flop has only two inputs: D and CP. The D input goes directly to the S input and its
complement is applied to the R input.

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The D flip-flop receives the designation from its ability to hold data into its internal storage. This type of
flip-flop is sometimes called a gated D-latch.

CASE 1: D=1 CLOCK=1 Q=1 SET

CASE 2: D=0 CLOCK=1 Q=0 RESET

3. JK FLIP FLOP

A JK flip-flop is a refinement of the RS flip-flop in that the indeterminate state ( RACE CONDITION) of
the RS type is defined in the JK type.

Inputs J and K behave like inputs Sand R to set and clear the flip-flop, respectively.

The input J is for set

The input K is for reset.

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 1. When J & K are low (i.e. J=0 K=0) , Q(T+1)=Q(T) NO CHANGE. This condition is called
latched condition as the flip flop retains its last value.
2. When J=0 and K=1 Q(T+1) =0 RESET STATE
3. When J =1 & K =0, Q(T+1) =1. SET STATE

4. When J =1 & K =1 Q(T+1)=𝑸(𝑻). COMPLEMENT (1-->0 or 0--> 1) the flip-flop switches to

its complement state, that is, if Q = 1, it switches to Q = 0, and vice versa.

Racing condition

J=K=1 CLOCK=1

In JK flip flop as long as clock is high for the input conditions J&K equals to the output changes or
complements its output from 1–>0 and 0–>1. This is called toggling output or uncontrolled changing or
racing condition.

4.T Flip Flop (Toggle flip flop)

The T flip-flop is a single-input version of the JK flip-flop. As shown in Fig the T flip-flop is
obtained from the JK flip-flop when both inputs are tied together. The name T comes from the ability of
the flip-flop to "toggle," or complement, its state. Regardless of the present state, the flip-flop
complements its output when the clock pulse occurs while input T is 1.

When T = 0, Q(t + 1) = Q, that is, the next state is the same as the present state and no change
occurs.
When T = 1, then Q (t + 1) = Q', and the state of the flip-flop is complemented.

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 5. Master-Slave JK Flip-flop

The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops connected
together in a series configuration.

One flip-flop acts as the ―Master‖ circuit, which triggers on the leading edge of the clock pulse

The other acts as the ―Slave‖ circuit, which triggers on the falling edge of the clock pulse.

This results in the two sections, the master section and the slave section being enabled during opposite
half-cycles of the clock signal.

The Master-Slave JK Flip-flop

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse. The outputs from Q and Q’ from the ―Slave‖
flip-flop are fed back to the inputs of the ―Master‖ with the outputs of the ―Master‖ flip flop being
connected to the two inputs of the ―Slave‖ flip flop.

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This feedback configuration from the slave‘s output to the master‘s input gives the characteristic toggle of
the JK flip flop as shown below.

The Master-Slave JK Flip Flop

The input signals J and K are connected to the gated ―master‖ SR flip flop which ―locks‖ the input
condition while the clock (Clk) input is ―HIGH‖ at logic level ―1‖.

As the clock input of the ―slave‖ flip flop is the inverse (complement) of the ―master‖ clock input, the
―slave‖ SR flip flop does not toggle.

The outputs from the ―master‖ flip flop are only ―seen‖ by the gated ―slave‖ flip flop when the clock
input goes ―LOW‖ to logic level ―0‖.

When the clock is ―LOW‖, the outputs from the ―master‖ flip flop are latched and any additional changes
to its inputs are ignored. The gated ―slave‖ flip flop now responds to the state of its inputs passed over by
the ―master‖ section.

Then on the ―Low-to-High‖ transition of the clock pulse the inputs of the ―master‖ flip flop are fed
through to the gated inputs of the ―slave‖ flip flop and on the ―High-to-Low‖ transition the same inputs
are reflected on the output of the ―slave‖ making this type of flip flop edge or pulse-triggered.

Then, the circuit accepts input data when the clock signal is ―HIGH‖, and passes the data to the output on
the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a ―Synchronous‖
device as it only passes data with the timing of the clock signal.

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Flip Flop – Triggering Methods

The basic pulse triggering methods are

HIGH Level Triggering

LOW Level Triggering

POSITIVE edge triggering

NEGATIVE edge triggering

The output of a flip flop can be changed by bring a small change in the input signal. This small change
can be brought with the help of a clock pulse or commonly known as a trigger pulse.

When such a trigger pulse is applied to the input, the output changes and thus the flip flop is said to be
triggered. nd these sequential circuits require trigger pulses.

The number of trigger pulses that is applied to the input of the circuit determines the number in a counter.
A single pulse makes the bit move one position, when it is applied onto a register that stores multi-bit
data.

There are mainly four types of pulse-triggering methods. They differ in the manner in which the
electronic circuits respond to the pulse. They are

1. High Level Triggering

When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is used. It is
mainly identified from the straight lead from the clock input. Take a look at the symbolic representation
shown below.

2. Low Level Triggering

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When a flip flop is required to respond at its LOW state, a LOW level triggering method is used.. It is
mainly identified from the clock input lead along with a low state indicator bubble. Take a look at the
symbolic representation shown below.

Low Level Triggering

3. Positive Edge Triggering

When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE edge triggering
method is used. It is mainly identified from the clock input lead along with a triangle. Take a look at the
symbolic representation shown below.

4. Negative Edge Triggering

When a flip flop is required to respond during the HIGH to LOW transition state, a NEGATIVE edge
triggering method is used.. It is mainly identified from the clock input lead along with a low-state
indicator and a triangle. Take a look at the symbolic representation shown below.

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 UNIT 3 PART A QUESTIONS

1. What are the classification of sequential circuits?

The sequential circuits are classified on the basis of timing of their signals into twotypes. They are,
 Synchronous sequential circuit.
 Asynchronous sequential circuit.
2. Define Flip flop.
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1or 0 until directed by
an input signal to change its state.
3. What are the different types of flip-flop?
There are various types of flip flops. Some of them are mentioned below they are,
 RS flip-flop
 SR flip-flop
 D flip-flop
 JK flip-flop
 T flip-flop
4. What is the operation of RS flip-flop?
 When R input is low and S input is high the Q output of flip-flop is set.
 When R input is high and S input is low the Q output of flip-flop is reset.
 When both the inputs R and S are low the output does not change
 When both the inputs R and S are high the output is unpredictable.
5. What is the operation of SR flip-flop?
 When R input is low and S input is high the Q output of flip-flop is set.
 When R input is high and S input is low the Q output of flip-flop is reset.
 When both the inputs R and S are low the output does not change.
 When both the inputs R and S are high the output is unpredictable.
6. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if
D=0, the output is reset.
7. What is the operation of JK flip-flop?
 When K input is low and J input is high the Q output of flip-flop is set.
 When K input is high and J input is low the Q output of flip-flop is reset.
 When both the inputs K and J are low the output does not change
 When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the
output toggle on the next positive clock edge.

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8. What is the operation of T flip-flop?
T flip-flop is also known as Toggle flip-flop.
 When T=0 there is no change in the output.
 When T=1 the output switch to the complement state (ie) the output toggles.
9. Define race around condition.
In JK flip-flop output is fed back to the input. Therefore change in the output change in the input. Due to
this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This
condition is called ‗race around condition‘.
10. What is edge-triggered flip-flop?
The problem of race around condition can solved by edge triggering flip flop. The term edge triggering
means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it
is sensitive to its inputs only at this transition of the clock.
11. What is a master-slave flip-flop?
A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a
slave.

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