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The document describes a 6.5 month physical design training course covering digital design basics to advanced physical design using Synopsys tools at 14nm. The course syllabus is divided into physical design basics over 2.5 months covering topics like VLSI design flow, device fundamentals, and PD flow keywords. The main course over 4 months covers synthesis, timing constraints, floorplanning, routing, and industry projects.

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0% found this document useful (0 votes)
21 views

Www-Vlsiguru-Com-P

The document describes a 6.5 month physical design training course covering digital design basics to advanced physical design using Synopsys tools at 14nm. The course syllabus is divided into physical design basics over 2.5 months covering topics like VLSI design flow, device fundamentals, and PD flow keywords. The main course over 4 months covers synthesis, timing constraints, floorplanning, routing, and industry projects.

Uploaded by

Ankit Gorawat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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HOME > COURSE > PHYSICAL DESIGN TRAINING

PHYSICAL DESIGN TRAINING


Physical design training is a 6.5 months course covering all the aspects starting
from digital design basics to advanced physical design using multiple hands on
projects at 14nm using Synopsys tools.

Best Seller 4.6 Star(1665 rating) 2,525 (Student Enrolled)

Trainer
Multiple Experienced Trainers

Syllabus Course Overview Projects Schedule Demo FAQs Trainer Certificate

Physical design basics course syllabus (Duration: 2.5 months)

 VLSI Design flow

Specification

RTL coding, lint checks

RTL integration

Connectivity checks

Functional Verification

Synthesis & STA

Gate level simulations

Power aware simulations

Placement and Routing


Course Registration
DFT
Custom layout

Post silicon validation

 Semiconductor device fundamentals

 IC fabrication

 Advanced Digital Design

 Linux commands – hands on training

 PD flow keywords and VLSI Technology concepts

 TCL scripting

Physical design main course syllabus (Duration: 4 months)

 Synthesis

Basics of Synthesis

High Level Synthesis Flow

Reading of Verilog RTL File

Target and Link Libraries

Resolving References with Link Libraries

Reading hierarchical Designs

Reading ddc design

Analyse & Elaborate Commands

Constraining and Compiling RTL

Post Synthesis Output Data


 Timing Constraints

 UPF

 NDM Libraries

 Initial Design Setup

 Placement

 Power Planning

 Scan Chain RE-Ordering and RE-Partitioning

 Floor Planning

 Global Routing

 Clock Tree Synthesis

 Detailed Routing

 Power Analysis (Static and Dynamic)

 Engineering Change Order Flow (ECO)

 Multiple Industry standard Projects

 Design For Manufacturability


 Softskill Training


₹63,000 + GST ₹79,000 20% Off
10 hours left to avail at this price

COURSE REGISTRATION

ENROLL NOW

Course Highlights

 1-1 Dedicated Mentor Support

 24/7 Tool Access

 Multiple mock interviews

 Industry Standard Projects

 Support with resume update


VLSIGuru is a top VLSI training Institute based in Bangalore.
Setup in 2012 with the motto of ‘quality education at affordable
fee’ and providing 100% job oriented courses.

NAVIGATIONS SUPPORT OUR


E-Learning Internship Request COURSES
FAQ's Course Functional / ASIC
Corporate Training Registration verification

Contact Us Training Overview RTL design and


Certificate Request integration
Course Enroll
Course Feedback Design for
Installment Form
testability (DFT)
Important Links Course Schedule
Custom and
Mock Interview
Analog Layout

Synthesis and STA

IR Drop analysis
using RedHawk

Custom/Analog
layout

OUR
COURSES
Physical Design
Functional
verification

Physical
verification
FPGA system
design
Embedded
systems

PERL Training

Physical Design

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