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Uvm Commands

The document provides commands for compiling and simulating UVM, assertion, and coverage models in QuestaSim. It includes commands for compiling modules with UVM and assertion libraries, simulating designs and generating coverage reports. Flags and options for assertions, coverage and logging are also shown.

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jerinkakkurumpil
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21 views2 pages

Uvm Commands

The document provides commands for compiling and simulating UVM, assertion, and coverage models in QuestaSim. It includes commands for compiling modules with UVM and assertion libraries, simulating designs and generating coverage reports. Flags and options for assertions, coverage and logging are also shown.

Uploaded by

jerinkakkurumpil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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//--------------------------------------------------------

//*********SION SEMICONDUCTORS******
//--------------------------------------------------------

//---------------------------------------------------------------------------------
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//***************************UVM commands********************

//................compilation cmd...............

//Dont forget to change vlog after ur top module filename.sv

vlog TOP.sv +incdir+C:/questasim64_10.4e/verilog_src/uvm-1.1d/src


C:/questasim64_10.4e/verilog_src/uvm-1.1d/src/uvm_pkg.sv

vlog count_topp.sv +incdir+C:/questasim64_10.7c/verilog_src/uvm-1.1d/src


C:/questasim64_10.7c/verilog_src/uvm-1.1d/src/uvm_pkg.sv

//................simulation command.........

// dont forget to change vsim after ur top module name

vsim top -sv_lib C:/questasim64_10.7c/uvm-1.1d/win64/uvm_dpi -l run.log

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//*************************ASSERTION CMDS*****************

//.............compilation cmd...................

vlog +acc top.sv +incdir+C:/questasim64_10.7c/verilog_src/uvm-1.1d/src


C:/questasim64_10.7c/verilog_src/uvm-1.1d/src/uvm_pkg.sv

//........simulation cmd..........................

vsim -assertcover -assertdebug -gui top -sv_lib


C:/questasim64_10.7c/uvm-1.1d/win64/uvm_dpi -l run.log

1)assertion tab open (if assertion tab is not opened then go to view option select
coverage then select assertion)
2) Once opened the assertion tab labels will be there , select those labels as Add
wave -> selected objects
3) Nxt select top -> add to wave -> all items in region above and below
4) run -all
5) Check assertion flag passed or not in waveforms

Green flag- assertion passed


Red flag -assertion failed
Blue flag-assertion inactive

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//*************************COVERAGE CMDS******************

//.................compilation cmd..................

vlog -coveropt 3 +cover +acc top.sv +incdir+C:/questasim64_10.7c/verilog_src/uvm-


1.1d/src C:/questasim64_10.7c/verilog_src/uvm-1.1d/src/uvm_pkg.sv

//................simulation cmd......................

vsim -coverage top -sv_lib C:/questasim64_10.7c/uvm-1.1d/win64/uvm_dpi -l run.log

add to wave -> run -all -> open covergroups tab check how many bins are hitted
analyse -> tools-> coverreport-> generate in html

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