Basics of Verilog - Session 1
Basics of Verilog - Session 1
Basics of Verilog - Session 1
Ex:
module basic_gates
(input a, b, output y1,y2,y3,y4);
assign y1 = a & b;
assign y2 = a | b;
assign y3 = a ^ b;
assign y4 = a ~^ b;
endmodule
• Ex: assign, case, while, wire, reg, and, or, nand, module,…
Ex:
module basic_gates ( input in1, in2, output out1, out2, out3);
assign out1 = in1 & in2; // and gate
/* assign out2 = in1 | in2;
assign out3 = in1 ^ in2; */
endmodule
All the verilog data types, which are used in verilog stores
these values –
Ex:
* 6‟d51 = 6‟b110_011 = 6‟o63 = 6‟h33
* 8‟hab = 8‟b1010_1011
* 9‟o3xz = 9‟b011_xxx_zzz
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Verilog Data types
Data types
Ex:
wire a;
wire [3:0] b; // 4 bit
Ex:
reg reset;
initial
begin
reset = 1‟b1;
#100 reset = 1‟b0;
end
Ex :
Ex:
wire arrayA[0:7];
reg arrayB[0:3];
The use of parameters make the code easy to read and modify.
Ex:
Parameter ADDR_WIDTH = 4,
DATA_WIDTH = 8;
Wire [ADDR_WIDTH – 1 : 0] addr;
// adder
module # ( parameter N = 2)
( input [ ( N – 1 ) : 0 ] a , b ,
output [ ( N - 1 ) : 0 ] sum , output cout ) ;
endmodule
• Keywords :
Input port – input
Output port – output
Bidirectional port – inout
1. Structural level
3. Behavioral level
endmodule