Basics of Verilog - Session 1

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Basics of Verilog – Session 1

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Introduction to Verilog

What is Verilog? Where will the verilog be


used?

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Why, What and Where are HDLs now?

• Why? In early 1980s, Digital logic circuit descriptions and Simulations


were done using Schematics, which is error prone proportional to circuit
size. Thus, designers felt a need for language to describe and simulate such
circuits.

• What? Originally developed for conveniently describe digital logic circuits


for Simulations. Later pushed to use as a specification language for logic
Synthesis as well.

• Where? In today‟s world, virtually every chip (FPGA, ASIC, etc.) is


designed in part using HDL languages.

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• Verilog is the hardware description language ( HDL ) used to
design the electronic systems

• It is used in design and verification of digital circuits at the


Register-transfer-level ( RTL )

• Verilog – IEEE 1364 – 2005

• 2009, merged into system verilog creating IEEE standard


1800-2009.

• The current version of verilog is IEEE standard 1800 - 2017

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Where will the verilog be used?

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The Structure of Verilog

Ex:
module basic_gates
(input a, b, output y1,y2,y3,y4);

assign y1 = a & b;
assign y2 = a | b;
assign y3 = a ^ b;
assign y4 = a ~^ b;

endmodule

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Identifiers
• Identifier is the name used to define the object, such as a
function, module or register.

• Can be formed from [A - Z] , [ a – z ] , [ 0 – 9 ] , _ , $

• Can‟t begin with $ or [ 0 – 9 ]

• Identifiers should not be the keywords of verilog.

Ex: reg value;


input clk;
input 1clk; // invalid
wire module; // invalid
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Verilog keywords

• The words that have special meaning in verilog are called


the verilog keywords.

• Ex: assign, case, while, wire, reg, and, or, nand, module,…

• These should not be used as identifiers.

• Verilog keywords also include compiler directives, system


tasks and functions.

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Comments
The two forms of representing the comments

1. Single line comment ( // )


2. Multiple line comment ( /* */)

• Nesting the comments do not work

Ex:
module basic_gates ( input in1, in2, output out1, out2, out3);
assign out1 = in1 & in2; // and gate
/* assign out2 = in1 | in2;
assign out3 = in1 ^ in2; */
endmodule

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Value set in verilog

All the verilog data types, which are used in verilog stores
these values –

0 - logic zero, or false condition

1 – logic one, or true condition

x – unknown logic value

z – high impedance state


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Representing Numbers

Ex:
* 6‟d51 = 6‟b110_011 = 6‟o63 = 6‟h33
* 8‟hab = 8‟b1010_1011
* 9‟o3xz = 9‟b011_xxx_zzz
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Verilog Data types
Data types

Fixed / net data type variable data type


1. wire 1. reg
2. wand 2. integer
3. wor 3. time
4. trior, triand 4 . real

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Net data type:

Represents the connection between the hardware elements.


Keyword : wire
Size : 1 bit unless they are declared explicitly as vectors.
Default value : 1‟b Z

Ex:
wire a;
wire [3:0] b; // 4 bit

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Reg data type :

Represents the data storage element.


Keyword : reg
Default value : 1‟b X

Ex:
reg reset;
initial
begin
reset = 1‟b1;
#100 reset = 1‟b0;
end

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• Integers - An integer is a general purpose register data type
used for manipulating quantities.
It‟s default value is signed 32 bits „x‟

Ex: integer counter ; // general purpose variable used as a counter


initial
counter = -1 ; // A negative one is stored in the counter

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• Real :

- declared with the keyword “real”


- Can be specified in decimal notation ( ex. 3.14) or in scientific
notation (ex. 3e6 = 3 x 106).
- default value is 0
Ex:
real delta; // define a real variable called delta
initial
delta = 2.13 // delta is assigned a value 2.13
integer i;
initial
i = delta; // i gets the value 2 ( rounded value of 2.13 )

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Time :

It is used to store the simulation time.

Declared with keyword “ time”

Ex :

time save_sim_time; // define a time variable save_sim_time


initial
save_sim_time = $time; // save the current simulation.

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Buses

• Buses (group of signals) can be declared either as a


wire or reg type.

• Accessing buses. Ex: wire [7:0]busA; reg [3:0]busB;

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Arrays

• Arrays ( group of same signals or buses ) can be declared


either as wire or reg type.

Ex:
wire arrayA[0:7];
reg arrayB[0:3];

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Memories

Memories are usually arrays of buses, specified by their width


and depths. They can either be of wire or reg type.

Ex: wire [7:0] mem [0:3];


reg [7:0] mem [0:3];

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Parameters

The use of parameters make the code easy to read and modify.

Ex:
Parameter ADDR_WIDTH = 4,
DATA_WIDTH = 8;
Wire [ADDR_WIDTH – 1 : 0] addr;

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Ex:

// adder

module # ( parameter N = 2)
( input [ ( N – 1 ) : 0 ] a , b ,
output [ ( N - 1 ) : 0 ] sum , output cout ) ;

assign { carry, sum } = a + b ;

endmodule

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Port Declarations

• Keywords :
Input port – input
Output port – output
Bidirectional port – inout

• Each port should be declared with its


signal type (wire / reg).

• wire – for all input, inout ports,


output ports driven from
assignment blocks.
• reg – output ports driven from
procedural blocks

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Ex: module generic_digital_circuit(
input wire in1,
input wire in2,
input wire in3,
output wire out1,
output reg out2,
output reg out3,
inout wire io1,
inout wire io2,
inout wire io3);
// parameter declarations
// internal signal declarations
// lower level module declarations
// concurrent assignments
// procedural statements
endmodule
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Modeling styles of verilog

Verilog is matured to model digital circuit accurately at


different levels of abstraction.

1. Structural level

2. Data flow level

3. Behavioral level

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1. Structural modeling

Structural style is the closest to a logic – level circuit made up


of gates.

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Verilog predefined primitives

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Ex

module basic_gates (input a,b, output out1,out2,out3,out4 );

and a1 (out1, a, b);


or o1 (out2, a, b);
xor x1 (out3, a, b);
xnor x2 (out4, a, b);

endmodule

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Port mapping in verilog

Types: ordered association


1. ordered association and
2. named association module basic_gates (input a, b, output y);
and_gate a1 (y, a, b);
or_gate o1 (y, a, b);
module and_gate (input a,b,output y);
endmodule
assign y = a&b;
endmodule
named association
module or_gate (input a,b,output y);
module basic_gates (input in1, in2, output o1);
assign y = a|b;
and_gate a1 ( .a(in1), .b(in2), .y(o1));
endmodule
or_gate o1 (.a(in1), .b(in2), .y(o1));
endmodule

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module half_adder (input a, b, output s, c);
assign s = a ^ b;
assign c = a & b;
endmodule

module full_adder (input a, b, cin, output sum, carry);


wire s1,c1,c2;
half_adder a1 ( .a(a),.b(b),.s(s1),.c(c1) );
half_adder a2 ( .a(cin),.b(s1),.s(sum),.c(c2) );
or o1 (carry,c1,c2 );
endmodule

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