Freescale Semiconductor AN3118

Rev. 0, 8/2005
Application Note

Production Flash Contents

Programming for the 1. Introduction .........................................1

56F8000 Family 2. Background Information .....................1

2.1 Considerations for Choosing a
Techniques for Production Programming the Production Programming Method ...2
56F8000 Family of Devices, Flash Memory 3. Programming Method Details .............3
Blocks 3.1 Serial SCI Bootloader .....................3
3.2 Bulk Device Loader ........................ 3
3.3 In-circuit JTAG/OnCE Port ............ 4
Leonard N. Elevich
3.4 GPIO Flash Programming Mode .... 5

4. Conclusion ..........................................6
1. Introduction 5. References ...........................................6
This document presents techniques and detailed information on
production programming of the Program Flash memory blocks
in the 56F8000 components. This is distinct from the
developmental loading of the Flash blocks that is achieved
using developmental tools such as the Metrowerks
CodeWarrior for Freescale debugger.
There are four ways to program the Flash blocks in a factory
environment:
• Using the Serial Bootloader present in the Internal
Flash
• Using a commercially-available device programmer
• Using the JTAG/OnCETM port
• Using GPIO pins with a custom bootloader
The first two methods do not require any developmental effort
to use. Using the GPIO pins to obtain the Flash programming
data would require the customer to develop his own loader
program.

2. Background Information
As a starting point, all methods require an application to be
created using the CodeWarrior development tools. This
application must be specifically targeted to operate correctly
from the internal Flash. The Freescale CodeWarrior
Development tools includes information as well as code to aid

© Freescale Semiconductor, Inc., 2005. All rights reserved.

Background Information

in the development of the application. It is highly recommended that a developer start with the appropriate
Processor Expert (PE) stationery. This will greatly facilitate the development of the application, and includes
all the elements required to create embedded applications targeting internal Flash. During development and
debug of the application, the CodeWarrior tool can be used to program the internal Flash and to debug the
program while running from Flash. Once the development and test are complete, the CodeWarrior tool can also
be used to generate the source file containing the executable image of the Program Flash block. In this case, the
source file is an S-record file. The S-record file contains the hex machine code and hex data information
formatted in a text file containing a series of S3-type S-records. Refer to Appendix A at the end of this
document for a detailed description of the format of the S-record file.
The CodeWarrior tool normally uses .elf files to store the application executable and to program the Flash
blocks in the devices. The user must specifically configure the CodeWarrior tool to create the S-record file.
Please refer to the CodeWarrior Targeting 56800E Manual for information on how to turn on S-record
generation. The CodeWarrior tool generates three separate types of S-record files:
• output_filename.p.S contains the Program Flash image
• output_filename.x.S contains the Data Flash image
• output_filename.S contains the combined Program and Data Flash images
The S-record file is the source file used by first two methods of production Flash programming. The file to use
when performing Flash programming will generally be the combined file, containing the Program and Data
Flash image. Please note that while 56F8000 devices do not have Data Flash, it is still recommended to use
combined S-record file.

2.1 Considerations for Choosing a Production Programming Method

A fundamental decision to be made is whether to initially program the devices after they have been soldered to
the circuit board, or to initially program the devices before they are placed onto the circuit board. Programming
with the Boot Flash Serial Bootloader, programming via the JTAG/OnCE port and the GPIO Flash
programming mode are primarily intended as in-circuit programing methods. The bulk device load method is
an out-of-circuit programming method, which allows programming the 56F8000 devices in advance of the
production run.
Since the JTAG/OnCE port and the bulk device loader mode options do not require that software be run from
any of the Flash blocks, they can reprogram any block without special considerations. The 56F8000 chips are
fully field reprogrammable, requiring no special voltages or external hardware to perform this function.
There is another option to consider. All of the 56F8000 devices also contain on-chip program RAM. A
bootloader can be loaded into this RAM and, from there, all Flash blocks can be reprogrammed.
All in-circuit Flash loading methods require that the target hardware conforms to certain minimal standards.
For the Serial Bootloader, these standards require that:
• The SCI port must be accessible for serial communications
Using the JTAG/OnCE port method requires only that a subset of the JTAG/OnCE pins be made available.
Please refer to Section 3.3 for details.
Using the GPIO port method would require access to any user-specified GPIO pins that the user-defined
bootloader software specified.
The approximate speeds at which the Flash blocks can be programmed with the various methods are:
• SCI Serial Bootloader = 2.5K words per second
• Bulk device programmer = 3K words per second
• In-circuit JTAG/OnCE port = 3K words per second.

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2 Freescale Semiconductor
 Bulk Device Loader

3. Programming Method Details

3.1 Serial SCI Bootloader
The software and protocol for this loader and how to use it are fully described in the Metrowerks on-line help
and web site (see References). Please refer to the SCI Bootloader application information in the 56F801x
Serial Bootloader User Guide for the processor being used. This manual has detailed information on how to
use the Serial Bootloader and how to prepare your application for loading using the Serial Bootloader.

Table 3-1. Details of SCI Serial Bootloader Versions 1.2

Version Baud Rate Flow Control Word Format

1.2 115,200bps Xon/Xoff 8 data bits, no parity, 1 stop bit

Figure 3-1 shows a possible hardware configuration for using the Serial Bootloader to program the device
in-circuit. This is one of many possible hardware configurations that will support the use of the Serial
Bootloader to program the device.

56F801x Target
Hardware Card

Pads tied to SCI signal

lines TXD0 and RXD0 RS-232 Interface Card
RS-232 Cable

Two-pin probe

IBM-Compatible

Figure 3-1. One Hardware Configuration for SCI Serial Bootloader

The configuration in Figure 3-1 shows how the Serial Bootloader can be used, even though the target
hardware has no additional connectors or RS-232 serial drivers. In addition, using an IBM-compatible
computer is not required--any host capable of providing the required serial stream and the protocol can be used.

3.2 Bulk Device Loader

In this method, the devices are programmed out-of-circuit in a device loader. The programming can be
performed using your own resources, or possibly through your distributor or another value-added reseller. The
device programmer can also be used to program the Program Flash blocks. The device programmer can be
used to load a complete and final application, or simply a custom Bootloader program. Later, the final or
complete application can be loaded using the custom Bootloader.
Please check www.freescale.com/dsc for device programmers support.

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Freescale Semiconductor 3
Programming Method Details

3.3 In-circuit JTAG/OnCE Port

To use this method, the user must provide access from his host computer to the JTAG/OnCE port signals on
the devices. Table 3-2 shows the required signals. If the programming set-up uses a standard command
converter to interface to the JTAG signals, then a standard JTAG pin header connector must be present on the
custom card. An example of this is present on the MC56F8013DEMO board; information on it is also included
in the 56F8013 Demonstration Board User Guide, which can be downloaded from Freescale’s website at:
http://www.freescale.com/dsc.

Table 3-2. Required JTAG/OnCE Signals

Signal Signal Description Required

TDI Test Data Input—This input pin provides a serial input data stream to Yes
the TAP and the TLM. It is sampled on the rising edge of TCK. TDI has
an on-chip pull-up resistor which can be disabled through SIM_PUDR
register in the SIM module.

TDO Test Data Output—This tri-state output pin provides a serial output Yes
data stream from the Master TAP, or 56800E core TAP Controller. It is
driven in the Shift-IR and Shift-DR controller states of the TAP
Controller state machines. Output data changes on the falling edge of
TCK.

TCK Test Clock Input—This input pin provides the clock to synchronize the Yes
test logic and shift serial data to and from all TAP Controllers and the
TLM. If the EOnCE module is not being accessed using the Master or
56800E core TAP Controllers, the maximum TCK frequency is 1/4 the
maximum frequency for the 56800E core. When accessing the EOnCE
module through the 56800E core TAP Controller, the maximum fre-
quency for TCK is 1/8 the maximum frequency for the 56800E core.
The TCK pin has a pull down non-disabled resistor.

TMS Test Mode Select Input—This input pin is used to sequence the TAP Yes
Controller’s TLM state machine. It is sampled on the rising edge of
TCK. TMS has an on-chip pull-up resistor which can be disabled
through SIM_PUDR register in the SIM module.

TRST Test Reset—This input pin provides an asynchronous reset signal to Yes
the TLM and all TAP Controllers. If the JTAG is not going to be used,
prevent signal interference by holding it low during operation.

The CodeWarrior tool, which supports command line interface as well as scripting, can be used to download
the program in production environment. The following steps must be performed to prepare for pruduction flash
programming:
• Install CodeWarrior Development tools on IBM-compatible machine that will be used in production
environment
• Obtain and install free 8K Words license key to enable CodeWarrior functionality
• Compile project cantaining final application on the development machine.
• Copy all project files except source code from the development machine to production machine.

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 GPIO Flash Programming Mode

• Open CodeWarrior IDE on production mashine and select Edit/Preferenses menu

• Set “Building before running” to “Never” in the “Build Settings” pannel
• Click “OK” button to save changes.
• Create a CodeWarrior TCL script file that will load application project into flash via CodeWarrior
debugger. Example 3-1 provides example of this script file named test.tcl In this example, script will
load an application project named script1.mcp located in D:\tmp\cw_script1 directory
• Create a batch file that will execute this TCL script from the command line. Example 3-2 provides
example of this batch file named test.bat. In this example batch file will execute test.tcl script located
in D:\tmp\cw_script1 directory. Please note that path to cmdide.exe may need to be modified to reflect
your actual CodeWarrior installation directory.

Code Example 3-1. Example TCL file test.tel

debug d:/temp/cw_script1/script1.mcp
go nowait
kill

Code Example 3-2. Example Batch file test.bat

“d:\program files\metrowerks\codewarrior 7.2\bin\cmdide.exe” /d

d:\temp\cw_scrip1\test.tc1

Once above preparation steps are completed, production technician can programm Flash simply by executing
created batch file.
Detailed information on how to program using the JTAG/OnCE port is available and can be requested from
your Freescale sales representative.

3.4 GPIO Flash Programming Mode

This mode requires the customer to define his own definition of GPIO Flash programming pin definitions and
code load protocol. He would then have to develop an appropriate bootload application to program into the
Boot Flash. This approach would also require the customer to provide access to the required pins for his
program loading.

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Freescale Semiconductor 5
Conclusion

4. Conclusion
The 56F810x components are very flexible in programming Flash blocks. In this application note, several
methods have been presented for programming the Flash blocks in a production environment. One of these
methods, or a variation of it, should meet your production Flash programming requirements.

5. References
The following materials were used to produce this paper:
1. CodeWarrior IDE Targeting 56F8300 Manual
CodeWarrior for Freescale DSP56800E Embedded Systems, CWDSP56800E
2. Targeting Freescale 56F8300 Platform, Processor Expert
CodeWarriorTM Development Studio for 56800/E Hybrid Controllers with Processor Expert, CW568x
3. 56F801x Evaluation Module Hardware User Manual for the device being implemented
4. 56F801x Serial Bootloader User Guide, MC56F801xBLUG
5. Programming On-Chip Flash Memories of DSP56F80x DSPs using the JTAG/OnCE Interface, AN1935
6. Metrowerks help:
www.metrowerks.com/MW/support
or
[email protected]

Production Flash Programming, Rev. 0

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 GPIO Flash Programming Mode

Appendix A S-Record Specification

Note: All references to Data Flash in the appendix apply only to the 56F8300 family of devices; the 56F8100
devices do not support Data Flash.
1) Use only S0, S3 and S7 records
2) Three S-Record files are built with every compile. The first contains the contents of all initialized
PROGRAM (P) Memory contents. The second file contains the contents of all initialized DATA (X) Memory
contents.
3) The third S-Record file (the “combined” file) is roughly a concatenation of the P file with the X file (P
followed by X). The S3 data records targeted for X shall have an offset of 0x02000000 added to their byte
address fields. There shall be only a single pair of S0 and S7 records for the entire combined file.

Notes:
• The P (and combined) file may contain: Program Flash contents, Program RAM contents, Boot Flash
contents
• The X (and combined) file may contain: Data Flash contents, Data Ram contents
• The device programming algorithm shall be address range aware
a) The byte address fields of S3 data records are examined by the device programming algorithm to
determine which Flash memory to access

b) The offset of 0x02000000 for X data records is required because the P and X memories within the
56F8300 devices both start at address 0. (S-Records don't normally support overlapping memories;
defining an offset is the most expedient work-around for the problem.)

c) Data specified for RAM locations shall be ignored by the device programming algorithm.
4) Unique codes shall reside in the P, X and combined S0 header records. In this manner, the S0 records will
identify the subsequent contents as either P, or X, or combined. The proposed S0 header records are as follows:

Code Example A-1. S0 Record for the P File

S0 0C 00000000 50 52 4F 47 52 41 4D DB
(Hex ASCII for: P R O G R A M )

Code Example A-2. S0 Record for the X File

S0 09 00000000 44 41 54 41 DC
(Hex ASCII for: D A T A )

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References

Code Example A-3. S0 Record for the Combined File

S0 11 00000000 50 52 4F 47 52 41 4D 26 44 41 54 41 96
(Hex ASCII for: P R O G R A M & D A T A)

Notes: The device programming algorithm will not be expected to recognize contents within any S0 record.
The S0 content is only to aid with human recognition of file contents and to assist in content
recognition by future tools.
5) S3 data shall not split across a processor word size (16 bits). In other words, there shall be an even number
of “data” bytes within each S3 record.
Sample S-Record files for the 56F8300 and 56F8100 follow. (Spaces have been inserted for improved
readability in this document; “CS” is a space holder for the checksum byte.) The address fields of the S3 record
shall be conventional BYTE addresses and byte data shall be represented in the Little-endian format. (The
Least Significant Byte [LSB] is located at the lowest address.)

Notes:
• In this manner, the constituent P or X S-Record files can be used to program any conventional
(external) non-volatile memory devices, without the need for any additional S-Record manipulation
utility programs
• 56F8300 and 56F8100 processors have a native 16 bit word. Likewise, the Flash memories are
programmed with 16-bit words and all addresses are interpreted as word addresses
• To get from the S-Record Byte address to the 56F8300 and 56F8100 16-bit Word address, divide the
S-Record address field value by 2. For X memory, first subtract the 0x02000000 offset, then
unscramble the little-endian format to recognize the data words.

Code Example A-4. Sample P File

S0 0C 00000000 50 52 4F 47 52 41 4D DB "PROGRAM"
S3 0D 00000000 10 32 11 32 12 32 13 32 CS
S3 0D 00000008 14 32 15 32 16 32 17 32 CS
S3 0D 00000010 18 32 19 32 1A 32 1B 32 CS
S3 0D 00040000 10 B2 11 B2 12 B2 13 B2 CS Boot Flash starts at word
S3 0D 00040008 14 B2 15 B2 16 B2 17 B2 CS address 20000
S7 05 00000000 CS (byte address 40000)

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 GPIO Flash Programming Mode

Code Example A-5. Sample X File

S0 09 00000000 44 41 54 41 DC "DATA"
S3 0D 00002000 10 A2 11 A2 12 A2 13 A2 CS Note: There is no offset
S3 0D 00002008 14 A2 15 A2 16 A2 17 A2 CS used in the stand-alone
S7 05 00000000 CS X S-Record file.
In this example, word
address 1000 is the first
location to be programmed.

Code Example A-6. Sample Combined File

S0 11 00000000 50 52 4F 47 52 41 4D 26 44 41 54 41 96 "PROGRAM
S3 0D 00000000 10 32 11 32 12 32 13 32 CS & DATA"
S3 0D 00000008 14 32 15 32 16 32 17 32 CS
S3 0D 00000010 18 32 19 32 1A 32 1B 32 CS
S3 0D 00040000 10 B2 11 B2 12 B2 13 B2 CS Boot Flash starts at word
S3 0D 00040008 14 B2 15 B2 16 B2 17 B2 CS address 20000

S3 0D 02002000 10 A2 11 A2 12 A2 13 A2 CS Big offset of 0x02000000

S3 0D 02002008 14 A2 15 A2 16 A2 17 A2 CS signifies X data follows
S7 05 00000000 CS

S-Record Explanation
S0 05 00000000 (data) CS

S0 S0 is a header record
S3 S3 is data
S7 S7 terminator for block of S3

05 (hex) 5 bytes follow

00000000 32 bits of byte addresses

CS The Least Significant Byte (LSB) of the one's

complement of the sum of the values represented
in the pairs of characters making up the record
length, address, and the data fields

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Freescale Semiconductor 9
References

After programming the 56F8300 or 56F8100 with either the combined file or both stand-alone P and X files, a
debugger dump would yield results like those in the following Code Examples:

Code Example A-7. Dump of Program (P) Flash

address p:00 0000 = 3210

address p:00 0001 = 3211
address p:00 0002 = 3212
address p:00 0003 = 3213
address p:00 0004 = 3214...

Code Example A-8. Dump of Boot Flash

address p:02 0000 = B210

address p:02 0001 = B211
address p:02 0002 = B212
address p:02 0003 = B213...

Code Example A-9. Dump of Data (X) Flash

address x:00 1000 = A210

address x:00 1001 = A211
address x:00 1002 = A212
address x:00 1003 = A213
address x:00 1004 = A214...

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 GPIO Flash Programming Mode

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Freescale Semiconductor 11
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AN3118
Rev. 0
8/2005