Digital Integrated

Circuits
A Design Perspective

Designing Combinational
Logic Circuits

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Combinational vs. Sequential Logic

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

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Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or GND via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

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Static Complementary CMOS
PUN provides a connection between output and VDD
VDD, when the output of the gate evaluates a
“1”. The PDN provides a connection between
output and ground, when the output of the gate In1
PMOS only
evaluates a “0”. In2 PUN

…
In steady-state, the output node is low- InN
impedance
F(In1,In2,…InN)
In1
In2 PDN

…
NMOS only
InN

PUN and PDN are dual logic networks

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NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

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PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

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 Threshold Drops
VDD VDD
PUN
S D
VDD

D S
0 → VDD VGS 0 → VDD - VTn

CL CL

PDN VDD → 0 VDD → |VTp|

VGS
D S
CL CL
VDD

S D

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Complementary CMOS Logic Style

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Example Gate: NAND

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Example Gate: NOR

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 Complex CMOS Gate

B
A
C

D
OUT = D + A • (B + C)
A
D
B C

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 Constructing a Complex Gate
VDD VDD
OUT = D + A • (B + C)
C
SN1 F SN4 A
F
SN2 B
A A
D D SN3

B C B C D

(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C

(c) complete gate

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Properties of Complementary CMOS Gates
Snapshot

High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)

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 CMOS Properties
q Full rail-to-rail swing; high noise margins

q Logic levels not dependent upon the relative device sizes;

ratioless

q Always a path to Vdd or Gnd in steady state; low output

impedance

q No direct path steady state between power and ground; no static

power dissipation

q Propagation delay function of load capacitance and resistance

of transistors

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 Switch Delay Model
A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV
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 Input Pattern Effects on Delay
q Delay is dependent on
Rp Rp
the pattern of inputs
A B
q Low to high transition
Rn CL
§ both inputs go low
– delay is 0.69 Rp/2 CL
B
§ one input goes low
Rn – delay is 0.69 Rp CL
Cint
A q High to low transition
§ both inputs go high
– delay is 0.69 2Rn CL

Series devices should be made wider to avoid performance penalty.

When sizing the transistors in a gate with multiple inputs, we should
pick the combination of inputs that triggers the worst case condition
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(be
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careful of self-loading)
 Example: Delay Dependence on Input Patterns
In general, the sizing should result in approx. equal worst case rise and fall times.

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Input Data Delay
2.5 A=B=1→0
Pattern (psec)
2 A=B=0→1 67
A=1 →0, B=1
A=1, B=0→1 64
Voltage [V]

1.5

1
A=1, B=1→0 A= 0→1, B=1 61

0.5 A=B=1→0 45

0 A=1, B=1→0 80
0 100 200 300 400 A= 1→0, B=1 81
-0.5
time [ps] NMOS = 0.75µm/0.25 µm
PMOS = 0.75µm/0.25 µm
CL = 100 fF 17
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Transistor Sizing (compared to a CMOS inverter)

Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

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 Transistor Sizing a Complex
CMOS Gate
B 8 6
A 4 3
C 8 6

D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2

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Fan-In Considerations
A B C D

A CL Distributed RC model
B C3 (Elmore delay)
t PHL = 0. 69[ R1 .C1 + ( R1 + R2 ).C2 + ( R1 + R2 + R3 ).C 2 + ( R1 + R2 + R3 + R4 ).C L ]
C C2
D tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
C1
R1 appears in all terms, making this device
especially important when attempting to
minimize delay.

Internal node capacitances consist of junction capacitances, and gate-to-source

and gate-to-drain capacitances (turned into capacitances with ground using
Miller equivalent) 20
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 tp as a Function of Fan-In
1250
quadratic
1000
Gates with a fan-in
greater than 4
750 tpHL
tp (psec)

should be avoided.

500

250 tpLH
linear
0
2 4 6 8 10 12 14 16
fan-in

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Fast Complex Gates: Design Technique 1

q Transistor sizing
§ as long as fan-out capacitance dominates
q Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)

In2 M2 C2 Can reduce delay by more than 20%.

Problem: Design rule considerations
In1 M1 C1 force designer to push transistors apart
-> internal capacitance grows.
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Fast Complex Gates: Design Technique 2

q Transistor ordering
critical path critical path

charged 0→1
In3 1 M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
0→1

delay determined by time to delay determined by time to

discharge C L, C 1 and C2 discharge C L
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 Fast Complex Gates: Design Technique 3

q Alternative logic structures

F = ABCDEFGH

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