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Grade 10 Notes Printed - 11 - 2010 - Fetch Execute Cycle

The document describes the Von Neumann architecture and the fetch-decode-execute cycle of a CPU. It explains the basic components involved like the program counter, memory address register, memory data register, and control unit. It provides a detailed example of the fetch-decode-execute cycle showing the processing of a single 'Load 5' instruction.

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13 views2 pages

Grade 10 Notes Printed - 11 - 2010 - Fetch Execute Cycle

The document describes the Von Neumann architecture and the fetch-decode-execute cycle of a CPU. It explains the basic components involved like the program counter, memory address register, memory data register, and control unit. It provides a detailed example of the fetch-decode-execute cycle showing the processing of a single 'Load 5' instruction.

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hlt
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COMPUTER ARCHITECTURE AND THE FETCH – DECODE – EXECUTE CYCLE

Simple representation of Von-Neumann architecture:

Memory
CPU Unit

Key I/O
Control Bus device
Input
Data Bus
and
Address Bus
Output
I/O
device
Bus: It is a distinct set of conductors carrying data and control signals within a computer system,
to which pieces of equipment may be connected.

Bus type Description Direction of Signal


Carries signal relating to addresses between the
Address Bus Travels in one direction
processor and the memory
Sends data between the processor, the memory
Data Bus Travels in both directions
unit and input/output devices.
Carries signals between devices, memory and
Control Bus Travels in both directions
processor to coordinate tasks between them.

The Fetch-Decode-Execute cycle of a computer is the process by which a computer:


1. FETCH - fetches a program instruction from its memory,
2. DECODE - determines what the instruction wants to do,
3. EXECUTE - and carries out those actions.

Registers/circuits involved
The circuits used in the CPU during the cycle are:
 Program Counter (PC) - an incrementing counter that keeps track of the memory address of
which instruction is to be executed next.
 Memory Address Register (MAR) - the address in main memory that is currently being read
or written
 Memory Buffer / Data Register (MBR / MDR) - a two-way register that holds data fetched
from memory (and ready for the CPU to process) or data waiting to be stored in memory
 Current Instruction register (CIR) - a temporary holding ground for the instruction that has
just been fetched from memory
 Accumulator - a register used to contain the results of an arithmetical or logical operation.
 Control Unit (CU) - decodes the instruction in the CIR, selecting machine resources such as a
data source register and a particular arithmetic operation, and coordinates activation of
those resources
 Arithmetic logic unit (ALU) - performs mathematical and logical operations

©AIS COMPUTER ARCHITECTURE & FEC COMPUTER SCIENCE Page 1 of 2


The program counter (PC) contains the address of the memory location of the next instruction which has to be fetched

This address is then copied from the PC to the memory address register (MAR), this is done using the address bus

The contents (instruction) at the memory location (address) contained in MAR are then copied temporarily into the
memory data register (MDR)

The contents (instructions) of the MDR are then copied and placed into the current instruction register (CIR)

The value in the PC is then incremented by 1 so that it now points to the next instruction which has to be fetched

The instruction is finally decoded and then executed by sending out signals (via the control bus) to the various
components of the computer system

Detailed description of the Fetch-Decode-Execute Cycle


Example shows the processing of a single instruction: “Load 5”.
PC 1 1 Load 5
MAR 1 2 Add 6
The contents of the Program Counter, the address of the MDR 3 Store 7
next instruction to be executed, is placed into the Memory CIR 4
Address Register 5 12
6 8
7
PC 1 1 Load 5
The address is sent from the MAR along the address bus to MAR 1 2 Add 6
MDR Load 5 3 Store 7
the Main Memory. The instruction at that address is found
CIR 4
and returned along the data bus to the Memory Data 5 12
Register. 6 8
7
PC 2 1 Load 5
The MDR loads the Current Instruction Register with the MAR 1 2 Add 6
MDR Load 5 3 Store 7
instruction to be decoded / executed. At the same time the
CIR Load 5 4
contents of the Program Counter is increased by 1, to initiate 5 12
the next instruction to be executed. 6 8
7
PC 2 1 Load 5
MAR 5 2 Add 6
MDR 3 Store 7
The instruction is sent to the CU for decoding and now the
CIR Load 5 4
Address part of the instruction is copied into the MAR. 5 12
6 8
7
PC 2 1 Load 5
MAR 5 2 Add 6
The Address bus locates the address 5 and the Data bus MDR 12 3 Store 7
fetches the value “12” stored in address 5 and carries it to CIR Load 5 4
the MDR. 5 12
6 8
7
The data bus now carries the value 12 from MDR and stores
it in the accumulator. This ends one F-D-E-C

©AIS COMPUTER ARCHITECTURE & FEC COMPUTER SCIENCE Page 2 of 2

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