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Verilog Guide

The document provides instructions for setting up Verilog and running Verilog code. It explains how to install Verilog, set the environment path, and use commands like iverilog and vvp to run Verilog files. It also gives an overview of some common Verilog keywords like module, always, and initial.

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Govind Gupta
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29 views3 pages

Verilog Guide

The document provides instructions for setting up Verilog and running Verilog code. It explains how to install Verilog, set the environment path, and use commands like iverilog and vvp to run Verilog files. It also gives an overview of some common Verilog keywords like module, always, and initial.

Uploaded by

Govind Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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VERILOG GUIDE

SETUP:
1. Download Verilog: iverilog-v12-20220611-x64_setup

2. Go to “bin” folder in iverilog and copy the path C:\iverilog\bin

3. Advance system settings >> Environment Variables >> path >> paste C:\iverilog\bin

NOTE:
Add copied path to
both “user variables”
and “System variables.”
 Open command prompt in “bin” and run command iverilog

 Repeat above steps for path C:\iverilog\gtkwave\bin

 Verilog installed successfully.

How to run Verilog file:


 Method-1: write the Verilog code in any text editor like notepad, Textedit and run the
Verilog commands in terminal i.e., cmd
 Method-2: write the Verilog code in VScode and run in terminal there.
Verilog Commands:
 Using text editor:
1. iverilog.exe -o Object_file file_name.v : creates an Object file of name
‘object_file’ of Verilog file file_name.v
2. vvp object_file : executes the code

 Using VScode:
1. iverilog -o Object_file file_name.v File_name_tb.v
2. vvp object_file
3. gtkwave object_file.vcd
Verilog Keywords:
module Represents block of Verilog code that implements certain behavioural
characteristics.
test.v Top level module that contains the design code.
test_tb.v Top level module (testbench code) that contains stimulus to check
functionality of design.
initial Procedural block used to initialize variables and drive design ports with specific
values.
always Procedural block that executes statements sequentially based on some
events.
always@(*) Always executes statements independent of condition.
$dumpfile Dump the changes in the values of wires and registers in file inside its argument
i.e., $dumpfile(“test.vcd”);
$dumpvars Specifies which variables are to be dumped mentioned in dumpfile.
$finish Terminates the current simulation.

NOTE: $dumpvars(0, testbench_file) signifies that when level is set to 0, it dumps all the
variables of that module and all the variables in lower level modules instantiated by this top
module.

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