Copy #

Preliminary Edition

UC T Maintenance Manual

COMPANY CONFIDENTIAL

The information contained in this manual is the property

of the Sperry Rand Corporation and is Company Confidential.
It is submitted in confidence and should not be disclosed
to others unless so disclosed in confidence with the per-
mis sion of Remington Rand Univac, Division of Sperry Rand
Corporation, being first obtained
u This copy is numbered
and is so registered in your name in our records. The
document is not to be reproduced or duplicated without
express perll1ission in writing from a duly authorized
representative of the Sperry Rand Corporation.

®
REMINGTON RAND UNIVAC
DIVISION OF SPERRY RAND CORP.
Philadelphia, Pa.
July 1958
 UCT MAINTENANCE MANUAL

PreliJninary Sections

The purpose of the three sections in this :manual is to fa:miliarize

:maintenance personnel with the physical layout and components of the processor,

and with the printed maintenance aids which accompany the UC T systeITl. As

:more detailed maintenance information becomes available, it will be published

and forwarded to holder s of this ITlanual.

Section 1 contains a physical description of the cOIIlponents used in the

processor and the location of each by means of photographs and illustrations.

In Section 2, the various types of printed maintenance aids, such as drawings

and tables, are described together with the prescribed procedure for their

use. Section 3 contains a description of the various controls and indicators

on the Operator's and Engineer's Panels in the Processor.

 UCT MAINTENA~CE MANUAL

SECTION 1 PHYSICAL DESCRIPTION

Title Page

1. 1 GENERAL .................................................................................................................................................................................................................. . 1-1

1.2 POWER SUPPLY UNIT ....................................................................................................................................................................... 1-1

1. 2. 1 Power Supply Chas sis '........................................................................................................................................ 1-1

1. 2. 2 Clock Driver Chassis '.......................................................................................................................................... 1-1
1. 2. 3 Clock Ou,tput Chassis .......................................................................................................................................... 1-2
1. 2. 4 Storage Drum ...................................................................................................................................................................... 1-2
1. 2~ 5 Bleeder Resistor and Rectifier Panel ........................................................................... 1-2
1. 2. 6 Relay Panel............................................................................................................................................................................... 1-3
1.2 •. 7 Power Control Tray .............................................................................................................................................. 1-3
1. 2. 8 Power Connectors ......................................................................................................................................................... 1-3
1. 2. 9 Alternator and Drive Motor .................................................................................................................... 1-3
1. 2. 10 Blower Systern,................................................................................................................................................................. 1-3

1.3 PACKAGE AREA ............................................................................................................................................................................................... 1-3

1. 3. 1 Package and Connector .............................................................. ~ .................................................................... 1-4

1. 3. 2 Power Wiring .......................................................................................................................................................................' 1-6

L 3. 2. 1 D.C ................................................................................................................................................................ 1-6

1. 3. 2. 2 Power and Blocking Pulses ........................................................................... 1-9
L 3. 2 .. 3 Bu,sbars ...................................................................................................................................................... 1-9
L 3. 2. 4 Shelf-Edge C onnectors .............................................................................................. 1-10

Signal Wiring .......................................................................................................................................................................... 1-10

SECTION 2 PRINTED MAINTENANCE AIDS

2. 1 GENERAL ........................................................................................................................................................................................................................... 2-1

2.2 LOGIC DIAGRAMS ................................................................................................................................................................................ . 2-1

2.3 TROUBLESHOO'TING LAYOUTS ................................................................................................................................ 2-2

2.4 SHELF WIRING CHARTS .............................................................................................................................................................. 2-4

2. 5 SIGNAL FLOW AND WIRING CONNECTIONS .................................................................................. 2-6

2.6 PACKAGE SCHEMATICS AND PICTORIALS ....................................................................................... 2-7

2.7 MOUNTING BOARDS AND ADDRESSING SYSTEM 2-8

 SECTION 3 CONTROL PANELS

Title Page

3. 1 GENERAL ..................................................................................................................................................................................................................... 3-1

3.2 ENGINEERS PANEL ................................................................................................................................................................................. 3-1

3. 2. 1 Pushbuttons and Indicator s .................................................................................................................... 3-1

3. 2. 2 Vol tage Monitor ............................................................................................................................................................ 3 - 2

3.3 OPERATORS PANEL ............................................................................................................................................................................. 3-5

3. 4 KEYBOARD .............................................................................................................................................................................................................. 3-7

APPENDIX
 LIST OF ILLUSTRA TrONS

Figure Title Page

1-1 General Wiring Exarrlple ........................................................................................................................................... 1- 3

1-2a Power Supply Unit, Rear View (Early ModelL....................................................... 1-3
1-2b Power Supply Unit, Rear View (Late ModelL........................................................... 1-3
1-3a Power Supply Unit, Front View (Early Model} ...................................................... 1-3
1-3b Power Supply Unit, Front View (Late ModelL ................................:........................ 1-3
1-4 Clock Driver Chassis (Block Diagrarrl) ............................................................................. 1-3
1-5 Bleeder Resistor and Rectifier Board .................................................................................... 1-4
1-6 Relay Box ............................................................................................................................................................................................. 1-4
1-7 Power Control Tray ....................................................................................................................................................... 1-4
1-8 Processor Package Bays~ Backboard View ................................................................... 1-6
1-9 Fixed Bay Layout, Shelves A-L ............................................................................................................ 1-7
1-10 Hinged Bay Layout~ Shelves M-Z ..................................................................................................... 1-7
1-11 Package Pictorial............................................................................................................................................................... 1-7
1-12 Bus bar Suppl y Systerrl................................................................................................................................................. 1-10

2-1 Logic and Troubleshooting Symbols ................................................................................................. 2-3

2-2 Gate and Arrlplifier Symbols .......................................................................................................................... _ 2-3
2-3 Troubleshooting Layout Example ......................................................................................................... 2-5
2-4 Shelf Wiring Chart ................................................................................................................................................................. 2-6
2-5 Signal Flow Exarrlple ....................................................................................................................................................... 2-6
2-6 Package Schematic Exarrlple ............................................................................................................................ 2-7

3-1 Engineers Panel ..................................................................................................................................................................... 3-5

3-2 Operators Panel ...................................................................................................................................................................... 3-8
3-3 Keyboard..................................................................................................................................................................................................... 3 - 8

LIST OF TABLES

Table Title Page

1-1 Packages Used in the UCT ................................................................................................................................ 1-7

Packages Used in the UCT (Continued) .................................................................................... 1-8

2-1 UCT Color Code ..................................................................................................................................................................... 2-5

3-1 Vol tage Monitor Setting s ........................................................................................................................................ 3 - 3

A-I UCT Processor Relays ................................................................................................................................................ A-I

A-2 UCT Processor Barrier Strips ................................................................................................................ A-4
A-3 UCT Processor Seleniurrl Rectifiers ........................................................................................... A-8
 SECTION ONE

PHYSICAL DESCRIPTION

1.1 GENERAL
The two sections of the DC T Processor are designated as the power supply
unit and the package area" The power supply unit contains the power supplies,
motors, storage drum~ blower system a control panels and other miscellaneous
components. The package area consists of two bays, one fixed and one hinged,
that contain the printed circuit packages ..

The distribution of the power supply voltage to the bays and input-output
devices is accomplished by means of barrier strips, connectors, and busbars.
However, no set pattern tor dist~ibuti~n of power exists, as can be seen in
Figure 1-1 which illustrates several of t~e many variations in the distribution
of the power supply voltages.

1. 2 P'OWER SUPPLY UNIT

The power supply unit (Figures 1-2 and 1-3) contains 17 power supply
chassis which p~ovide all of the dc voltages for the processor and most of the
dc voltages for the input-output units.. Figures 1-2 and 1-3 show the physical
layout of these chassis The unit also houses the barrier strips and connectors
a

which distribute the voltages~ In later models of the UCT the power supplies
are grouped together, as shown in Figures l-2b and 1-3b~ resulting in fewer
power supply chassis o

The storage drum~ clock chassis, control panels~ blower, motors and
alternator are all contained within the power supply unit. Each item contained
in the power supply unit is shown in Figures 1-2 and 1-3 and explained in the
following paragraphs.. The control panels are described in section 3.

1. 2 .. 1
Power Supply Chassis
The power supply chassis (Figures 1-2 and 1-3) provide the processor
with dc voltage. Each power supply chassis has a barrier strip attached to it
to serve as a distribution point. A harrier strip consists of a set of terrninals
on a bakelite board. The number of terminals on each barrier strip varies
from 2 to 12. Each chassis is pointed out in Figures 1-2 and 1-3 along with
the barrier strip that serves it.. The distribution of the power supply voltages
is shown in engineering drawings DX805$ 632 or DX805 633 supplied with the
j

system.

1. 2. 2 Clock Driver Chas sis

j

The clock driver chassis (Figure 1- 2 a ) contains the various components

necessary to shape and amplify a sine wave. Test terminals, tuning and control
devices are located on the left edge of the chassis (see Figure 1-4). The top
edge contains three coax connectors and a 24 terminal connector plug.

1-1
 The clock driver chassis receives a sine wave from the drum) aIT1plifies
and shapes it, and then produces an output which consists of two sine waves
equal in all1plitude but 180 degrees out of phase. The two sine waves then
drive the clock output chassis. A complete circuit analysis of this chassis is
contained in section 6 of the UCT Processor Manual. The wiring and circuit
schematic of the clock driver chassis are shown in Engineering Drawings
DX601, 163 and DX808, 412.

1. 2. 3 Clock Output Chassis

The clock output chassis (Figure .1-2a ) receives as input the two sine
wave outputs of the driver chassis. The output chassis receives the two sine
waves, increases their power, and produces A and B phase sine waves. A
single tuning shaft, for the tank circuit of the output chassis) is on the top edge
of the chassis. The output transformer is above the chassis.

The complete circuit analysis of this chassis is !.contained in section 6 of

the Processor Manual. Engineering drawings show the complete circuitry and
wiring of the output chassis.

1. 2. 4 Storage Drum
The storage drum (Figure 1-2a) is sealed in a container located next to
the clock driver chassis. The container is filled with helium at a pressure of
one third of an atmosphere. The container is bolted to a mounting plate which
contains 27 connector plugs set in two circles. The drum-to-processor wiring
drawing DX805 7 754 shows the drull1 plate and indicates the use of each connector
plug.

1. 2. 5 Bleeder Re~istor and Rectifier Panel

The bleeder resistor and rectifier panel (Figure 1-5) contain resistors,
potentiorr'leters~ a ITleter relay (Relay 31), three pyrometers, selenium rec-.
tifiers, and mounting boards.

Seven of the bleeder resistors have adjustable sliders and all are con-
nected to the output of one or more power supply chassis. The resistors are
included in the dc power distribution drawing.

The selenium rectifiers are used in power control circuits. Table A-3 of
the appendix lists the circuits and drawings in which the sixteen rectifiers are
used.

Two of the three potentiometers on this panel are used in the low clock
alarm circuit. Resistors RIO (Figure 1-5, 16) a ..~d R11 (Figure 1-5 i 15) are
initial setup adjustments for calibrating the voltage monitor-to-clock signals.
Resistor R12 (Figure 1-5, 17) regulates the arrlplitude of the clock output
signals.

The meter relay (Relay 31) is used to detect for abnormal head-to-drum
spacing and the three pyrorrleters, (R20, R2l~ R22) are used to detect the over-

1-2
heating of any of the drum components.

The three mounting boards ll MBl, MB2, and MB1211 (Figure 1-5, items
14, 12, 13 respectively) are used to mount the rem.aining components required
for the circuitry of this panel (See section 2.70' Mounting Boards and Address-
ing System). The wiring of this panel is shown in the Bleeder Resistor Panel
drawing, DX808, 080.

10 20 6 Relay Panel
The relay panel (Figure 1-6) contains 21 relays and two connector plugs
(CP.54 and CP55, items number 22 and 23 in Figure 1-6). The wiring of this
panel is shown in the Relay Box drawing. The name and number of each relay
is listed in Table A-I in the appendix.

1. 2. 7 Power Control Tray

The power control tray (Figure 1-7) contains three transformers, six re-
lays, a barrier strip, and two mounting boards (See section 2 .. 7).

Transformers T2 and T3 (Figure 1-7, items 5 and 6 respectively) are

part of the drum alternator circuit and transformer T4 (Figure 1-7 J lZ) is the
clock filament trans form.e r.

The. six relays and the one barrier strip are listed by number J name,
and location in the appendix.

The mounting boards, MBI3, and MBl4 (Figure 1-7, Z and 3) are used to
mount miscellaneous circuitry components.

1" 2.8 Power Connectors

Three connectors, shown in figure I-2a, are used to supply power to the
input-output devices" Each connector is colored to match the connector mounted
in the particular device it supplieso Green connector socket CS53 (Figure l-Za)
supplies the Card Reader .. Yellow connector CSS1 (Figure 1-2a) supplies power
to the High Speed Printer e Blue connector CS5l (Figure 1- 2 a ) supplies the
Read Punch.. The wiring of each connector is shown in the Connector Wiring
drawings supplied with the co:mputer.

L 2 .. 9 Alternator and Drive Motor

The alternator drive :motor (Figure 1-2a) drives the alternator to supply
power to the dru:m motor. The alternator is located directly behind the drive
motor.

1. 2 .. 10 Blower System
The main blower (Figure l-Za)lI driven by the blower motor (Figure 1-
3a), circulates air around the packages. Two smaller blower units are used to
circulate air about the storage drum and a fourth small unit circulates air
through the clock chassis ..

Ie 3 PACKAGE AREA
The fixed bay (Figure 1-8, 1) of the package area contains most of the

1.3
 FIGURE 1-5 BLEEDER RESISTOR AND RECTIFIER BOARD

1. R3

2. R4

3. RI

4. R9

5. R5

6. R6

7. R2

B. RB

9. R7

10. Selenium Rectifier (SRI to SRB)

11. Selenium Rectifier (SR9 to SR16)

12. MBZ

13. MB1Z

14. MB1

15. R11

16. RIO

17. RIZ
 METER
RELAY PYRO,
31

PYRO 3 PYRO 2

Figure 1-5 Bleeder Resistor and Rectifier Board

 FIGURE 1-6 RELAY BOX

1. Relay 23 Fast Reader Off Normal

2. Relay 28 Input Ready

3. Relay 14 DC Fault

4. Relay 13 AC Fault

5. Relay 3 Blower Holdover

6. Relay 30 Memory Wr,ite Inhibit

7. Relay 29

8. Relay 32 Clock Alarm

9. Relay 33 Drum Alarm

10. Relay 24 Start

lL Relay 19 General Clear

12. Relay 10 DC Ready

13. Relay 8 Drum. Ready

14. Relay 18 -DC Alarm

15. Relay 17 . tDC Alarm

, ~'.;..w

Relay 16 AC Alarm

Relay 1_~ St:a~d.by Alarm

18 .. Relay 5 Air Flow and Air Temp.

19. Relay 20 Proces Bor Off Normal

20. Relay 21 High Speed Printer Off Normal

21. Relay 22 Read Punch Off Normal

22. Conn.ector CP54.

23. Connector CP55

 3266-1

Figure 1-6 Relay Box

 FIGURE 1-7 POWER CONTROL TRAY

1. +45V Power Supply

2. MB13

3. MB14

4. Relay 34 Drum Motor Start

5. T2 prurnAlternator. Circuit

6. T3 Drum AlternatQxCi:r<;:uit

7. Relax 26 Overcurrent +3V

8. Relay 25 Overcurrent -t3V

9. Barrier Strip 33

lO. Relay 7 Drum Relay

-
11. Relay 9 DC Delay (2min.)

12. T4 Filament XFMR

 3267-'

Figure 1-7 Power Control Tray

input-output packages, and the hinged bay (Figure 1-8, 7) contains the pack-
ages of the arithmetic unit.

The bays are connected to the frame of the power supply unit and
positioned back to back so that packages can be replaced v/ithout moving the
hinged bay. The hinged bay can be swung out to expose the backboard wiring
when it becomes ne~essary to check the package connections.

Each bay ~onsists of eleven shelves .of packages. The shel~_es of the
fixed bay are lettered ABC D E F G IiJ. K L (rom top to bottom and the
shelves of the hinged bay are letteredMNPR STY W X ;~l z.

The bays contain busbars, barr1er strips, and connectors to distribute

power and information signals to and ~from the packages. - Each item contained
in the bays is explained in the following paragr:~J~~s.

1. 3. 1 Package an(lConp.ector
Each bay has eleven shelves of packages with each shelf capable of hold-
ing 100 packages. The packages are numbered p.o to 99 from l~ft to right and
are grouped according to functional units. All packages that are used by
Register C are grouped together I all those used by the co:mparator are group-
ed together, etc. Figures 1-9 and 1-10 show both bays with the logical group-
ing and package types indicated. Table 1-1 shows all the package types, their
key positions, and the quantity of each type used in the UCT.

A normal package re,quires at least one shelf space. However, a few

occupy two or more spaces because of the size of the components. These
double types are marked by asterisks in Table 1-1 and by arrows across two
spaces in Figures 1-9 and 1-10. The arrowhead indicates the space where the
package <;qnnector i~ l:.ocated.
~ .. ~ '<:. ;"..

Packages consist of wiring printed on a plastic .board onto which cir-

c uitry components are mounted. Indentic al wiring patterns are printed on both
sides of the board and the component leads are inserted through drilled holes
and dip soldered. The wiring patterns are identical on both sides to insure
reliability of the ~i!c:_u:!ts and connections~ In s~me casesI,lrinted wiring is
supplemented by W'fre Jumpers. -'~.

Each package has 22 possible input-output terminals (44 bifurcated

terminals) along one edge and 10 test terminals along the opposite edge. The
input-output termina~s (Figure 1-11) located on the end of the package that fits
into the package connector, are numbered 1 to 22 .:)n the component side and 31
to 52 on the solder side. Since the wiring on both sides is identical and co:m:mon,
the terminals by pairs are also common. That is, 1 and 31, 2 and 32, are
electrically the sa:me point. Not all of the input-output and test terminals
are used.

The package plugs into a connector that is mounted on the shelf to provide

1-4
connections for the inputs and outputs of the package. The package connector
(Figure 1- 8 J 6) is equipped with tabs· on one s ide an,~ sockets on the oppo site
side. On the side into which the package is inserted t~he socket is a slot with
22 pairs of spring-tension contact points which exert pressure to hold the pack-
age firmly. On the wiring side are 22 pairs of tabs onto which the backboard
wiring is connected.

The tabs at ~he connector are numq,ered the same as the terminals of
the package. E'ach tab of a pair is cornrnon to
the ~ther. tab of the sarne pair.
The use of bifurcated contacts permits the conne'ction of two leads to the sarne
printed circuit when necessary.

Viires ~re fitted with tab recep'tacles that fit firrnly onto the tahs. A
slight leverage is required to connect or remove the tab receptacle b . 'Clll the
tab. A special tool is used to grip the tab receptacle when connecting it to a
tab.

Keying In Figure 1-113 terminal position 9 ~ 39 has a slot in place of

the terminals. This indicates the key position of the package. The connector
designed for this type package will have a ridge in position 9, 39 to fit the slot
of the packag~o On the wiring side of the, connector;, tab position 9 J 39 has no
tabso Each packag~ has. a key position to prevent on~ type of package being
inserted in a connector designed for another type package. Two or rnore dif-
ferent types of packages rnay be keyed at the sarne position because there are
46 types of packages and'~only 20 key positions, The,; top and bottorn terrninals
positions are not used as key positions. EO',lever" the packages are laid out In
the bays so that package types v-/ith the saITle key are not next to ea~h other.

Test Terminals The test terminals (Figure 1- i 1) are located on the

end opposite the input-output terminals to enable signals to be tested without
swinging the hinged bay open. The test terrninals are numbered 1 to 10 frorn
top to bottomo Wire jumpers connect them to,the component positions. One
package; type CSP uses i~15 test 'terminals instead of the ordinary ten. The
extra five, numbered 11 to 15 are located in another vertical row beside the
first ten test tAYITlinals.

Addressing of Components The COITlpOnents of a package are narne-

ed on the p~ckage circuitry drawing according to their address on the board.
As illustrated ir~ Figtlre 1~11 there are five rows of Inounting positions label-
ed J, KJ' Hi' M., and Nt' The address consists of the initial letter of the com-
ponent (D for diode, etc. L a letter designates a row and a nUInber of the specific
Inounting pos'ition in the rOVil., Thus, a diode mounted on position 3 of row J
would be called DJ3 (Figure 1.-11), The bottom Inounting position for a corn-
panent is not given. The length of the component deterrnines to what row the
bottom connection would be made., The one notation DJ3 is sufficient to locate
the c oITlponent on the board,

A board which contains magnetic cores has fou'r circular (Figure I-II,
 FIGURE 1-8 PROCESSOR PACKAGE BAYS, BACKBOARD VIEW

1. Fixed Bay

2. Shelf Edge Connector

3. Clock Driver Chassis

4. Signal Cable Between Bays

5. Shelf Edge Connector

6. Package Connector

7. Hinged Bay

8. Bypass Capacitor (-+3V to G) (1. 5ufd 200V 10 0/0 )

9. MB9

10. Connector CP72, Signals to and from the Engineer's and Operator's Panel

11. Connector CP71, Signals to and from the Engineer's and Operator I s Panel

12. Connector CP70, Signals to and from the Engineer's and Operator's Panel

13. Barrier Strips (BS16, BS35, BS39)

14. Barrier Strips (BS12, BS36, BS38)

15. Connector (CS73 and CP73), Signals to and from the Engineer's and
Operator's Panel

16. Connector CPB (Dark Blue), Signals to and from Read Punch Unit

17. Connector CPC (Yellow), Signals to and from High Speed Printer

18. Connector CPD (Green), Signals to and from Card Reader

19. Connector CPA (Light Blue), Signals to and from Read Punch Unit

ZO. MBII

21. Busbar Assembly

 3268 -1

Figure 1-8 Proces sor Package Bays, Backboard View

dotted lines) position patterns replacing row H. These four positions are
nUITlbered 1 to 4 on the cOITlponent side of the board. Individual points in a
circular pattern are numbered 1 to 9 in a counterclockwise direction. Com-
ponents mounted in these positions are, with rare exceptions, usually
magnetic cores, which are named Ferractor #1, Ferractor #2, etc.

1. 3. 2 Power Wiring

1. 3. 2. 1 D. c.
All dc voltages are distributed within the package area from barrier
strips. Seven barrier strips. on the end of the fixed bay (Figure 1- 8, 1) and
three in the base of each bay (Figure 1-8, 13 and 14) receive dc voltages
from the power supply chassis. The three in the base also carry control
power to the thermostats and card bay interlocks. The leads from the barrier
strips in the fixed bay are connected directly to the packages in the fixed bay
and to packages in the hinged bay by ITleans of shelf-edge connectors with the
exception of the +3V and -29V distribution, explained below. The same is true
in the distribution of voltages from the barrier strips in the hinged bay. Shelf-
edge connectors are explained in section 1. 3. 2. 4.

1-6
 00 01 02 03 04- 05 Of> 07 08 09 10 11 12 13 14 15·16 17 18 19 20 21 22 23 24 25 26 27 28 2q 30 31 32 33 31- 35 3G 37 38 39 1-0 41 42 43 4-4: 45 46 4-7 f'D 49 50 7
I
I
I

R
I I I I
A I
II
I

I fo--
Non:: i

* THESE PACKAGES ARE \)SED BY SEVERAL I

I
i
GDP eel
LOGICAL GROVPINGS 46E 54E 5GH 55H I pee BPCP PB
i
B 47E ~2G 52H )S-J
4-8 E 53 G 53 H 41 L
** THESE PACKAGES AR£ FOLLOWED BY\~x'l (DELETED FOR ILLUSTRATION
I. Cf\OSSHAiCti LINES I ND ICATE SH IELD
5GD eCI S~D ACI AU AC
2. THESE PAcKAGES ARE FOLLOWf" D BY \\-5 11 (DELETED FOR! LLUSTRAT/ON
c AC1
AC3
AR1 CC1
CC3
GDP
Msr
RAP
RFF-
S~D
WPP
W,/-p
1** *
I

I I
CC1 GDPIAC1 i
Ac1 GD

D I I
SW ITCH BRACKET
I I I ! I
I I

GoDP CCf GOP C.C1 GDP GDP AC1 AC1 ACf AC1 eel AC3 SGD GDP eel eCl eCI GDP GDP eCl eel eel eCI GDP GDP GOP ACI CCI BfP TAP GDP GDP eCI ACi ACI CCf GDP CC.1 e.Cl ACI ACI C;DP GDP ACI GOP eel SWJ2sWI2.I:LCk. ~C1 eel GD

E
** !I **
1+--+- PRI NT-CO DE CHEC K C IRe U ITS -+-----1~.......-+-----1I__-+---+--+___t-_+-_t_--+____+-___t_-+____jr______t__ CA R D READER S H 1FT REG 1ST E R --t-----t-I --t---+_--II__-t---t----t--___t---+----t--t---t----;--+_--II---+--t---t--
I
**
ee1 ACI CCI CDP ACI eel GDP AC1 eel AC1 C;DP ACt ('DP GDP cef Ae1 eel GDP C.C1 ACI eCI GDP AC1 AC3 GDP AC1 AC1 AC3 Act GDP AC3 AR1 AR1 eel ee1 AC3 CC3 AC1 CC3 AC1 AC1 AC3 G.DP CC 3 AC 1 G DP AC3 GC
PRP PRP
F
- PR1NT COM PA RA TO R ---t--~-+--+--+-__II---+---+--+-__I--+---+--+----t--+---+-_'l_~.........__t_-t___-___+__ ** eye LI NGUN IT ** **
-+---t-----j--ptooI------+--t--

GDP TAP GDP TAP TAP GPP TAP TAP ~DP GOP eel ee1 GDP TAP TAP GDP eel GDP eel TAP TAP GDP CDP GDP AC1 Ac1 GDP AC1 AC1 GDP AC1 AC1 AC1 GDP AC1 ACl GDP AC1 AC1 GDP AC1 ACI ACl GDP CC1 AC3 GDP 1\C.1 AC1 GDP eel cc.

G
~-+---+--+--+---+--+- P RI NT DI STR 1B UTa R+---I---t--+---+--t----Jl...-F------1r- P RI NT CO MPA RATOR -t--+l.......-+--t---+----l--+---+---t-----t--t--
I
M EMORY TO PRINT BUFFE R CONTROL
I
**
~-+--~--~-+--~~~~--+-~--~--+--+--~--r--+--~~~-+--+_~--~--~_+--~--~_+--~~--_r--T_~--~~-- -- -- -- -- --
eel G-DP CC1 CC1 GDP TAP CC1 CC 1 GDP CC1 GD? TAP eel TAP rDP ! RFF AM GDP AC~ peG eel eel GoP
PRG PRG PRG PRS PRS ~ PRP PPSA
CC1 GDP eel ref Gj)P
PBC AC1
H I I I
~--+---I---t---t-- PRINT DIS TR I B U TO R. --+-----1~_+--......~--t--t_---t--t--t_- pp I NT CO M PA RA TO R ---+--t-----t--+----t---j----i~ t__-+---+-- SW I TC H BRA eKE T-____j---+-----.,. *
I I
GOP eel GDP eC3 GDP eel AC3 AC1 GDP eel GDP eel BFP AC1 GOP ACl GDP eel GDP CC1 eCI GDP CC1 CC1 GDP CC1 CC1 GDP AC1 CC1 B'P c.p I I
PDR PD R PDR PDR PD? PDR PDR cel C.C1 CC1 SGD GDP

** I I I
J ~~-+-~-~-~-+--+-~--~-~-- READ-PUNCH SHifT REGISTER---4--~~-~-~-+-+-~-~--~-+--+-~~~--r--r--+- ** PRINT COMPARATOR
1 1 1 I I I I I - ----~
I I I I I I I I
C5D CSD CSD CSD CSD CSD CSD (SD CSD (SD PDGD PDGD POGD PDSD PDGD PDGD PDGD PDGD
K ,
~-+--~--~--~-+--~--+---~-+--~--+-~---+--~--r-~---r--~--r-~---r--r-~---+--4---r--- READ-PUNCH SHIFT RE~ISTER ----+-~--_+--_t_--r-___t---r--+-~~-+--r_r--+___t--_+--4_--+__

CSD (SD CSD CSD CSD CSD CSD CSD CSD CSD TCS
L I I I , I
~-+----t---+---+--t----+---+--+--+-----1~-+--- CAR D- REA DE R S H \ FT RE GIST E R ---t--+---+---+--~_+--+----+---+-___j--+___l~~ * ~-~~--~____j--_T--_r--+---t____+-----r-
I I
00 0 f 02 03 04- 0;- Db 07 08 ocr 10 11 12- 13 14 1li 16 17 18 19 20 21 22 23 24 25" 26 27 28 29 30 31 32 33 34- -:;S- 36 37 36 39 10 41 42 43 44 4-~ 46 47 48 49 ~o ~1
 20 2f 22 23 24- 25 26 27 28 2q 30 31 32 I 33 34- 35 3G 37 38 39 4-0 41 42. 4 3 4-4 45 46 4- 7 4-'3 49 5 0 ~1 52 53 54 '35 5 b -5 75'S 6'3 GO 6 1 {; 2 63 rO 1- b 5" Gb (.; 7 b 8 69 70 71 72
--~--~--+---r-~--~I--~--~--~--+-~~~---+--~--~--+---r-~---+--~--4---+---r!1--~:---+---r--~--+---r--1---+---r-I--~;F-F-r--~I--~-R-F-F~-4I---+-R-F-F~~---+-R-F-Fr-~I---+-R-F-Fr-~I---+-R-FF~I--~I~-+I-R-~-r~-41
RAP-S RAP RAF RAP RAP RAP RAP RAF
I I I
-........--+----+---+--1-----+--+--+---+- CARD BU F FER BA N D S 1 AND 2 ----+_-+I_-+--_+-_+-_+----+
I I I
USED BY SEVERAL
;S 46E 54E 50 H 5SH pee. 8PCP
1

GDP CCi
PBC wxp WXP WXP Cc., Wy-p
I
GDP wpp wpp W)(~ TAP
wxp
I
WXP WXP
4-7E 52G 52H :;S-J I I
t8E 53 G 53H 41 L ~-+--4---~-+--1---r--+--~--+-~--~C~RDBUFFER BANDS 1AND 2~--r-_+--4_--r-_+--4_--r-_+--1_--~~
)LLOWED By\~x'l (DE LETEP FoR I\...\...\)S TRATION ILl I
~TE SHIELD
5GD cC1 S~D AC1 AC1 AC, CC3 "DP !WACD(ACD I G DP WACDICOI'WACD AC1 IAC1 GOP AC1 GDP AC1 VlJACD' ec. 3 C.C.3 WACD WAGJ) wtJe,D A C 1
'OLlOW£" D BV "-S" (DELETE.D FO~ ILLUSTRATION
i

;rDP
~ 5r
RAP S~D
RFF
W)(P
WP P 1****
I
I .l.
! !
I +-1
I ! I
i
****
CARD ~UFFER BANDS 1 AND 2 ** ** **1
1 I J !! I L I
CC1 GDP ,AC1 IAct ! !! '
GDPlAC11CC1 !CC11IGDPICC3\'AC1 GDP AC1 I I GDP IAC1 !
SI4DISGD CC1 cel SGD GDP~AC1 '
GDPlcC1 Aei AC3

I I I I I I

I
\

I I i I ** I I I I
- SW ITCH BRACKET I
\ I CARD BUFFER BANDS 1 AND 2 --+--4--+----+--4---1--4
t
I ,i I
fo---t--r---i---i
! c c, co., :c~! G DP G DP GDP ;C~ ec, BfP TAP GDP G DP CC1 I
Ac1 Ac1 eel GDp eel C.C1 AC1 IAC1 GDP GDP AC! GOP eel SWI2 5WI2.r:LC~ t..C1 eCf G.OP ~DP PES eei GDP CC1 I i SGD eCi SGD CCi GDP CC1 AC1 AA1
I CC 3 AM

1 I I
f----+--+--+--~ CA RD READ ER S HI FT REG \ S T E R _ _1----+-1--+---!---f----4--+--+--+--I---+--+--+--+-------+--+---+--+-----'i---+-..,. "* "'-_+--~--r- CA RD BUF' FER BA NDS 1 AND 2 -----+---+-----+---.-.

eCl GDP AC! AC3 GDP ACi AC1 AC3 Ael GDP AC3 AR1 AR1 eel CCi PRP AC-"3 CC3 AC1 CC3 AC1 AC1 AC3 GDP CC3 AC1 GDP AC3 GOP ACl cC1 eei I <::.DP GDP CC1 CC1 CC1 GDP CC1 eC1 GDP eel ACI ACi GDP AC1 GDP CC3 CC1 CC1
PRP

** ** **
eye LI NGUN IT -+---+--t--......---+---+--~_+-_+_-+_--i~-+--_+_-+_--+--+-+_-t__-+-~--+---...,f._-_+--+--+--- CARD ** **
TAP GDP GDP GDP AC1 ACi GDP AC.1 Ac1 GDP ACI ACI AC! GDP ACi ALI GDP AC! AC1 GDP AC1 AC1 AC1 GDP CCl lIe3 GDP ACI ACi GDP CC1 CCi T.b.P TAP CC1 SW'Is- GDP AC3 AC1 CrDP AC1 ('DP Act GDP ACl AC1 GDP Act ,ACI SGD GDP AC1
I

:OMPARATOR+--.~-+---r--+-~---+---+---~~---+­
I
M EM 0 R Y TOP RI NT B U F FER coN T RO L
I
** ** "*
+-~--+-....,..-..,...-+--+----+--+--;---+--+--+-....... - - - - - -
RFF AM GDP AC3' peG eet eel GoP eCI GDP CC1 eet GDP CCf GDP I CC1 ACf GOP IICf ,4Cf AC1 GOP AC' IICf GDP GOP ccf !JCI /lCf ACf (;J)p
pJp PPSA PBC ~c 1 ATP ATP
I I
I
- PR I NT CO M PA RATO R ----+--+---+--+--+--+--1-.
I

.__--+--+-- S WIT C H BRA eKE T---1---+----'~

I I
* * * * ** ** READ-PUNCH ** COl

eel GDP cc1 ee1 GDP cel cel G,DP AC1 eC1
I I 5WI2 CCf G DP CGl GDP AC1 ACf GDP eCl G DP CC1 CC1 C C1 GDP eCI GD P CC 1 GDP
Bf' c.p PDR PDR PDR PDR PDP PDR eel eel CC1 SGD GDP

I I
** - PRINT COMPARATOR
j I I
*' ** ** ** ** **
I I I
PDGD PDGD POGD PD~D PDGD PD~D PDGD PDGD PDG. PDe PPG PDG PDG PDG P DG PDG PDe:, PDq ARS ARS AR'S
I
READ-PUNCH SHIFT RE~1 STER ..
TCS ACDT ACDT AC.DT AC DT ACDT ACDT AC DT A C DT A C DT AC
I I I
- *"1
.......f---+--t---+----+---+-----+---+--+----..-+---+--f----+---t----+--4---4--+---i---l---l-----jl---I---+---+--1- REA D- PUN CH :) HI F T R E(
J L I
20 21 22 23 24 2~ 2b 27 26 28 30 31 32 33 34- ~5 3b 37 36 3'7 10 41 42 43 44 4-~ 46 47 48 4'7 ~O 5"1 5"2 S-3 51- 55 56 57 58 '5Cf fO 61 62 1&3 G4 ('5 06 G7 68 G9 70 71 72
+'3 49 50 :;-152 53 54 55 5b 576869 GO 6 1 62 63 01- 65 sG (;7 (;8 69 70 71 72 73 74 7S- 76 17 78 79 80 8 1 182 83 84 85 86 87 138189 90 91 92 93 94 95196.97 98 99
---r--~--;---+---"~-
I RFF I R FF I R FF I R FF I RFF I R FF I RFfl I !RFt:" I RFF I RfF I R'FT I I?FF I R FF
R~P
I I RFF I R FF
RAr:
I RFF
RAP-S RAP RAP RAP RAP RAP RAP RA P-S RAP RA P RAP RAP-S R-AP RAP

I I I I A

4_--+--+-----4---!---+----+--+--+ PRI NT 8 U F FER 8 AN D5 1 AND 2 --t--t---+--+----i--t---t---t-~
I
GDP eCI
P8C i

I
wxp wxp WXP Ce.1 INX~ GDP Wpp Wpp 'NX~ TAP WXp WXP WXP 5T,~P GDP C. C-1 PBC P]5G WXP WXF WXP WACO WXP
I
WACD C C 3 WACD WXP WACD WXP WXP WfP
I I I I B
--~---+----+---+---+---r--+CARDBUFFER BANDS 1AND 24_--~_+--~--~_+--~--+_~--~--+_~ __~--+_~--_+_-+_~-_+--4_--~_+_ P~\\NT BUFFER BANDS 1 AND 2 -
I I I
S ~D II: AC1 AC1 ACl lee 3 GDP jWACD WACO G DP . WACD[ CC.3 WAeD AC1
I IACi GDP AC1 GDP AC1 INACD CC 3 CC3 WACP WACJ) WILD Act ACi GDP AC.1 GDP ACI ecl AC1 CC~ WACD WAcP CC3 eCf G,DP AC1 AC1 AC1 AC1 WACD WAC.D CC1 CC3 CC.f
1
CC1 1AC1 AC1 AC1 AC.1

I****! **** ** ** 1+ "k c

i'

i I
1

,
: I,
! :

i
II

J
I
i i iI
! , I
1

****
CARD BUFFER BAI'~DS 1 AND 2. -l--+---+--+----+I--+--+----+--+-'--+-+---+---i.....--+--+---If---+--+---+---+ PRINT BUFFER BANDS 1 AND 2
J
I
I
-
GDPiAC1 IAc1 GDP!IAC1!CC1ICC1'IGDP'ICC3!\ACl GDP AC1 GDP AC1 SGOISGD CC1 cel SGD GDP'ACl GDPicC1 AC11AC3 SGD GDP AC.1 cei G,DP AC.1 GPP A(.1 GDP,CC1 G;DPAC1 ~DP AC1 QDP CC1 GDP!ICC1 SGtD AC1 GDP cel GDP CC1 GOP

I' I I 1* *1 I I I o
I 1 CARD BUFFER BAINDS 1 AND 2 PRINT BUFFER BANDS 1 AND 2

rLC" t>.C1 CC I GDP <:;DP PES

CC1 GDP eel SGD eCl SGD I eel ~DP eel AC~ AA1 CC3 AA1 AAI AAI GDP eCI GDP AC1 GDP AC1 GDP CC1 GDP ACI GDP ACl ACl GDP AC1 Ae3 CC3 C,DP AC1 ACl GDP I AC3 AC.1 GDP AC~
I
I E
w-_+--t---t--- CA R0 8 UFFER BAND S 1 AND 2
*" ------t---+----+--H PRINT BUFFER BANDS 1AND 2
I
AC1 GDP AC3 GDP AC1 ee1 eC1 GDP GDP! eel eel CC1 GDP CC1 eel GDP CC1 AC1 AC1 GDP AC1 GDP CC?, CC1 CC1 GDPI ee I CCI G DP C03 GDP ACl AC1 AC1 CC1 AC.3 <::;DP p~s- GDP 4DP ACI ACI f>-c..f AC1 ACl GDP C,DP CC1 eCf eel
i
F
**
--~~4---~-4--~--4---~-4--~--+---~-+--~--+---~-+--~--+--4---+--~--+-----
I
** ** CARD (\EADER CONTROL
, ** ** **
AC1 GDP CC1 eCl H.P TAP CC1 Sw!s- GDP AC3 AC1 GDP AC1 <;'DP AC1 GDP ACl AC1 GDP AC1 ACl SGD GDP ACI GDP AC1 AC1 GDP AC1 AC1 GDP AC1 AC3 AC1 SG.D AC1 GDP AC1 AC1 AC1 GDP ACf CC1 GDP IAC1 AC1 GDP AC1 5GD AC' CDP
I
G
** * "* ~--~-4---+--~--~--+----'r--~--+---+-~~--------+--~--1---+---r-~---+--~--1---PRINT CONTROL **
CCf GDP I CC-I AC f GOP /lCI ACf GOP Gf)? cell7Cl /lCf ACt CDP Act GDP /lei CDPllcl C(3 /tCI AC1 CDP eel (JC-1 GDP Ac!.1 GDP C(H AC1 Ac'$ GDP TAP Act CC 1
AC1 ATP ATP PFDA
I H
* * * * ** **
** R£AD-PUNCH CONTRoL **
~---+--~--1---+---r-~---+--~--4---+---r-~--~_.---r-- ** PRI NT CONTROL -+---+-_..tI

CC1 SGD GDP

5WI2 cel GDP CGl GDP AC1 ACf GOP eCI GlDP CC1 eCl CC1 GDP eCI GDP cel ~DP CC1 eel I GDP eel eel GDP TAP TAP TAP <;PP ACI GDP GOP CC3 GDP eel AC3 GDP CC1 GDP

J
* ** ** ** ** READ - PU~~H COUNTERS *"* "* "* ** -
I l I
I I I

PDGD PDG, PDe poe; PD~ PDG PDG PDG PDG PDq PDG ARS ARS ARS ARS AP,S ARS ARS AR'S ARS ARS ARS ARS
I I I K
READ-PUNCH SHIFT REGISTER
I I I I
I I I I
CRG ACDT A eDT I Ae-DT AC DT ACDT /-\CDT ACDT ACDT ACDT ACDT ACDT ACDT ACDT ACDT AC-DT ACDT ACDr ACPT ACDr ACDT ACDT ACDT ACDr
I I I L
,---,.-t---+---+---t--t---+--t---t--t---t----i--+--+---+---t--t--__t_ REA D-P UN CH SHI F T REG \ST E R
I I I I I I
48 4cr LJO :71 52 5'"3 5'+ 55 56 57 58 5"Cj GO 61 62 163 104 ('5 bb (;7 68 (;9 70 71 72 73 74 7S- 76 77 78 7Cf so [51 82 '03 84 85 86 87 88 89' 9cJ all '1;2 93 94 ~~ 96 97 99 79

Figure 1-9 Fixed Bay Layout, Shelves A-L

 00 O~ 02- 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 21- 25" 2r;; 2-7 128 29 30 31 32 33 34 35 36 37 38 39 to 41 42- 43 44- 45 46 47 48 4q 5"0 J;)

I I I I I I I
RPF R!=F R!=F R/=F
I RF~
% I<.FF RFF RFF RFF RFF I RFF RFF

~
RAP RFF R FF R f=F
/<.AP RAP RAP RAP RAP RAP RAP RA P RAP RAP RAP RAP RAP
I RAP
M I I I I I I I
~
I
TIMING-BAND READ CIRcurTS FAST-NORMAL READ-WRITE CIRCUITS ~
- - I I I I I I
I I
PBC 8PCP P13C PBC W'AP WXP eel wXP
IGDP wxp
I I
~G11
I
WXP wXP C.C1 WXP GDP WXP WXP WXP wpp MSI Msr MSI I
NISI MS11 W
N ~~ I I I
FAST- NORMAL READ-WRITE C-IRC\JITS

AC1 AC1 ~DP AC1 AC3 CC3 AC3 AC1 C,DP eel Act AC' AC} C.C3 GDP GDP CCI
WACD WACD
CC3 eC1 CC1 GDP
wACD
CC3 cC~
WACO
cei CC1 C.C1
WACD
AA1 cc 1
WACV WN:-D
CC3 CCi GPP CC1 eCI C.C3 ee1 GDP eel GDP eel IGDP ec
WACD WACD WAeD
p I
T1MIN G- BAND READ CIRCUITS FAST - NORMAL READ-WRITE CIRCUITS - ~

-
ACI ACI GDP GDP eCl C.DP AC1 GDP ACf SGD AC1 GDP GDP GDP AC.3 .l\Cl GDP AC3 ACl ACI GDP GDP TAP GDP CC3 GDP CC3 GDP C C1 Acl GDP AO cel GDP CC 1 I GPP AC
ILCR
I I
I
R 1
-* FAST-NORMAL READ-WRITE CIRCU\TS-·~· --- MEMO!

GDP eel GDP eC1 GDP eCI GDP CC1 ACI GDP eel CDP CC1 SGD SGD GDP AC1 ce3 GDP GDP eel SGD SGD CC3 '3GD CC3 SGD SGD SGD SGD SGD SGD AC1 SGD CC3 AC1 GDP cel GDP GDP Acl AC.1 ~DP SGD AC.i AC1 AAI

s
** COMPARATOR ** **
AC1 ACl eel GDP eel GDp ACi GDP eel AC1 GOp AC3 CDP ACi GDP SGD GDP ACI CC3 AC1 ACI ~DP Aei GDP CC3 CC3 AC3 GDP CC3 CC3 AC3 (;iDP CC3 AR1 ACl SGD A R~ GDP AR1 ACi Cel A(
T
SIGN AND CONTROL FLIP-FLOPS -- S BUFFERS -
(C3 AC1 GDP C.C1 ee1 CC3 eCl C<:1 ACI SGD AC1 GOP ACI ACf GDP AC1 SGD GDP CC3 GDP SGD CCI CC3 CC1 GDP AC.1 AC1 GDP ACl ACI ~DP ACI AC1 GoP ACi AR 1 Ak

v
** ** ** ** FUNCTION ENCODER ** ---
eel GDP eel GOP GDP ce1 GDP CC3 GOP eC1 GDP eC3 GDP cel GDP GDP eel GDP c.c 1 CtDP GDP ee1 GDP GDP eel GPP GDP AC1 GDP CC3 GDP GDP CC3
SWI5 SWI2. SWI2
w I
I
-* INSTRUCTION DECODER
"* *
GDP SGl) GDP eel CC-I GDP cei ACi cel GDP CC3 CC1 GOP ACI eel GDP AC3 cel SGD Act eCl AC1 AC1 CC3 CC3 CC3 AC1 GDP AC3 AC3 ACI ACI GDP ACI AC1 CC3 GDP CCl GjDP CC3 AC3 GDP SGD eef eel CCl G[)P CC1 GDP AC
ILC~

x **CyeLi NG
I NTERUPTED OPERATION ** UNIT ** - 'f<
.---
~

- - - - - - - - I
CC3 eel GDP TAP GDP eC1 GDP CC3 AC1 GDP Act G;DP AC1 GDPiAC1 GDP eCI GDP AC1 GDP C.C3 ~DP ACI GDP CC3 GDP AC1 ACt AC1 Act AC1 Aet CiDP A(
$P5
y
** ** **
MULTIPLIER QUOTIE.NT COUNTER -
AC1 GDP ACI AR1 ARI AR1 AA1 GDP ACl GDP ACt AR1 ARI ARf AA1 ACI GDP AC1 AI
RDP RDP RDP RoP RDP RDP RDP RDP RDP RDP R.DD
z REGISTER C REGISTER L
J 1
00 o 1 02. 03 04 05" 00 07 08 ocr 10 11 12 13 14 15 16 17 18 1q 20 21 22 23 24 2[; 2~ 27 26 28 3() 31 32 33 34 3S" 36 37 38 3« 40 41 42 43 44 45" 4b 47 48 4-Cf 50 '5
 I
23 24- 2S- 2<,; 2..7 28 29 30 31 32 33 34 35 36 37 38 39 to 41 42- 43 44 45 46 47 49 4q 5"0 ~1 52 53 54 55 5"6 57 56 '59 60
1
61 ('2. G3 64 !~5 06 67 68 Gq 70 71 72 73 74 75

RFF f\FF RFF RFF

I RFF RFF R FF Rr:F
I I I I I
,p ~A P RAP RAP RAP RAP RAP RAP MSP MSP tv1SP MSP tv\SP tv'\SP MSP
I I I I I I I I I I
Ii
FAST-NORMAI~ REAO-WRITE CIRCUlTS MEMORY SELECTION I
I I I I 1
IMSI
I
I I I I M51 MSI MSI MSI I MSI MSI MSI MSI MSI Msr MSI Msr MSI MSI M51 MSI MSI MSJ M51 ~JOTE'.
IGDP WXP
AC1i WXP WX? C.C i WXP GDP WXP wxP WXP wpp

I I *'
:MAL READ-WRITE c. IRCUITS MEMORY SELECTioN
i

I
I

I I
> WACD C:C3 CC1 WAC'D ee4 CC1 C.C1
WACD
AA1 CC1
WAC'V Wff;D
CC3 CC1 ~D.p CC1
WACD
CC\
WACD
('C3 eel WACD
GDP CC1 GoDP CC1
IGDP CC1 ~DP eCI GO? CC1 I
GDP CC1 CCi t;' DP CC1 GDP CC1 GDP CC1 GDP ** I.

I 2.
FAST - NORMAL READ-WRITE CIRCUITS MEMORY SELECTION

) Ae f SGD AC1 GDP GDP GDP A (,,3 A.C 1 GDP AC3 ACl ACI GDP GDP TAP GPP CC3 CDP C.C3 GDP CC-1 AC1 ClDP AC3 eel GDP CC 1 I GPP AC1 SGD GDP ACl C C1 CCI GDP CC1 eel ~DP CC1 Gi DP AC1 CC1 lIe1
I I
I

- .. ** ** ** **
I
FAS1- NORMA l READ -WR IT Eel RC U IT S _.--- - - MEMORY SELECTION

) CC3 '3GD CC3 SC;D 5C;D £GD SGD SC,D SGD ACI 5GD CC.3 ACf GDP cel GDP GDP Ac1 Ac..i GDP SGD AC.i AC1 AA1 GDP GDP eel GDP GDP CC1 CC1 eel SGO SGD ce3 AC3 GDP GDP eel I CCi
I
I
ARATOR ** ** ..
::> SGD GDP ACl CC3 AC1 ACI ~DP ACi GDP CC3 CC3 AC3 C;DP CC3 CC3 AC3 c:;DP CC3 AR1 ACf SGD A R1 GDP AR1 AC. eCI ACI AR1 ACt ACf GDP AC.f ACl GDP AC1 eel AC1 AC1 ACl GDP ARl AC1 ACl GtlP ARI AC1 ~DP ACI AC'I AC1 GD

-FLOPS S BUFFERS REG\STER X

j CC1 GDP AC1 ACl GDP ACI AC1 GDP AC1 ACl GDP AC1 ARI AR1 AR1 ~DP 'SGD AC1 Ac1 GDP AC1 AR1 A R1 ARI GDP AC1 ACI GDP AC1 CC1 £GD AR1 AR1 AR1 GDP AC.l GDP GDi

I I
REGiSTER A
i I r

P CC3 G, DP eel G.OP GDP cel GDP CCI C.DP CDP Cc..1 GDP GDP eel GPP GDP AC.t GDP eC3 GOP GDP CC3 AC 1 ACl ~DP ACl GD!

iI
INSTRUCTION DECODER
I
**
1 CC:3 CC3 CC3 AC1 GDP AC3 AC3 AC1 ACI ~DP ACI ACI eC3
ILC.R
GDP eel GDP CC3 AC3 GDP sGD cef ee, eCi GDP CC1 GDP ACI GDP ee, Ci DP eel GDP AC3 <4DP CC3 eel AC3 CC3 AC3 eC3 GDP eCl eel GDP AC3 eC3 CC} ee1 C;DP AC1 AC ~

~
** Cyell NG UNIT
J
** ~ STATIC REGISTER
I

I GDP ACI GDP AC1 GDPi AC1 GDP eCI GOP ACI GDP C.C3 GDP AC1 GDP CC] GDP AC1 ACl ACI ACI AC1 AC1 GDP ACl AR1 ACI A R1 AA1 A PI GOP Act Alii AC1 ARI AC1 GDP AAI ARI A R1 ACt GDP AM AC1 AR1 AR1 GDP

1** ** **
MULTIPLIER QUOTIENT COUNTER REGISTER C
I

AC1 GDP ACI ARI ARI AR1 AAI GDP ACI GDP ACI ARI ARI AR1 AA1 AC1 GDP Act AR1 ARI ARI GDP ACI GDP AC1 AR1 ARt AR1 AAf

REGISTER L
I I I

~ 23 24 2£ Qtf:. 27 28 2,.q 30 31 32 33 34 35" 3~ 37 38 3'1 40 41 42 43 44 4;- 4b 47 48 4-'r '50 5"i 52 53 54 55" :;-6 57 58 Y1 ~O 61 62- 63 64 65 66 67 68 6 (1 70 71 72 73 74 75
 49 4'1 5"0 ':J1 52. 53 54 55 56 57 58 59 60 1 61 "2 63 64- 05 <;6 67 68 0q 170 71 72 73 74 75 76 77 781 7'1 80 81 82 83 64 85 86 87 88 89 I
90 q i q2 Cj3 Cf4 Cf5 96 97 q~ q9
I I 1 I I I :
MSP MSP )v1SP MSP IY\SP W\SP MSP I

I I I I I M
MEMORY SELECTION I I
I
MSliMSI MSI I MSI MSI MSI Msr MSI Msr MSI \ MSI MSI MSI MSI MSI M51 MSI MSI ~JOTE .
I
*THESE PACKAGE.S ARE USED BY SEVERAL
I LOGICAL GROUPINGS C4N 15f\ 3W 37X N
ME~ORY SELECTioN Cfw 76X
lOW
** THESE PACKAGES ARE. FOLLOWED BY"-X' (DELETED FOR ILLUSTRATION)
GDP CC1 IGDP eel GDP CC1 GDP eC1 GDP CC1 CC1 GDP eel GDP CC1 GlDP cc~ Gt DP I. CROSSHATCH LIN ES INDICATE SH IE LD
2. tHESE ~AC<AGES AR:E FOLLOWED 8Y"-SIf(DELETED FOR 1LLVSTRATIC1IV) p
I MEMORY SELECTION AC1 AR1 C C.1 G,DP RAP SCiD wxp
,

AC3 CC3 MsI RFF wpp

GDP eel ~DP ACl SGD GDP ACI CC1 eCl GDP CC1 eCl G,DP CC1 ~j)P AC1 CC1 ACl
I
I
R
I
MEMORY SELECTION ** ** ** ** I

C;DP GDP eel GDP G DP CC1 eCl eel SGD SGD CC3 AC3 GDP C,DP eel I CC1 I CC1 SGD SGD CC3 CC3 eC1 eel GDP cDP AC3 GDP cel eCl SGD e.C3

I I i
.. s
M 8U~FERS

AR1 ACt eCl Act AR~ ACt ACt GDP ACt ACt GDP AC1 eel AC1 ACt ACI GDP AR1 AC1 ACt G1W ARl AC1 ~l>P Act AC1 AC1 GDP GDP AC1 A R~ AR1 ARi
ClDP cel AC 1 GDP
T
REGISTER X
I

GDP ACl ARl AR1 ARl ~DP SGD AC1 AC1 4DP AC1 AR1 A R1 ARI GDP ACl AC1 CDP AC1 CC1 ~~D ARl ARl AR1 GDP AC.l GDP GDP At 1 i ACl Acl AC1 AR 1 AP1 A R1 GDP S~D AC1 ACl AC1 GDP CC1 cC1 AC1 ACl

I v
i
REGISTER A
I
I
! AC1 ACI CiDP ACl GDP AC1 I AC1 GDP ACI CC1 GDP CC1 GDP CC1 GDP eCI GDp ce1 GDP CC1

I I
I I w
!

**
... QUI NARY ADDER

GDP eel GDP AC1 GDP CC1 qDP CC1 ~DP AC3 GlOP CC3 cct AC3 CC3 AC3 (C3 GDP CC1 CCl GDP AC?> CC3 CC3 eel GDP AC1 ACt ACt GDP CC1
lLCR
x
STATIC REGISTER *
GOP Act AR1 AC1 A R1 AA 1 A R1 GOP AC1 AM AC1 ARt AC.1 GDP AAI AR1 A R1 AC1 GDP AA1 ACl AR1 AI<1 GDP ARt AC1 GDP AR1 AR1 AR1 (ipp

y
I
REGISTER C

AC1 GDP AC.1 AR1 AR1 ARl GDP ACf GDP AC1 AR1 ARI AR1 AAf
z
5TER L -
1 1

48 4-cr 50 5"i 52 53 54 55" t>6 57 58 5"Cf GO b1 62 ('3 64 65 66 67 68 6 (1 70 71 72 73 74 7§ 76 77 78 7Cf 80 81 82- 83 84 85 88 87 68 89 qo 9 1 'J2 Cf3 <11 95" q6 q7 q8 9'1
Figure 1-10 Hinged Bay Layout, Shelves M-Z 315'7
 INPUT-OUTPUT FERRACTOR
TERMINALS LOCATION

TT1
o 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SIGNAL COLUMN '\
00 00000000000

--
J
TT2
TERM SIGNAL OR VOLTAGE ~

o 1.31 1 31 BLOCKING PULSE 1

2.32 2 32
TT3
o DIODE-DJ3 3.33 3 33

--
4.34 4 34 -29 VOLTS 1
TT4
o 5.35 5 35 GROUND
6.36 6 36
TT5
7.37 7 37

--
8.38 8 38 OUTPUT 1
K
9.39 9 39
10.40 10 40

o ,_, 2 ~ 3 ,_,J ,_ 4 ;.: ....

11.41 ". 41

--
r.... (
\ I I
"-,I \ ( I ,_ C,~I t!) 12.42 12 42
... j
.... -,
:-" ,_ i",
'-..../
,. . . . ., 1'-, t_.1 0; (51 (j)
.... ./ ' , .......' \._1 '- . . . '_..I _I 13,43 13 43
14,44 14 44
00000000000 15,45 15 45

--
16,46 16 46 INPUT 1

17.47 17 47 POWER PULSE 1

I,... ~
~ ij
TT7
0 "- "- 18,48 18 48
~ ~
~ U)
19,49 19 49
I~} rri~
~

TT8 3:
0 ~
N
;:::. 20,50 20 50

TT9 21,51 21 51
0 _ 22,52 22 52 DIODE IN PUT 1
,
N o 00000000000
T~~EST
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 NOTE:
THE SHADED AREA ON ALL DIODES
TERMINAL INDICATES THE ANODE.

3236

Figure 1-11 Package Pictorial

 TABLE 1-1. Packages Used in the UCT

Package Key
De s ignation Type of Package Position Quantity

AAI Single power amplifier 7,37 21

ACl-S Single power all1plifier, complementer 9,39 274
ACI-X Special single power amplifier,
Complementer 21,51
AC3-S Double .power amplifier, c oll1plementer 12,42 35
ACDT-II* Actuator column driver 5,35 23
AR1-S Arithmetic register 3,33 47
ARS* Tower punch actuator row switch 6»36 12
ATP* Actuator transistor 13,43 2
BFP Bit filter
,,' . '. ,":', ":'- "'I."
13,_.43 2
BPCP* By-?as s c~paci~?r:. _, .' .. 14,44
CCl-S Single "power c ornple'rnenier 11,41 223
CCI-X Spec ial Single power c omplell1enter 2,32
CC3-S Double power complementer 8,38 62
CGDT* Clear generator driver tower 14,44 1
CGT* Clear generator tower 13,43 1
CRG* Column reset generator 13,43 1
CSD>:C Capacitor sense driver 21, 51 32
CSGP Capacitor storage gating 13,43 4
CSP-II Capacitor storage 14,44 50
GDP-S Gating diode 10,40 322
ILCR* Indicator light, choke 13,43 4
MSI-S-II Head switch driver 4,34 20
MSP-II* Matrix selector position 29 32 7
PBC Probe Clear 13,43 8
PCG PC generator 13,43 1
PDG Punch Information distribution 14,44 10
PDGD-II* Punch distribution gate driver 20,50 8
PDR-II* Print drum read amplifier 14,44 7
PDSA** Print drum sprocket amplifier 13,43 1
PES* Printer noise suppres sor 18,48
PFDA* III PCl.per feed drum amplifier 13,43 1
PRG Print gate 13,43 3
PRP* Print sample 19,49 3
PRS Print set 14,44 2
RAP-S-IV* Read amplifier 16,46 31
RDD-II Register display driver 13,43 1
RDP Register display 14,44 10
RFF·-S Read amplifier flip-flop 17,47 32
SGD-S Special gating diode 13,43 45
SPS Sprocket shaper 14,44 1
Package Key
Designation Type of Package Position Quantity

S·W12 Switch input circuits to :mag. a:mps. 14,44 4

SW15~~ Switch input circuits to :mag. a:mps. 13,43 1
TAD Tower actuator diode 7,37 30
TAP Trans istor a:mplifier 18,48 18
TCS* Tower ca:m synchronizer 13,43 1
TSD Tower §'ensing diode 20,50 60
WACD Write a:mplifier and cornplernenter drive 20,50 26
WPP-S-II -W:rite pedestal 13,43 3
WXP-S-II* Write transfor:mer 15,45 26

* Double Shelf Space Required

~o:( Triple Shelf Space Required
 The + 3V and -29V are distributed to all magnetic am.plifier packages
by TI1eans of busbars. The barrier strip leads are connected to horizontal
busbars between the shelves (Figure 1-12). The package leads are connect-
ed to tabs on the busbar. The busbars are explained in section 1. 3.2. 3.

1. 3. 2. 2Power and Blocking Pulses

The clock circuit develops A- and B- phase pulses which are sent to
every magnetic amplifier package. The clock output transformer is connect-
ed directly to the vertical busbars in the power supply section which in turn
are connected to the vertical busbars of the hinged and fixed bays (Figure 1-12)
and the horizontal busbars between the shelves. The A- and B- phase block-
ing pulses are supplied to the horizontal busbar from a transformer mounted
on the shelves at the end of each busbar assembly. The A- and B-phase
power pulses enter the transformer and are stepped down to the blocking
pulse level.

1.3.2.3 Busbars
There are five busbar assemblies (Figure 1-8~ 21) mounted in each bay
between the shelves to supply voltage, power pulse 9 blocking pulse, and ground
connections to the packages.

The top shelf of each bay does not require busbar connections so the first
bus bar assembly in the fixed bay is between shelves Band C and the first bus-
bar assembly in the hinged bay is between shelves Nand P. Each busbar
assembly is identified by the shelves it feeds. Thus, B~C would be the top
busbar assembly in the fixed bay and N-P the top busbar assembly in the hinged
bay. The five bus bar assemblies in the fixed bay are: B-C, D-E, F-G, H-J,
K-L; and in the hinged bay: N-P, R-S, T- V, W -X, and Y-z.

Seven busbars are mounted in each busbar asserrlbly with spacers and
insulators. The busbars are made of brass coated with iridite, the spacers of
brass and the insulators of Teflon and Mylar.

One edge of the horizontal busbars is formed into tabs identical to the tabs
on the package connector to which the package wiring is connected. The tabs of
the busbars are not num,bered or lettered in _any v..:ay. The connections from the
packages are made to the nearest available tab.

The busbars are numbered one thru seven from top to bottolTI o Busbar 1
carries +3 volt dc, busbar 2 carries the B-phase blocking pulses; busbar 3
carries the A-phase power pulses; busbar 4 is ground; busbar 5 carries the B-
phase power pulses; busbar 6 carries the A-pha.3e blocking pulses; and bus bar
7 carries -29 volts de.

The horizontal busbar assemblies mounted between the shelves are con-
nected to vertical busbar assemblies on the end of each bay. The vertical busbar
assemblies supply the horizontal bus bar with the required voltages and pulses.
The \ilertical busbar assemblies consist of five iridite coated brass busbars
clamped together with spacers and insulators.
 + 3 VO Ln. G E:' DC

BLDCKIN6 PUL.$E B

l I
POWER PULSE A

I
GROUND(F'RAME GROUND}

I
POWER PULSE B
1
BLOCKI~G PuLSE A

I I
•I -29 VOL TA5E DC
I

Ii TR'N5FDR"E~1

'-1r- 'lr-
T
H'NGED
BAY
IXE:O
AY
cniTER

T FIX""
SAY Y r
~"'N'E"
, BAY

CL()CI( OUTPur
TRANSFORMER
I rb

Figure 1-12 Busbar Supply System

 The five busbars of the vertical assemblies s'J.pply+ 3 and -29 volts,
ground e A and B phase power pulses to the horizontal bus bars. The A- and
B- phase blocking pulses are supplied from a transformer mounted on the
shelves at one end of each bus bar assernbly. The A- and B-phase power
pulses enter the tra:;'lsformer and are stepped down to the blocking pulse level.

The vertical busbars a!:'e supplied the A~ and B-phase power pulses
directly from the clock output transformer. The voltages are supplied from
barrier st:~ips in the base of each bay.. The ground bus bar is grounded to the
frame and is also connected to the center tap of the clock output transformer.
Figure 1-12 shows the connections of the vertical and horizontal busbar in
block diagram form.

1. 3.2.4 Shelf-Edge Connectors

The fixed bay contains 9 shelf connectors (Figure 1-8) 2), one on the
end of eac'h. shelf to serve as a connection point for voltages and signal be-
tween bayso Each edge connector has twelve taper pin sock.ets on both sides.
A rnaxiInum of five connectors can be inserted on each shelf givjng a total of
60 possible sockets. Each connector is identified by the shelf letter and its
position in relation to other 'edge connectors. The five on the B shelf would
be edge connectors BAli BB, BC~ BD8 and BE. BA will be the first one from
the wiring side of the bay.

The leads from the packages a=e connected to one side of the edge
connector. On the other side leads are connected into the sockets and carried
over to the hinged bay in harness form, ~he individual leads are connected
to a connector socket by mea:'1.S of taper pins. The socket in turn is connected
to connector plugs (Figure l-8~ 5) on the end of the equivalent shelf on the
hinged bay ..

'The connector plug has taper pin sockets on one side into which leads
to and from packages are connected. The socket and plug combination in the
hinged bay is used to provide an easy disco~nect and eliminates disconnect~
ing the individual ieads in the fixed bay.

The connector plug has fifty taper pin sockets on. one side 'and male
connectors on the other end. The connector plugs are designated Cp60 through
CP68 and the connector sockets are deeignated CS60 through CS68, The low-
est number plug is located on the N shelf with the connectors on the other
shelves numbered consecutively downward 'with CP68 on the Y shelf. The
connector socket on the end of the ha:rnassed wires fits the connector plug of
tl-te corresponding nurnber. Thus CS60 plugs into CP60:CS6'1 into CP61,
j

etc" The wiring of each shelf edge connector is shown in the Processor
Connect~r Wiring d~awings.

10 3 • .3
Signal Wirin] ,
Signal wiring consists of leads between packages within one bay, between
both bays~ bet~'een the processor and input-output units and between packages
j

and the control panels, Signal flow between packages within the same bay is
accompl:ished by connecting a lead between the tabs of the packages involved.
Signals between packages in different bays are routed through the shelf-edge
connector (Section L 3" 2. 4).

1 ... 10
 Signals between the bays and the control panels are routed through the
panel connectors (Figure 1-8, iteTI1 10~ 11, 12 and 15) in the base of each bay.
There are four 50-socket connector plugs mounted in the bays, 3 in the base of
the hinged bay and 1 in the base of the fixed baYa These plugs carry signals to
and from the control and Engineering Panels o The connectors in the hinged bay
are CP70, CP71~ and CP72 and the one connector in the fixed bay is CP73.
Connector plugs 70, 71, and 73 carry signals to and from the operators panel,
CP72 is used mostly for signals to and from the keyboard and Engineering Panel.

The leads to and from packages are connected to the plug by TI1eans of
taper pins. The plug then fits a connector socket to carry the leads to the
panels.

Signals between the package area and the input-out-put units are sent
through the four connectors (Figure 1-8, items 16-19) in the base of the fixed
bay. Signals froTI1 the hinged bay are first routed through the shelf-edge con-
nee tor s 3 then to the input- output c onnec tor s.

The four connectors are named CPA (light blue)~ CPD (green), CPC
(yellow), and CPB. Each connector is '<-colored to match the connector in the
particular input-output unit it supplies.

The signal leads are connected by taper pins to the connector sockets. A
connector plug attached to harnassed leads fits the plug to carry the signals. to
the necessary equipTI1ent~ The harnassed leads have a connector socket to fit
a plug mounted in the accessory are labeled CPA~ etc. The connector sockets
mounted in the fixed bay and the sockets on the harnassed wires are labeled
CSA, etc. The connector socket CSC in the fixed bay receives connector plug
CPC which is on one end of the harnassed wires. The connector plug in the
printer is also CPC and it fits into connector socket CSC on the pa'rnassed wires.
CSA and CSB carry signals to the Rea'd.-Punch Unit» CSC carries signals to the
High Speed Printer and CSD carries signals to the Card Reader.
 SECTION TWO

PRINTED MAINTENANCE AIDS

2.1 GENERAL
Printed maintenance aids in the file of prints for the computer provide
various types of information. The lTIajor types of prints are: Logic; Trouble-
shooting Layout~ Wiring, and Schematic.

Logic diagrams~ which are discussed in the Processor and Input-Output

manuals, describe the logic of UeT circuits~ Troubleshooting layouts are expand-
ed versions of logic diagrams showing many physical connection points. Wiring
Charts show all terminal-point connections. There are wiring charts for all
shelves, connectors~ power supplies, fuse panels~ barrier strips~ etc. Since all
wiring charts are of the same type~ only the shelf wiring charts are explained in
this section.

Pictorial drawings of each package show the circuit components, their

positions on the board~ and all terminals on the package. (See section 1. 3. 1 J
Figure 1-11). Schematic drawings show all of the circuitry of the DC T. There
are schematic drawings of packages~ power distribution 3 power controls, con-
trols and indicators, etc. Since most circuits consist of printed wiring, pack-
age schelTIatics are explained in this section. Reference drawings such as layout
legends, signal lists~ processor package compleITlent, and bay layouts are also
available as maintenance aids.

Signal lists show all logic signals ~ together with their source and de stin-
ation. The complete signal list is contained in Appendix A of the Processor
Manual. The processor package cOll1plement combined with the bay layouts
(see section one, Figure 1-9 and 1-10) show the grouping of the logical units and
each package location.

Most diagrams and drawings can be advantageously used in conjunction

with others. For example, an input signal can be found at a certain terminal on
a particular package on a troubleshooting lC:.-you!, and then by locating the same
terminal and package on the shelf wir:ing charts 8 the package type can be found.
Next, using a package schematic i the circuit component that the signal enters can
be identified, and with a package pictorial it can be located on the package. This
section explains the troubleshootili g layouts and wiring cha"rts and their use to-
gether in tracing signals.

2.2 LOGIC DIAGRAMS

Logic diagrams show only the logical components of UCT circuits and the
signal flow between these components. No attempt is made on these diagrams to
identify physical locations. The UeT Processor and Input-Output ll1anuals use the
logic diagrams to explain the theory of operation of the computer, and Section
Two of the Processor manual explains the symbolism used. A cOll1plete set of

2-1
logic diagrallls is contained in Appendix A of the Processor manual.

2. 3 TROUBLESHOOTING LAYOUTS
Troubleshooting Layouts (also known as Logic L~yout Drawings) indicate
the package addre.sses of all logical cOlllponents and show in detail the physical
connections between packages. All troubleshooting layouts use the same sym-
bolism, so the example used in Figure 2-3 will suffice to explain the use of this
type.

Figure 2-1 lists all logic sYlllbols and their Troubleshooting L~yout
counterparts. When an amplifier has a huilt-in diode, it is indicated by an en-
closed corner of the symbol. Figure 2-2a shows a gate feeding an amplifier in
both logic and troubleshooting symbolism. In the logical representation of the
circuit, four input signals enter a gate symbol, whose output enters an A-phase
amplifier. In the troubleshooting representation of the same circuit (Figure
2-2b), three leads enter the gate symbol and the fourth enters the amplifier
through the built-in diode.

A gate or buffer consists of a number of diodes with a common output and

several inputs. The actual electronic configuration of a huffer or gate is shown
below along with its logical and troubleshooting counterparts.

~-
LOGICAL GA~E LOGICAL BUFFER TROUBLESHOCYI'INC ELECTRONIC CONFIGURATION
GATE OR BUFFER OF GATE OR BUFFER

Sections Two and Six of the Processor manual explain the logical and
electronic ~functions, respectively, of gates and buffers. .

The troubleshooting amplifier sYlllbol (Figure 2-2b) has power pulse,

Mocking pulse, and test terminals indicated. On both logic a~d trqubleshooting
symbols (Figure 2-1), a dot on the amplifier symb,ol indicates that it is a com-
plementer and the letter A or B indicates the phase of the component. The
letter S following the phase letter within th~ symbol indicate's an arithmetic-
register shift--type core. Similarly, the letter T indicates an arithmetic -reg-
ister transition-type core. On troubleshooting layouts an output signal is
shown within a rectangular box (Figure 2"12) at the vertex of the ·amplifier sym-
bol. Complete special packages are represented by a:
r~ctangle with the pack-
age letters inserted for id~ntifiG·a~ion.

Figure 2-3 contains parts of four sep~rclte packages, all of which are on
the Y shelf. The packages involved are numbered 57, 60, 61, and 63. The
package-terminal-point is designated by the package num~er, shelf letter, and

2-2
 LOGfC LA'tOUT ~ LAYOUT

f'OW'E.~ POWE~
PULSE PULSE

-G>- INPUTS OUTPUTS

-G>- INPUT OUTPUT

BLOCKING. BLOCKING
PULSE PULSE
Non-Complementing SinG le Power Amplifier Arithmetic Reg 'l ster Shif't iype Core
POWER POWER
FULSE. PULSE

INPUTS uUTPUTS INi=lUT

BLOCK ING, BLOCK ING BLOCKING

PULar: PULSE PUL..Se.
Ccmplt!'Tlel'at:n; :'!"gle Pewer- Ampiifler Arithmet ic Reqister Trans it ion T'1'pe Corp.
,"OWER
PULSE

OUTPUTS

B\.OCKII'{G
PULSE
Non-Comp'e;r..e'1tir.g Double Powe~ I-,mplif!e r Ell/'fer
POWER
" :.J LSL

INPU TS Ct;TPUTS

BLOCKING
PULSE
Complemer.ting DoubJp. Power Amplifier 5ignc\s

-[} OR

Non-Complementi."9 Transistor Driver Amplifier

-ill- Complementing Transistor' Driver Ampliflel"

*' WI-!EN SHOWN OEHOTIS A HEAVILY LO"OED CORE

Figure 2-1 Logic and Troubleshooting Symbols

 GATE AMPLIFIER
(NON- COMPLEMENTER)

Q. Logica'

GATE AMPLIFIER
(NON~COMPLE MENTER)

SIGNAL

b. Troub"'eshooting
3161

Figure 2-2 Gate and Arn.plifier. Symbols

terIninal nUInber. Example:

Package Number T Shelf I-Terminal Number

Three leads are shown connected to the firs,t gate in Figure 2":3 although
only one is used e The unused leads are shown for uniformity since many other
such cOInponents dO,use all or most of their connections. The broken lines in
Figure 2 -3 show the separation between packages. Such lines are not found on
the actual layouts and are used only to siInplify this , exampie~

The first input shown in Figure 2-3 is sig~al M2 which comes fro:m point
39Z5 and enters package 57Y at terminal point five. It leave"s' package 57Y at
point 35 (57Y35) and also, after flowing through a diode, at point 8 (57Y8). From
point 57Y35 it goes to and enters pa'ckage52X at point 20 (52X20), and from
57Y8 it enters an A-phase compleInenter in package 60Y at point eight.

Function signal 2B comes froIn 51 Y52 and enters package 60Y at point 22.
Signal 2B leaves package 60 Y at terminal point 52 and enter's package 70Y at
point 22. It also enters an A-phase complementer in package 60Y through the
built-in diode which is indicated by the' enclosed corner'of' thecomplementer
symbol. ' The complemenfer is supplied with anA-p'hasep'ower pulse entering
package 57Y at terminal point 17 and with a B-phase blockLng pulse enteririg the
package at point six.
,
, ,

The circled numbers 17 _and 6 signify only the terminal point at which the
power pulse or blocking pulse enter~ the pack.ag'e and should. nof'be corifused
with funt:tinn signals. In all function signals, the number is" followed by the letter
A or B; for example, function signal 2B enters package 60Y at terminal point
22. The letter A or B signifies the phase of the function sig'nil. Power pulses
are always indicated entering a c~mplementer, amp'lifier, or core 'from above
the symbol, while a blocking pulse enters ft"om below. When the component is
A-phase, the power pulse is A-phase and the blocking pulse B-phase, while the
reverse is true for B-phase components. - -

The two lines (TT7 and ';tT4) shown entering the complementer from be-
low indicate test terIninals. The ~irst (TT7) is for testing the input signal while
the second (TT4) is for testing output sig!"l~ls. The" t~st terrninat for the input,
is always shown toward the input side of th~ symbol and th'e output test terminal
IS shown on the output end.

The output signal of the com.plementer in package 60'Y goes' to point 14

(60Y14), w~ich is one point of a branch in the drawing. The second common
terminal point (44) is not used but is inclU:ded for uni{orm'lty.' SInce point 44 is

2-3
not used, it is not labeled on this layout. An example of the use of both bifurcated
terITlinals is the first input on the drawing. Signal M2 from terminal point 39Z25
enters package 57Y at point five and leaves by the corresponding point 57Y35.

The signal leaves package 60Y at point 14 (60YI4) and enters package 57Y
at point 22 (57Y22). It flows through a diode in package 57Y to become an output
at point 15 (57Y15). From this point the signal leaves package 57Y and enters
package 60Y at terminal point 12' (60Y12). The signal goes through. a l3-phase
complementer in package 60Y. An output signal from terminal point 60Y 13 also
enters the same com1?lementer at point 20 (60Y20), through the built-in diode.

The complementer in 60Y receives a B-phase power pulse through point 19

(60Y19) and an A-phase blo~king pulse through p~int three (60Y3). The signal
leaves the complementer at termina~ point (1 (60Y 11), and then enters package
63Y at point 22, flows through a diode, and becomes an output at terminal point 15
(63 Y15)a From point 63Y 1'5' it enters an arithmetic shift-type core in package 61 Y
at point five (61 Y5). This core also receives A ... phase power pulses through ter-
minal.point 21 (61Y21) and B-phase blocking pulses ,through point 22 (61Y22). All
7
other troubleshooting
, ',' ..
layouts follow this same patte rn.
,. ;,." '

Z.4 SHELF WIRING CHARTS

The shelf w~ring charts show all package terminal points of the shelves and
connections to and from each point. Each bay of the Processor contains eleven
shelves -- A~. C D ~ F'G H J K,L -- in the fixed bay and --M N P R S T"V W X
Y Z - . . in the hinged bay. Each shelf has 100 package positions, and each shelf
wiring chart shows wiring connections for 25 packages on one shelf. Figure 2-4
shows only four of these package' positions. .

Be,cause the numbe,r of packages in a logical grouping varies, each wiring

chart does not al'~aYt:3 ,show connections for one full logical group. For instance,
the Register C package-group contains 39 packages, but only 25 appear on one
chart. The reITlaining 14 are on another. The first four package positions of the
Register C group a.~e used for explanation of shelf wiring charts. These wiring
charts include both internal and external wiring. Internal wiring is wiring with-
in a lqgicalgroup (not limited to a shelf), while external wiring is wiring' between
logicCil groups (notnecessarily wiring between two &helves, as the logical groups
may fallon one shelf). T~e wiri~g connectors and encircled connections on the
exaillple are shown for explanatory purposes only and refer to the section on Lay-
out-to- Wiring charts.

The tabs at one ,edge, of a package connector are numbered 1 to 22 on one

s~de~n,.d 3,1 to 52 on the opposite side. Every terL.~inal point shown on a trouble-
shooti~g layout is also shoWn o'n the wiring charts.

The packages receive power pulses, blocking pulses, d-c voltages, and
ground c9nnections fro~ sev~n busbars below each shelf. Three volts d-c is
carried on bus'bar 1, B-phaseblocking puises on busbar 2, A-phase power pulses
on busbar 3, B-phase power pulses on busbar 5, A-phase blocking pulses on

2-4
 I I
GATE OR BUFFER A PHASE COMPLEMENTER I B f-'HAS[ COMPLEMENTER I A PHASE
I I ARITMETIC, REGIS TE R
5H I fT TYPE CORE
POWER
PULSE I
I I I I \
I I
II ~ 51Y I I 11~n~
l~r151
b3Y I I I

81 I I III
I
I
BLOCKt NG
I I I
I PULSE I I I
I I I I
3162.

Figure 2-3 Troubleshooting Layout Example

busbar 6, and -29 volts d-c on busbar 7. Busbar 4 is a ground connection. All
package contacts on the wiring chart with a Bus 1 through Bus 7 designation
must be wired to the appropriate busbar.

Packages are numbered from 00 through 99 on each shelf, so that every

package is designated by its position. Thus, paCkage number 50 on shelf Y is
package SOY.

All shelf wiring in the Processor is color-coded according to its

application.. The following table shows the wiring color code used.

ABBREV.. COLOR APPLICA TION BUS DESIGNATION

BRN BROWN + VOLTAGE, +3 BUS 1

RED RED BLOCKING PULSE B BUS 2.

ORN ORANGE POWER PULSE A BUS 3

YEL YELLOW GROUND BUS 4

GRN GREEN POWER PULSE B BUS S

BLU BLUE BLOCKING PULSE A BUS 6

VIO VIOLET - VOLTAGE, -29 BUS 7

BLK BLACK EXTERNAL WIRING

WHT WHITE INT ERNAL WIRING

CLR CLEAR FUNCTION SIGNALS

+ TIMING SIGNALS'

GRY GREY
.

TABLE 2-1 UCT COLOR CODE

A typical example of package wiring is package number 52 on the Y shelf,

or 52Y (Figure 2-4).. Terminal point 52Y 1 is the first point on the left side of
the package S2Y; it connects to bus bar 6, ~hich carries the A-phase blocking
pulses.. The letters BLU alongside point 5lYl indicate that a blue wire is used
to connect this tab to busbar 6
0 Terminal point 53Y3, tab 3 of package 53 on
the Y shelf, is connected to busbar 2~ which ca~ries B-phase blocking pulsesl)
by a red wireo Tab connections which have nC! representation on the wiring
layout are not used, so that point 52Y31 (blank space) is a package tab which is

2-5
 not connected. Terminal point number SOY 12 is connected by a white wire to tab
10 on package SlY (5IYIO). Terminal 52Y37 is connected with a white wire to
52Y42. The lettering ARI-S across package 52Y indicates that it is an Arith-
metic Register Package. The package type is always shown in the location of
its key. Thtis, all ARI-S packages are marked at point 3, 33 on the wiring
charts.

2. S SIGNAL FLOW AND WIRING CONNECTIONS

Figure 2-4 is the wiring chart for the layout diagram shown in Figure
2-5. The following table details the relationship between these two diagrams.

SIGNAL FLOW CONNECTIONS

Refer to Fig. 2-5 Refer to Fig. 2-4

Signal RSC from 08X48' enters pack- A black wire connects 08K48,~tith tab
age SOY at point 1. 50Y*.

The signal RSC is sent from SOY 1 Two leads on package connect point I
through a diode in package SOY to to diode and diode to point 9*.
50Y9.

The signal also leaves package A black wire connects 60Y31 to

SOY at point 31 and enters pack- 63Y 1*.
age 63Y at point 1.

From 50Y9 the signal enters pack- A white wire connects 50Yto tab 53Y10.
age 53Y at point 10.

A signal from 51 Y45 enters pack- A white wire connects 51 Y45 to

age 53Y at point 18. S3Y18.

The two signals then enter a com- A lead on package connects points
plementer 'in package 53Y. 53Y18 and 53YIO to complementer.

A B-phase Power pul~e enters com- A green wire connects busbar 5 to tab
plementer 53Y at point 21. 5jY21.

An A-phase blocking pulse enters A blue wire connects busbar 6 to

.
. c omplementer 53Y. at point 4. 53Y4 •

The signal is sent from the com- A lead on package connects c omple-
plementer to 53 Y 13. l.L1.enter 53Y to tab 53Y13.

From 53Y13 the signal enters pack- A white wire connects 5JY 13 with
age SOY at point 5. SOYS.

*The wiring between these two points is not shown because the figure being
used does not contain both ends of the connection.

2-6
POW~R (17\~____
PUL'!>E. \!2J
I<.MZ TYPE oS
TYPE. C 1.57K DIV\4-
1ft. W 1"/0
\NPlJT rypE.G.

INP~T© t1 ;3
0--+:
\-_.

I
·OUTPUT
7
TT~ @}-----. FERrACTOR
TYPE C A1-S TYPE.e
DJ4 '-------41 0) T T 5
DJ3

-zt!J

BLOCKI N C. 'PUI..$E

~z.~7

Figure 2-6 Package Schematic Example

 SIGNAL FLOW CONNECTIONS

Signal LIOD COll1es froll1 33Z41 A black wire connects 33Z41 with
and enters p,ackage SOY at point ? 50Y6*.
. '

Signal Alar:> cqll1es froll1 9lVI.3and A bla~k wi~~ connects 91 V 13 to

enters package 50Y 'at point 37. 50Y·37*.

These three signals are then sent Three leads on the package connect the
through a dl'ode in package50Y and diode to SOY8.
the resulti.u1.t signal output goes to
terll1inal pOInt says.

The signal then leave s the package A white wire connects 50Y8 to 53Y7.
SOY at point 8 and enters package
53Y at point 7.' "

Signal X10D cOll1ing froll1 terll1inal A biack wire connects 77TII to 53Y46*.
point 77TII enters package 53 Y at
point 46.

These two signals are sent to a A lead on the package connects termi-
.;'
c oITIplell1enter In package S 3 Y. nai points 53Y7 and 53Y6 to· cOITIple-
ITIen.tei,

An A-phase power pulse ente'rs the An orange wire connects tab 53 Y 17 to

co~plementer from 53Y17 •. bus bar 3.

A B-phase blocki'ng pul~e ~'nters the A red wire connects busbar 2 to 53Y6.
cOITIplell1enter 53Y at point 6.
p

The resultant output' signed RDlthen A lead on package connects the c om-
tlows from the' comp1ernenter to pfementer 53Y t'o P?int 15.
53Y15, " . ,.

Signal RbI then leaves the package A 'black wi~e c~nnects 53Y15 to 10Z1S):~.
at:SlYl5' and enters package' 1:0Z -
atpoi:n:t15., h .

*T-he'wiritig- betweeIl :these two points 'is not shown because the figure being used
does n~t contain both ~n~rs of the connecti.:;n. "

, 2. 6 PACKAGE: SCfIE'MATICS ANDP~CTORtALS

There. i~' a s~-h~iri~ti~ ~~d l~i~to~ial' for>each. t:y~e, of :pCl:ckage 'use'd in the
UCT. Each schematic shows the complete circuitry of a package with circuit
cOll1ponents named according to....the position
, ~ -'.' -
' : : ,
they occupy on the package board.
~ -, , -' .

, Figure 2-6 is a~'~mple sChemat'ic of th~~~n-complementing single

power amplifier package I which is shown in Figure 2-2 in the logic and'

2-7
troublesho~~~~g diagJ:"am representation. The package pictorial drawing of this
circuit, Figure l-fl, shows the circuit components mounted in position on the
board.

The input and output terminals (Section L 3. 1) of the package used in

this circuit are circled and labeled. Example: the inputs to this circuit are
terminal points 22, 52 and i6, 46. The two terminals (22, 52) that make up a
pair are bifurcated as explained'in Section 1. 3.1. . . ..

The power pulse to this amplifier enters the circuit at term~nalpoint

17, 47, the blocking pulse at 1, 31, -29V at 4, 34, and terminal point 5, 35 is
connected to ground. The circled single numbers represent the pin numbers
of the magnetic cores. .

The circuit components are all labeled on the schematic according to

their locations on the board. Resistor RM6 is mounted in row M, position 6,
diode DJ3 is mounted in row J, po,sition 3 (Figure 1-11). Section 1. 3. 1 ex-
plains the addressi!lg of cir,cuit components. TT5 and TT6 are test terminals
f or the output and input signal s.

2.7 MOUNTING BOARDS AND ADDRESSING SYSTEM

Circuit components on a mounting board are n.amed on the circuit sche.-
matic according to their address on the board. There are three types of mount-
ing boards. One type of board has t~ree rows of numbered mounting positions
labeled M, Land N (top to bottom) and a second type of board has three rows
labeled J, H, and K (top t<;> bottom). On these tv.:0 ~Yf>es" the addres s consists
of the initial letter of the component (R for resistors, D. for. diode ll C' tor
capacitor, etc.), a letter designating the row, and the number of the specific
mounting position in the row. Thus s a diode mounted on position 3 of row J is
DJ3.' . . ' ".

When a component is mounted between row J and e,ither row H or K, the

address is give~ fo~ th~ 'J ~ow. 'If a"component ts 'mo~'l1t'ed between r()ws" Hand
K, the K row is used 'in the 'component address. On 'th~ L~M'-'\N type 'boards; a
component mounted between row M and either row L or N, is given an M-row
address. If the component is mounted between rows Land N, the N row is
used in the component address. Rows Land H (middle rows of the two types
of mounting boards) are never used in the address of a' component unless all
leads of a component are connected to that row. For example~ if the three
leads of a transistor were connected to mounting positions IS, 20, and 22 of row
H, its address would be QRlS. The mounting position used in the address is the
one to which th~ transistor ba:se is co~nected. 'E~gineering 'Drawing D)(SOS;
OSO illustrates these two types of mounting boards. The circuit schematics
indicate which mounting boards are involved in the circuit. Mounting boards are
abbreviated to the lettersMB an'd a numhe~' ()n cal ~cheinatic's ancfwiring draw-
ings except on Read-Pun,~h drawings ~here the ~ett'~~st:TB are used.

The third type of mounting board' has two rows of mounting posItions. The
positions are,numbere? c~ntinuously through t~~ two rows. For ex~mple, if each

2-S
 50 31 51 31 52 31 53 31
1- 31 "08X4S BU( b3)'1 VIO 52Y2 BlV ~U.5 6 "52 Y32. VIO ?4YZ

t
---- ---
2-32 YEL BUS{ "51'/3f v,o 53Y1 YEL BUS ....
I

, - f------- ---- -- 1----- --_.-

3-33 BlU BUS6 AR i-'S Rep BUS 2
- -- ------- --
4-34 RED BLyJ ~£IS 6 ....
\
, BUS 2 ~f<N BUS ~
1': .",.
-.-~-

5-35 WHT ~3Y13 r--- BRN BUS 1 "50Y1. 13fiiN £3 ()S 1

---.... ~
/' /'
---- -- ~- ~,--,- 1--

6 -36 13LK 33Z41 BUS 2 WHT 52Y15 /' RfD I '$rJ5 2...
- - , - - - - - r----- r-..:
~~13-
........ 1---
7-37 WHY 1~2"142 ~ ~50~8""
r'
B- 38 WHT r.£.:.3YJ-., ~to-"
r--
-- .,- - "SOYU'
f - - - ---
'"
---,---,-1-
- --r ---
WilT
"51)'16
52'( 10 WI-lT/ 55Y22 / WHT 57Y11
9 -39 WHT ~ 3Y1 0: ___ AC1-S~ ".s-OYf1 .. I I AC1-S
~OY12~ ~ '5-2V~
10-40 GPP-S -- I ~ ~OY'1=
!

SHELF ---,.--- ~
11-4 t WHT 52Y9 5"0'12) ------ -J..- ~--
"3<1r48
Y 12 -42 WHT 5'1'{10
f-----
"50Yf5 ............... ~I I"'" 52-Y3? WHT '57r12.
~3 -43 WHT ~/YS WHl S'1'Y20 I r---- "5'OYs-.....
14 -44- WHT ,ZYIJ ~OY22
WJ.lT
- - - --
54Y15
,
I ..... ..,;

.- ---
WHT 5'1Y9 I ,
1. "39T17
15 -4- 5 WHT 51 y12.
--
~;Yt7 WHr . . .S3Y/S
.
~
.....
.",.
"52'(6 I I
BLK W~15
I

1(-4- ,6 "',2 ~ Y48 ~;~20 wl4T SLY7 «ED 8US~ ~r..... I "77Tl1 I
-- -- - - - I

17-4- 7 Wt-l1 5"iy'1~

.
oRN
_----- 1--'-
BVS 3 SlIJ BUS 6 I ~ ~f?fV 131JS
..... 3 .... ~ .. I

~8-4-
8 WHr 5SY12 Ref) BU:; 2. I I ~ ~1Y45"= \
- ----- -
19-49 "34X45 CLR. 57Y1 GRN
-,
BUs, '(EL B(}s 4 I
,I ORN BUS 5 \ I

~1V1S ",1 yo \I,mr, !i"5"YIIJ

20-50
2.1-5~ WHT 5"1 Y~1
C L~ 5-,'('2-

oRN
f---
BUS 3
ORN
ORN
BUS .5
svs :1
I
I , GRN I ~vs
i'"
s-
.....

22- 52 WHT I!i~ '114 'OOV14- CL.R. 60'122 RED BU~ 2- I

I I WfI' f/~Y g
--- ----- ----- ...-

FbLZ:- -E-s:S-~fW#Lerm _~BUS1

I I

+ VOLTAGE

== ~;~E §EE$Ee ~:;:~::

+3
cm··YJJ
BLOCKING PULSE" B
POWER PULSE A
GROUND
POWER PU LSE 8 tWlJ WAI -__ ~~___-_-a-~-~_~~-m- ~JP~L fW;l jpgLJ BUS 5

BLOCKING PULSE A ~-=_ ~ W#J ~=_:m~C:F'L.--=wtCl?#Au-lW~ _UIiiIl¥WJiI W4 _ fW!l; IW I8

___
w@ f{({i1 US 6

-VOLTAGE -29 ~-=-==~--=-~~==~~ ,~.m::~-:m:::J!Wj:::::::J BUS 7

311o~

Figure 2-4 Shelf Wiring Chart

R5C OBXA8 I 1
63 Vi 31
5
soY SOY
L f OD 33 z. -f 1 b
I ._e ~OZ-tb
A10D 91V13 . I
37 X10D 77TH

316+

Figure 2-5 Signal Flow Example

row has 12 mounting positions, the first row is numbered 1 to 12 and the
second row 13 to 24. The address of a circuit component mounted on this
type of board consists of the initial letter of the component, the number of
the mounting board, and the lowest position number the component is mount-
ed on. Thus, if a diode is mounted between position 2 and 14 of ITlount-
ing board 6, its address would be DMB6-Z. In some cases mounting boards
of this type are identified by a letter instead of a number. If the diode in
the previous example was on mounting board A, its address would be DAZ.
This type of mounting board is shown on Engineering Drawing DX601, 083.

2-9
 SECTION TI{REE

CONTROL PANELS

3.1 GENERAL
All controls and indicators for the processor are contained in the Engi-
neers and Operators Panels o The purpose of this section is to provide an
explanation of the function of each control and indicator on the panels.

This section will explain only the panels on the processor. The Read-
Punch~ Printer~ and Card Reader Manuals each contain an explanation o{
their respective panels.

3.2 ENGINEERS PANEL

The Engineers Panel (Figure 3-1) located on the processor is intended
priTIlarily for the use of technicians and mai71tenance TIlen. The panel contai~s
12 indicator lights~ three illuminated pushbuttO!"L switches~ a voltrne~:er~ voltage
TIlonitor switch» and a polarity switch for the voltrrleteT. All indicators on this
panel have clear glass domes above the neon lamps, which glow orange when
lit. The function of each light and/ or switch is explained in the following para-
graphs.

3. 2. 1 Pushbuttons and Indicators

DOOR INTERLOCK - lights when the door interlock sWItch is open,

indicating that the processor bays are open.

AIR FLOW - lights whenever the air circulation falls from -t:he desired
rate of flow in the processor.

OVERHEAT - lights to indicate the temperature has gone above the

desired limit in the processor.

DRUM - lights to indicate either of two off-normal conditions of the drum:

(1) that the drum temperature bas risen above fhe desired limit or; (2) the
spacing between the heads and drum has become less than or greater than the
required distanceo Either condition energizes a relay to tUrn off power and
light the DRUM indicator. The relay is reset by depressing the FAULT RE-
SET !FUSE TEST pushbutton o

CYCLING UNIT - lights when an error is detec.ted in the cycling unit

indicating that the timing band sentinels have occ.u:r red at the wrong time or in
the wrong phase or that the series circuit is openo

PRINTER CODE WHEEL - lights to indicate a parity error in reading

from the code generator~

MAIN STORAGE - lights to indicate parity error when reading frolll the
lllain storage druITl.
 ADDRESS STORAGE - lights to indicate a parity error when reading
from the TS band.

PRINT BUFFER STORAGE - lights to indicate a parity error when read-

ing from the Print Buffer Band.

DELETE STOP - lights when depressed to over ride all errorp,' instruc-
tion and control, that would normally stop the computer. This pushbutton re-
mains locked allowing the computer to override all errors until it is depressed
a second time (alternate-action).

MUL!DIV TEST - lights when depressed to stop processor when it is

executing a multiply or divide instruction. This button must be depressed a second
time to allow the processor to continue (alternate-action).

FAULT RESET /FUSE TEST - depress to test for blown fuse in pro-
cessor and/or printer. If there is a blown fuse in either or both units, the
PRINTER FUSE and/ or PROCESSOR FUSE indicator will light. Depres s to re-
set overload relay of+'3 volt and -1.5 volt circuits and to reset the drum over-
heat and drum head spacing relays (momentary).

OVERLOAD RELAY - lights to indicate a current overload on the .+3

volt and -1. 5 volt circuits.

3.2.2 Voltage Monitor

VOLTAGE MONITOR METER - indicates percent deviation from normal

voltage level.

POLARITY SWITC"H - set to polarity of voltage being monitored.

VOLTAGE MONITOR S'WITCH - set to voltage level that is to be mon-

itored. Table 3-1 lists the switch positions and the voltage that is monitored for
each position.

3-2
 TABLE 3-1

Polarity Switch Set on Plus

i
I
POSITION VOLTAGE MEASURED TO

A + 3 GND

C -+ 6 GND

D +10 GND

E + 16 GND

F +18 +19
I

I G +19 +16

H +20 +19
I

J +28.5 +30

K + 30 +35

L + 35 GND

M +45 GND

N + 100 GND

P + 150 +100

R +300 GND

V Clock A GND

W Clock B GND

OFF

3-3
 TABLE 3-1 (Continued)

Polarity Switch Set on Minus

POSITION VOLTAGE MEASURED TO

A r
I -1. 5 GND

D -10 GND

E -11. 5 -10

J -29 GND

K -30 or -40 GND

L -32 or -42 -30 or -40

M -45 or -55 -30 or -40

N -SO -29

P -150 GND

OFF

3-4
o o
VOLTAGE MONITOR
W OFF A +

DOOR AIR OVERHEAT DRUM

INTERLOCK FLOW
o
~0 0 10 5) 0 I L K J o
CYCLING fA...
UNIT '0
PRINTER
CODE
MAIN ADDRESS PRINT
BUFFER eJ FAULT 0 0
WHEEL
RESET PRINTER ~ PROCESSOR~

00
DELETE
STOP
MULTIPLY I DI VI DE
TEST
00000
FUSE
TEST
FUSE FUSE OVERLOAD
RELAY

o o o o o

Figure 3-1 Engineers Panel

 3.3 OPERATORS PANEL
The operators panel (Figure 3-2) is the main control panel of the
computer. It contains most of the controls and indicators necessary to
operate the computer. Each pushbutton and indicator is described in the
following paragraphs.

STATIC REGISTER -.8 lights to indicate the contents of the Static

Register. The number in the lights indicate the weight of each bit.

REGISTER SELEC TOR - four illuminated pushbuttons, L, X, A9 C I

used to select register to be displayed by the REGISTER CONTENTS lights •
. The four pushbutt~ns are interlocked to prevent selection of more than one
register (alternate action).

SIGN - two lights to indicate the sign of the contents of the register
being displayed. r,:

REGISTER CONTENTS - 40 lights indicatiq; the contents of anyone of

the four registers, A, x, Land C.

PRINTER OFF NORMAL -. lights red when an abnormal condition

occurs in the printer or when the printer is not prepared to print. Refer to
lights on the Printer panel for cause.

CARD READER OFF NORMAL - lights red when an abnormal con-

dition occurs in the Card Reader. Refer to lights on the Card Reader panel
for cause.

READ PUNCH OFF NORMAL - lights red when an abnormal con-

dition occurs in the Read-Punch or when the Read-Punch motor is not
running. Refer to lights on the Read-Punch panel for cause.

PROCESSOR OFF NORMAL - lights red when a malfunction occurs

in the Processors when the stop switch is depressed, or if the processor
is operated in a non-continuous mode. Refer to the lights on the Engineers
. . panel for caus ell . .

Do C. - lights green when dc is on. Depr e s s to turn dc off

i{

( motnentary). ~

Ao Co - lights amber when the DC READY pushbutton is depressed

to indicate ac is on. Depress to turn ac and dc eff (momentary).

DRUM- lights when DC READY is depressed to indicate drum is on.

Depress to stop drum revolution (momentary).

Do C. READY - lights amber when drum is at full speed and AC time

I delay has expire,d. Depress to turn ac an~ drum on and depress when lit to

3-5
turn dc on (moment~ry).
! -l.

'9'6CHECK - depr~~s to
i'iihib'it operation of bulier transfer check cir-
cuit. Lights white when activated (alternate action). (Not shown on Figure
3-2) ..

i'LERT -9b CHEJCK_' iigb'is t~ indicate that a b~ff~r transfer was

mis sed 'o~ a 96 instr:uciion, ',~(N~t'~ho~n on 'Fig~;e ~ -2). '

REA']) PUNCH _'iEMPf:~i S'TATION INHIl3IT' '-'depress to cause the

computer to continue even though one or more stations are e~pty in the Read-
pun~hu~ft.' Liiht-s"'a~her wh~~ activaf'ed (rno~entaryJ~-"

READ PUNCH-NO PUNCH - depress to eliminate punching in the

Read-Pun:chUnit.' Li'ghts ambe-'r' when acH:Vat~d. 'Mti.'sth~ 'depr~~~'ed a second
time to be released and allow punching (alternate a~tion). '. ' v

NEXT ADDRESS m - when lit, indica~es next memory search will be

for the rn addre~s. Whe~ not fit and m
address' is desired, de~ress. to trans-
C

fer control :~rorn c,to 'm ,(momentary).

NEXT ADDRESS c - when lit, indicates next memory' search will be

for c address. When not lit and c address is desired, ,dep,re,ss to t!ansfer
control from m to c (mome~tarY).

GENERAL CLEAR "~ . depress' to clear controls, i~dicat;~rs, and flip-

flops. Lights red when activate,d (momentary).

PRINTER - NO PRINT -. eliminates printing when depressed. Lights

amber when activated. Must be'dep'ressed. a;' se'co'i:J.ci time to"be r~leased and
.;

allow printing (alternate action).

PRINTER-ONE LINE PRINT - when this pushbutton is depressed~

the processor proceeds normally until the next print instruction is staticized
and then stops. Lights when activated (alternate action).

READ PUNCH - ONE CARD R. P. U. - when this pushbutton is de-

pressed the processor proceeds normally until the next card feed instruction
is staticized and then stops. Lights when activated (alternate action).

READER-ONE CARD READER - when this pushbutton is depressed

the processor proceeds normally until t~ .. z next card feed instruction is
staticized, then stops. Lights when activated (alternate action).
)
COMPARISON STOP - when this pushbutton is depressed the pro-
cessor completes the next comparison instruction, then stops. Lights when
activated (alternate action).

3-6
 ONE INSTRUCTION - when this pushbutton is depressed a ' the processor
staticizes the next instruction and stops. Lights when activated (alternate
action). ,",

CONTINUOUS - when this pushbutton is depressed the processor pro-

ceeds on a continuo,us basis. ,Lights green when activated. This pushbutton and
the five othe~ pu'shbuttons und~r the headi~g· OPERAT'ION 'in F'igu~'e' :3-'2 are all
interlocked. Only one can be a~tivate'd at"one f'{me. When 'any 'one fs'depressed,
it releases the pushbutton previously depressed, (alternate action).
" : ~ 'h , -,.'

COMPUTATION RUN - .,~~press to start computati,on~ Ltg~ts green

when activated (momentary).

COMPUTATION STOP - depress to ~top co:rn:putation. Lights amber

when acti~a"t~d·(mome~tar!Y). "'../". ~.,~ .
:.. ~':l, ; , ,

3.• 4 ,KEYBOARD
The k'eyboarcl (Figure 3-3) contain's 13',push?uttons and i~'u'sedr to type a
manual entry into the computer. The manual entries are sent to the register
selected by depressing one of the four REGiSTEtfsE'LEC'tOR pushbuftons on the
oper(itors, panel.

A- Keyboard' alert - depressed to actlvat'ekeyboard.

Keyboard Ready
'" , ..... -
- lights white when keyboard is activated.
, "' ~ ~. ~. - ...... ~.' , ~ !.:.:

0-9 Keys - used to type words Infothe'co~puter.

+ and - keys - releases typ~d ~ord into sei~~tedregister a~d dis-

connects 'keyboard. ','

3-7
 ,....-
STATIC
REGISTER
ISIGN
t---
1 2
REGISTER CONTENTS
3 .. 5 6 7 8 9 10
8 § Ie§) 8
READER PUNCH OR

OFF NORMAL
5 5
+ ® ® W ® ® ® ® ® ® ®
4 4 @ @ @ (i) @ @ C!) (!) (!) Ci) D.C. A.C. DRUM

PUSH OFF
® (i) (i) (i) (i) @ @ ® ® @
2 2
- CD CD CD CD CD CD CD CD CD G) nco READY
1 1
- OPERATION m ...c I PUSH ON I
READ PUNCH REG ISTER SELECTOR NEXT ADDRESS

D EMPTY
STATION
INHIBIT
NO PUNCH

PRINTER
L
I X

OPERATION
A I c
TIl., L

COMPUTATION
GENERAL
CLEAR

D P'L~~'lt

D
PRINTER READER

NO PRINT ONE ONE ONE COMPAR-I ONE ,ICONTINU- RUN STOP

LINE CARD CARD ISON INSTRlJC- OUS
PRINT R.P.U. READER STOP TION

Figure 3-2 Operators Panel

8

3f7~ .

Figure 3-3 Keyboard

APPENDIX
 TABLE A-I

UCT PROCESSOR RELAYS

RELAY NO. LOCATION NAME ENGINEERING DRAWINGS

Relay 3 Figure 1-6, 5 Blower Holdover Primary Power Control

Relay 4 Figure 1-3, 12 Blower Contactor PI and F2 - AC Power Distribution
Coil - Primary Power Control

Relay 5 Figure 1-6, 19 Air Flow Primary Power Control

Relay 6 Figure 1-3, 11 Drum Contactor PI - AC Power Distribution
Coi1~ P2, P3 - Primary Power Control

Relay 7 Figur e 1 - 7, 10 Drum Relay Primary Power Control

Relay 8 Figure 1-6, 13 Dl!um Ready
Relay 9 Figure 1-7, 11 DC Relay Primary Power Control
Relay 10 Figure 1-6, 12 DC Ready Primary Power Control
Relay 11 Figure 1-3, 10 AC C ontactor PI and P2 - AC Power Distribution
Coil and P3 - Primary Power Control

Relay 12 Figure 1-3, 9 DC Contactor PI, P2, P3, and P4 - AC Power Distribution
Coil and P5 - Primary Power Control

Relay 13 Figure 1-6, 4 AC Fault Fuse Alarm Circuit

Relay 14 Figure 1-6, 3 DC Fault Fuse Alarm Circuit
Relay 15 Figure 1-6, 17 Standby Fus e Alarm Pale Primary Pawe r C antral
Coil - Fuse Alarm Circuit
Relay 16 Figure 1-6, 16 AC Alarm Fuse Alarm Circuit

A-I
 TABLE A-I (Continued)

RELAY NO. LOCATION NAME ENGINEERING DRAWINGS

Relay 17 Figure 1-6, 15 .+ DC Alarm PI - Primary Power Control

Coil-Fuse Alarm Circuits

Relay 18 Figure 1-6, 14 - DC Alarm PI -

Primary Power Control
Coil-Fuse Alarm Circuit

Relay 19 Figure 1-6, 11 General Clear Cycling Unit

Relay 20 Figure 1-6, 19 Processor Off Normal Off Normal Indicators
Relay 21 Figure 1-6, 20 High Speed Printer Off Off Normal Irrlicators
No r:rn al

Relay 22 I'igure 1-6, 21 Read-Punch Off Normal Off Normal Indicators

Relay 23 Figure 1-6, 1 Card Reader Off Normal Off Normal Indicators
Relay 24 Figure 1-6, 10 Start Interrupted Operation
Relay 25 Figure 1-7, 8 Overcurrent +3V Coil - DC Powe r Distribution
PI - Off Nor:rnal Indicators

R·elay 26 Figure 1-7 J 7 Overcurrent + 3V Coil - DC Powe r Distribution

PI - Off Normal Indicators

Relay 27 Power Control Overcurrent -1. 5V Coil - DC Power Distribution

Tray PI - Off Normal Indicators

A-2
 TABLE A-I (Continued)

RELAY NO. LOCATION NAME ENGINEERING DRAWINGS

Relay 28 Figure 1-6, 2 Input Ready Interrupted Operation

Relay 29 Figure 1-6, 7 PS Short Circuit Off Normal Indicators
Relay 39 Figure 1-6, 6 MeIllory Write Inhibit Coil - Prim.ary Power Control
PI, P3, P4 - DC Power Distribution

Relay 31 Bleeder Resistor Meter Relay Primary Power Control

Panel

Relay 32 Figure 1-6, 8 Clock Alarm Primary Power Control

Relay 33 Figure 1-;6, 9 Drum Alarm Primary Power Control
Relay 34 Figure 1-7, 4 Drum Motor Start AC Power Distribution
Relay 35 Drum Speed Control Primary Power Control
Relay 36 Power Control Drum Air Flow Primary Power Control
Tray

Relay 37 Power Control General Air Flow Primary Power Control

Tray

A-3
 TABLE A-2

UCT PROCESSOR BARRIER STRIPS

NUMBER LOCATION DISTRIBUTION OF ENGINEERING DRAWING

BSI Figure 1-2, itern 12 Prirnary input power AC Power Distribution

Primary Power Control

BS2 Figure 1-2, itern 8 Autornatic Start Clock Input Primary Power Control
BS4 Ao C. N. AC Power Distribution
BS5 A. C" N~ AC Power Distribution
BSI0 Figure 1-2, itern 5 -1. 5V DC DC Power Distribution
BSII Figure 1-2, itern 5 -lOY DC DC Power Distribution
BS12 Figure 1-8, itern 14 + 3V and -29V DC DC Power Distribution
BS14 Figure 1-2, itern 5 -30V, -32V, and -45V DC DC Power Distribution
BS16 Figure. 1-8~ itern 13 +3V and -29V DC DC Power Distribution
BS18 Figure 1-2, itern 5 -SOV, +6V, +4.7SV, and + lOY DC DC Power Distribution
BS19 Figure 1-2, itern 5 + 16v and +20V DC DC Power Distribution
BS20 Figure 1-2, itern 5 + 35V, +28. SV, +19V, + 18V and DC Power Distribution
+30V DC
BS22 Figure 1-2, itern 5 +45V DC, (/) A and (/) B DC Power Distribution
Voltage Monitor
BS23 +3V DC
BS24

A-4
 TABLE A-2 (Continued)

NUMBER LOCATION DISTRIBUTION OF ENGINEERING DRAWING

BS25
BS26
BS27
BS30 Figure 1-2, item 18 +3V» +16V, and +10V DC DC Power Distribution
BS31 Figure 1-2, item 17 +45V. + IOOV, and +300V DC DC Power Distribution
BS32 Figure 1-2, item 16 -1. 5V, -29V, and -150V DC DC Power Distribution
BS33 Figure 1-7 » item 9 Over current relay connector OFF Normal Indicator
BS34 Figure 1-2, item 15 Miscellaneous to area units
BS35 Figure 1-8, item 13 +3V and -29V DC DC Power Distribution
BS36 Figure 1-8, item 14 +3V and -29V DC DC Power Distribution
BS37 Figure 1-2, item 14 Motor Barrier Strip AC Power Distribution
BS38 Figure 1-8, item 14 Miscellaneous OFF Normal Indicators
BS39 Figure 1-8, item 13 Miscellaneous OFF Normal Indicators
BS40 Figure 1-7, item I +45V Power Supply (Sola)
BS41 Figure 1-2, item 25 ..... 300V Supply (Sola)
BS42 Figure 1-,2, item 22 -30V, -48V Supply (Sola)
BS43 Figure 1-2, itern. 19 -150V Supply (Sola)

A-5
 TABLE A-2 (Continued)

NUMBER LOCATION DISTRIBUTION OF ENGINEERING DRAWING

BS44 Figure 1- 2 11 ite:m 1 -800V Supply (Sola)

BS45 Figure 1-2, item 28 -29V Supply (Sola)
BS46 Figure 1-3, ite:m 3 +100V Supply (Sola)
BS47 Figure 1-3, ite:m 4 +3'V Supply (Sola)
BS48 Figure 1-3.'1 ite:m 5 +16V Supply (Sola)
BS49 Figure 1-3, item 6 +2V (-32 V, -SOY) Supply (Sola)
BS50 Figure 1-3, ite:m 7 +6V Supply (Sola)
BS51 Figure 1- 2 11 item 27 +15V (-4SV, -63V) Supply (Sola)
BS52 Figure 1-2, item 26 +35V Supply (Sola)
BS53 Figure 1-2, ite:m 24 -SOY (-16S0V) Supply (Sola)
BS54 Figure 1- 2 3 HeD1 23 +300V (-1300V) Supply (Sola)
BS55 Figure 1- 2 11 ite:m 21 -lOY Supply (Sola)
BS56 Figure 1-2, iteD1 20 -1. 5V Supply (Sola)
BS57 Figure 1-3, item 1 -800V Supply (Sola)
BS60 Ground
BS61 Ground
BS63 Alternator and Clock Blower AC Power Distribution
BS64 Alternator Drove Motor AC Power Distribution

A-6
 TABLE A-2 (Continued)

NUMBER LOCATION DISTRIBUTION OF ENGINEERING DRAWING

BS6S Drum Blower AC Power Distribution

BS66 Thermo couples on Drum Blower Primary Powe r Control
BS67 Clock Output
BS68 Clock .Driver Chassis
BS70
BS71
BS72
BS73
BS74
BS75
BS76
BS77
BS78
BS79
BS80 Meter Panel
BS81 Meter Panel
BS82 Meter Panel
BS83 Meter Panel

A-7
 TABLE A-3

UCT PROCESSOR SELENIUM RECTIFIERS

RECTIFIER NO o LOCATION USE ENGINEE,RING DRAWING

SRI Figure 1-5, 10 Interlock OFF Normal Circuit OFF Normal Indicators
SR2 Figure 1-5, 10 Air Temperature OFF Normal Circuit OFF Normal Indicators
SR3 Figure 1-5, 10 Air Flow OFF Normal Circuit OFF Normal Indicator
SR4 Figure 1-5, 10 Fuse Fault Circuit Fuse Alarm Circuit
SR5 Figure 1-5, 10 Fuse Fault Circuit Fuse Alarm Circuit
SR6 Figure 1-5, 10 HSP Fuse Fault Circuit Fuse Alarm Circuit
SR7 Figure 1-5, 10 Fuse Alarm Circuit
SR8 Figure 1-5, 10 Standby and AC Fault RL Y Circuits Processor Fuseboards
SR9 Figure 1 ~5, II Standby and AC Fault RLY Circuit Processor Fuseboards
SRIO Figure 1-5, II Standby and AC Fault RLY Circuit Processor Fuseboards
SRII Figure 1-5, 11 Standby and AC Fault RL Y Circuit Processor Fuseboards
SR12 Figure 1-5, 11 Standby and AC Fault RLY Circuit Processor Fuseboards
SR13 Figure 1-50 11 Standby and AC Fault RLY Circuit Processor Fuseboards
SR15 Figure 1-5, 11 Overcurrent Circuit OFF Normal Indicators
SRl6 Figure 1-5, 11 Drum. Alarm Circuit Primary Power Control

A-8