FPGA

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The
F-Feld
P-Progranmmable whch can be veproammed
4-Gate Logic gate - Boolecn fuwnction
A-Aoy >n Ow and Column
FPQA:Means fg an Sntegrated Chcult which Can be
rogramme d by userfdesigner to implement any Boolean
loqfe om ComPorent& arYonged in
YOWE
Cnd Colmna,
Vendas iliny, Atero Ace
techntques- SPOM,Artifuze tEPPOM, EPRo

a
A
Field Proammable Gote AyYay CFPAAD i3 zemimductl

device -thot Can be ConfiRLaed by the customer d

degher
after mnonufoctuaing Hence tthe name is ffeld- re ammable
7HYGAs ae ogrommed using o
logic civcult aioqram
hodwae Proammable langtuag HD)
C
e n a
Bouce Code

- unlt ke ASTC whc Con Perfm a zfng le specifie funoio

fo time othe chip and

lipe FPGAs Con be refrogoed
-to perfom a di fren t functton
FPOA Anchitecte
logi B/ock.

Switeh block.

Irter Connecf

Pads
Dbo
 t
has TWee main Comnporents
& ConfiguOtle logic SlockA CclB).
togic Elemert (Les)
Logfc Blocks C LB)

nkrconhections (Switch Box

veical and hatzontot
In PUutloutput Block Ilo Pads
a Cohnpkx
*
SUPpOse I Uwant to degn and Smplement
des tqnC Ful Adode)
The deslqh has divided in to Small sub tunctons and
eoch sub tunction is Smplemented by usng one logic
bock
Soto get requied function,oll
the dered des'grs
modules ae
Cimplementcd the function În logc Llockz)
necd to be Conne cted together, this Con be done by
using ProgRamming metthod

cne bagic building block% db

I FP&A logic bloc Ks
the
P6AS.They ae Programma ble, meaning thoat their
th

funct fon can be changed by corfigoing the FPaA

The FPGA logfc block în the diagYom Contains the
fol6using component.
* Look Up talelT is a memoy arYay that
ClUT): The
Can stãe a look uP toble d logic functim. This allows
the FrGA Logic Lock to,implement any ogle functon
ot op to a certotn numbes inputb. o
etrtPut
*Mutiplexer CMUX):The MUx Selects beten the
Dt -the LUT and the ctput
o a
dip-Hor. Thi allow%
to fnplement both Combina final
The FPSA logic block
amd Sequertiat
loic.
 D
Htpflop TheD Hir flor stöes the output tt the
MUx ThiB alowp he FP6A kogfc block to implemevd
Sequenttal lo gc. civcuils

B
UT Solp
FF
ABCDl
Pst 6
îngtnuctims )
CIk

Cogc Blcck
Y
heed to douwnload the "BLT STREAM Hle
we to
an aA,
Programning FPGA is Enon as cotigwaton
BITSTREAM, So
* At the LUts ahe Cmtfased uzingthe
that -trey Contafn the ccet Valuez to im plenment the
Beolegn toqíc
Y
Hore by Programmfng we send to tne Computer insttion

switch Box
Connecta fo VertiCat and haízonta intyConect
%

Heye fs an exampe c
hs a saiteh tox udks
•Each Switch ox irter Connect Point hag 6 Pos trontistos
Pas tionsztös ahe dven by comigsatfon memay cets
lbinary data pass transisto e on
and oot
TO
Conique the Proqrammable outing, let uz look at
how the moutng circutt wths
y
Take the suwitch block this block Contro
the Connectro
bettween foua hoizontat and four vertical
L
The dfamend ghaped channel.
och Potehtal inerCatnert
site.
 Tside the Qwitch
a
Ly block there is síx Paxz tyans istox
Suoitches initictY all t
co eoch fz
The gofe in Put boch switch Control by the
CEx. tbit E)
Cutput ob t bttvegistey

The follouoing is
i8 a
brief Eplanation t how the
FP6A (ogic blcckK wdks
(. The fo fnput pins CABCD) ae comnecte d to the lUT.

2 The LUT Stoes a

look logic functi onz
op
to ble co

e
3. The MUY elects between the Cutput the LuT and Ob

o
output ot the ip oP.

4The output d the MX 3Stoe d in the tip- floP.

s The cloch Snput CCIk) iB used to ynckroni 2e the
OPeYatfon t the ip plo p.

By Confiquafng the lut and the MUx,the FPGA

Coqsc blo ch used to împkm ent any logic functon.

can be

This. mahes FPGAS VeYy Versotile

evces thot Can be use
to impe ment a wide vaiety o digital cicuit
some Examgles db how FP6A logk blocks
Here oe
Cah be used.
• TD implement e simple ANDthe lUT wOuld be
gade,

Con
ighed to Bte tthe teth table fo the AND
function. The yUx would be Contigwedto zelect the
Out put db the lur
•TO implement a sequertiol circult, suchaz a Counter,
the Lur woul d be Contiqsed to stie the loglc fuhctio
tote Mux wou td
foi
the Count transien, The be
oo
Configue d to zelect Letueen the output the LUT and
the UT ond dhe op theff
o do
the output
c to
The locK input would be used synchrze the
Cpaot fon ot
the Coute
 FSA Design
Po
FfoA Dsign prosA

*lhe Process rt onfiqoong a

design onto n
rat
Can be byohen Snto several stoges
* A TYPi Col ComPudey aided design CCAD) ow fo fP6A
would includ e Soffwcne tootc fo the task uch o
Initial design cnty
toqic ynthests
plocement and Pating
-and Proqramming orrto
the Fr6A
* The CAb tools cðhe
esent iot t Configsfng
circutts rrto FPGAS the
The populoa
tools core
ISE from
[ins xi

Modelsôm fom Ment ophic

Qucatus Softwce
fm Atfea
FPGA Design Plow

Deslgn speciticotion)
J
Tmfementatn yfunctonal veyifcotion
fn "VHDi/verilog"
Logic synthesis
Tecnolog4 Netlist fozt- sytheis smulbctiom
MAFP9, Placingd
Tiring simutin
Fatin9
Bit steOm Pragiomming FPaA
by daunlong
the Bt stream
Decigrng
pecignong an PGA inVolves the folloofng stoges
If Ít oh/ match yequire
ments
then g0 fa next
ctage eLie maPe CÒletions
Deslgn specifiCotions
aeiqn entry uch as
y
There didfevent teclhniques
e to
Schematlc bosed
HDL and Combination ob both

Behavidal simulotion
o
smulotim and t fx
* This is the st ste

Pexfamed befåe synttesi Pocess o

verify PTL Cace
as intende d
is fuettonmg
and comprm thot the lesfgn
desiqney to chonge the tHDL Code
IH allows the
any requYe d tunctionalty
synthesis
vevilog/vHDL
VHDL
pro esb which tyanelates
* I fs the Code
81 Verilog Coole into a device netlist tmat synthesA
uu cotth legical elements
iea Complete cncit NGC File
Cgotes, (tp tePs, ete) fa the des'gn
Syttesis is the Process wtu chec
k Code and stox
analyze the hieYoCY do de stqn. shich
ensae tht the
sign ib optimizcd få the achitcctae. qeneme
soved in nGC CNgtfve
* The eswting nettist i
cincult) fle.
o
Implementotion CMapping.Plaing. &Poutin)A
TYansate
fle
aNA NGC

Map tnenslate
CNGPRild
• Placed
ond Poute
NGD
le
 Tanc la te
Omd
DYanslote all tthe inpt netist Qnd
Proceb% Combines
Thiy intdmation s
Cnshonts fn to a togle sign ile.
de

oved ax a NGDCNotve generc Dota boe)

e

Defining the Consbhoints fn notting at, ascgng

Pih,
"the pats inthe desiqn to physiCal elements (ie tng
Specity
suoitehes, ete. )dt togettd devlce and
D26 the tgeted
te sted in
tfre yeqiements o
the design. ohich is
UCF CUUseY Con styants Fle)
NGD
MAP Trasate
-MAP Pcesx devide the dhole crcut FP6A MAPingSTAJ
Into logiCal e (eentz into ib dockz
NCP
sUCh tht they Can it into the
FP6 A l6gic Hoc hz:
loqrcat de
ine d by the NGp Fle into
Map Psocess fft the Loqg'e Block- CLB
-tgele d FrGA elements C Contiqwable
the n NCp

tnpt ttput bac hs CIlo BlocK3) and geneYotes

CNotve cicuit descyfpti on)
ik
ma ppe d m

* twhich Physically rereents the desgn he

Canponents dt FPGA

Place and Poute.

place MaPPed Nep file
The plale and Youte Proce38 tofres
map Procexs PGA MaPpingSA)
the ss Hoc kt fyom the

bocK accoding to the PoUted NCp fleiS

into log
Contafns nd Cnnec t the
lo9 fe bloc
K,
*
The mapPed ncD le I the input to
te cna

Process amd 3et the Youcted out Put

o% NCD fle
Cendro Grnslst te Yothg înfomatto
 Post- synthess Simulation Tunctional imulaion
the logic
x
Functonal Snulction ives infomatim abot
efevot ien ce ttie crcuit
Desger Can treyify the tuncHonality
6
the
desgn eUsing Po Ces the -bansate Proces,
afer .
not as Exfc ted, then the
A
tHhe functionalit
*
It ges in the and ageia oe
de sigrer has to nade Chah
tollouotthe destgn totw tePA
Stotte timng amolsik
This Can be ane affer "MAp'
&
PAR PYoceB Poot

MAP timi nq Ye Pdt tits siqnat path de loys the

e
de sgn devfved frtn the ('gn logic.
Bit stream
* NOw the de sin the fP6A utthe
must be load ec on

a tamat. So that the

design must be Conveted to
accep
fPGA an it
The BIT GEN Pr gnan îb deal wrth this Conevpion
then gVen to the BITGEN Pogr
The YOuted NCD file ?n
G]ie), ohich can be
bit stream
a C:
to geneYok
Confiquae tue -tooget fP6A dlevice.