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14-Addressing Modes-30-01-2023

The document discusses computer instruction format and types. An instruction contains an opcode and operands, specifying an operation and sources/destination. Instructions vary in number of operands and addressing modes. The document provides examples of instruction formats and categorizes instruction sets based on operation, operands, and addressing modes.

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14 views25 pages

14-Addressing Modes-30-01-2023

The document discusses computer instruction format and types. An instruction contains an opcode and operands, specifying an operation and sources/destination. Instructions vary in number of operands and addressing modes. The document provides examples of instruction formats and categorizes instruction sets based on operation, operands, and addressing modes.

Uploaded by

akum2302
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BCSE205L - Computer Architecture and Organization

L T PC
3 0 0 3

Dr. M. Bhuvaneswari
Assistant Professor Senior Gr.2
School of Computer Science and Engineering
Vellore Institute of Technology, Vellore
[email protected]
Instruction and its format
• A computer performs a task based on the instruction provided.
• Instruction is a statement by which the operation of CPU is
determined.
• An instruction comprises of two parts: Opcode, and Operand.
• Eg.:
• ADD R3,R4 – R3=R3+R4
• ADD LOCA,R1 – LOCA=[LOCA]+R1
• ADD R1,#10 – R1=R1+10
• MOV R1,R2 – R1←R2
• Opcode specifies the operation to be performed.
• Various categories of instruction – data transfer, arithmetic and logic,
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control, I/O
Instruction and its format
• Operands - input for the operation.
• Specifies the source(s) and destination of the operation.
• Source operand - Immediate data, register name or a memory
location.
• Destination operand - register name or a memory location.
• Number of operands varies from instruction to instruction.
• Three-Address Instructions
• ADD R1, R2, R3 R1 ← [R2] + [R3]
• Two-Address Instructions
• ADD R1, R2 R1 ← [R1] + [R2]

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Instruction and its format
• Number of operands varies from instruction to instruction.
• One-Address Instructions
• ADD M AC ← [AC] + M[AR]
• Zero-Address Instructions
• ADD TOS ← [TOS[ + [TOS – 1]
• Instruction format example

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An Instruction Example
• Let say we have an ISA with 32 bit instruction only.
• Decoding process is easy – Fixed size instruction.
OPCODE Destination Register Source Register Memory location

32 bits
4 bits 5 bits 5 bits 18 bits

• 16 instructions can be represented by the opcode field (0000-


I1,0001-I2...)
• 32 registers (each can store 32 bits information) – 5 bits to address
the register uniquely. (00000-Ro,...,11111-R31)
• 218 uniquely addressable locations in the memory.
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An Instruction Example
• Let say we have an ISA with 32 bit instruction only.
• Decoding process is easy – Fixed size instruction.
OPCODE Destination Register Source Register Memory location

32 bits
4 bits 5 bits 5 bits 18 bits

• 16 instructions can be represented by the opcode field (0000-


I1,0001-I2...)
• 32 registers (each can store 32 bits information) – 5 bits to address
the register uniquely. (00000-Ro,...,11111-R31)
• 218 uniquely addressable locations in the memory.
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An Instruction Example

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Instruction Set
• The collection of different instructions that the CPU can execute is
referred to as the CPU’s instruction set.
• Instruction Set is categorized into types based on
• Operation performed
• number of operand addresses
• and addressing modes.

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Instruction Set Category
• Based on Operation
• Data movement instructions: Move data from a memory location
or register to another memory location or register without changing
its form.
• Memory : LOAD, STORE, MOV
• I/O Instructions: IN, OUT

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Instruction Set Category
• Data processing instructions : Arithmetic and logic (ALU)
instructions. Changes the form of ne or more operands to produce a
result stored in another location
• Arithmetic : ADD, SUB, MUL,...
• logic Instructions: AND, OR,...

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Instruction Set Category
• Control Instructions : Any instruction that alters the normal flow of
control from executing the next instruction in sequence.
• Conditional : JNZ, JZ, JNP, ...,
• Un Conditional: Jump

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Instruction Set
• The collection of different instructions that the CPU can execute is
referred to as the CPU’s instruction set.
• Instruction Set is categorized into types based on
• Operation performed
• number of operand addresses
• and addressing modes.

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